I just pushed my design through wafer.space and it took 10 hours. Almost all of the time (8h47m) was spent in esd and sab decks in KLayout DRC. Can this be accelerated? It would be nice to have just to wait for an hour to see the final GDS.
Github issue: https://github.com/wafer-space/gf180mcu-project-template/issues/76#issuecomment-5248976075
Thanks,
Andreas
Title: KLayout DRC: esd and sab decks each take 4+ hours on a full-chip 0.5x1 padring design Body: Ran the full LibreLane flow (make librelane) for a custom design on the 0p5x1 slot (GF180MCU, gf18...
I can't say without looking at the layout and running the check for myself.
I don't recall the ESD and SAB decks taking up much time in other designs. There shouldn't be much SAB in the layout except for the ESD devices. So it may be something unique to this design.
I'll get back to the issue on GitHub once I've had time to investigate further.
@Leo Moser (mole99) Thanks for checking (I saw the comment on Github). I am using my own flake.nix (IHP and Skywater tapeouts, lots of other stuff, all pristine Nix without binary cache) and am currently investigating. I will report back when I find out what the reason was.
You can find the changelog for KLayout here: https://www.klayout.de/development.html#0.30.10
The important point is Bugfix: #2339 Ruby ReportDatabase merging can lead to internal error which is required by our DRC runner.
Ok, I'll upgrade the klayout, librelane, openroad and yosys (new version contains a fix for an error I reported) nixpkgs and point my flake.nix to it. Thanks for helping me out.(edited)
Ok, it works. My run was 35 minutes now (due to heavy compilation on the same machine). But now it reports DRC violations, and if I am to believe my friend Claude, this is not due to my design but wafer.space's sealring: https://github.com/wafer-space/gf180mcu-project-template/issues/77 Maybe you can tell me whether I'm right here, @Leo Moser (mole99) ?
Follow-up to #76 (thanks again for the KLayout version fix — precheck now runs in ~20min instead of 10h25m on our end too, confirmed). While re-running the full KLayout DRC on the same chip_top.gds...
gonsolo
Ok, it works. My run was 35 minutes now (due to heavy compilation on the same machine). But now it reports DRC violations, and if I am to believe my friend Claude, this is not due to my design but wafer.space's sealring: https://github.com/wafer-space/gf180mcu-project-template/issues/77 Maybe you can tell me whether I'm right here, @Leo Moser (mole99) ?