wafer.space Community - Creating masks ourselves

I was talking to a small foundry about pricing for their 350 nm node recently, and some of the cost was NRE (to create the mask etc.) Got me thinking about if we can reduce mpw costs with open nodes if we do some of this work ourselves? even technically it would be cool to have the mask preparation flow be open sourced for open PDKs. Did some reading online and looks like usually foundries do this themselves as it's highly specialized and they don't want to give manufacturing tool specific data out but it would be cool to still have this option available for open PDKs. Does anyone have any info about this?

11:39 a.m.

looks like there's also a standardised mask set format spec https://store-us.semi.org/products/p04400-semi-p44-specification-for-open-artwork-system-interchange-standard-oasis-%C2%AE-specific-to-mask-tools

(1) we don't even have enough info about the open process to generate the mask. Sometimes we don't even know what those masks are. (2) Even if we did, there is no way the foundry would even let you ... a bad mask could cause issues bringing their production line down.

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12:29 p.m.

ATM they even wince at minor antenna violations ... so I don't see them just accept raw masks blindly.

tnt

(1) we don't even have enough info about the open process to generate the mask. Sometimes we don't even know what those masks are. (2) Even if we did, there is no way the foundry would even let you ... a bad mask could cause issues bringing their production line down.

that's interesting, i never thought about how design mistakes could bring down a production line, but makes sense.

rahulbhagwat

that's interesting, i never thought about how design mistakes could bring down a production line, but makes sense.

You also need to be aware that the shapes you design are not the ones that will be put on the mask. The shapes will go through OPC before put on the mask to correct for the 2D (non-linear) low-pass filtering of lithography. You don't have the information to be able to do the OPC and I don't think you will be able to get that information.

Optical proximity correction

Optical proximity correction (OPC) is a photolithography enhancement technique commonly used to compensate for image errors due to diffraction or process effects. The need for OPC is seen mainly in the making of semiconductor devices and is due to the limitations of light to maintain the edge placement integrity of the original design, after pro...

12:43 p.m.

BTW, although it is called optical proximity correction it also takes into account other processing effects like etch. (edited)

12:44 p.m.

And even if you would be able to do it, I don't think a fab will ever except masks not from a qualified mask supplier. (edited)

The OPC aspects would likely be among the least secret aspects there, going by that the wavelength of light is known, AFAIK the type of mask (negative/positive/phase-shift??) is documented (or was that just for sky130, not gf180mcuD?), and it takes only a few test features if done explicitly or likely just a couple dies I guess distributed well across the reticle and wafer scanned under an electron microscope being compared with the actual (post-OPC-editing) masks responsible for the studied shapes, to calibrate a model for like https://opg.optica.org/oe/fulltext.cfm?uri=oe-33-17-37229 or https://arxiv.org/html/2606.00228v1 (the latter literally has https://github.com/laiyao1/LithoGRPO linked in the abstract!)

GitHub - laiyao1/LithoGRPO: [ICML 2026] LithoGRPO: Fast Inverse Lit...

[ICML 2026] LithoGRPO: Fast Inverse Lithography via GRPO Reinforced Flow Matching - laiyao1/LithoGRPO

Both the exact exposure conditions (NA, conventional/annular/quadruple illumination) and the resist are considered trade secrets and are critical to be able to do OPC.

12:59 p.m.

resist = photosenstive layer.

namibj

The OPC aspects would likely be among the least secret aspects there, going by that the wavelength of light is known, AFAIK the type of mask (negative/positive/phase-shift??) is documented (or was that just for sky130, not gf180mcuD?), and it takes only a few test features if done explicitly or likely just a couple dies I guess distributed well across the reticle and wafer scanned under an electron microscope being compared with the actual (post-OPC-editing) masks responsible for the studied shapes, to calibrate a model for like https://opg.optica.org/oe/fulltext.cfm?uri=oe-33-17-37229 or https://arxiv.org/html/2606.00228v1 (the latter literally has https://github.com/laiyao1/LithoGRPO linked in the abstract!)

I don't see anything of substance in that repo; only shotcounting analysis.

At least to my understanding the optics themselves at least as far as needed to be understood to pull off decent inverse lithography on a process node that does not utilize any multi patterning at all, is not under so much secrecy/"trade secret" (of the genuine, warranted kind) that it has a legitimate reason to block us from knowing enough detail/nuances about how the mask shapes print, as we'd need to calibrate and then add an ILT tech to the PDK.... though I did now in the past few minutes since posting that read that the above Github doesn't yet include anything but their FastShotCounter, the ShotCounter reference baseline for that, "plus the comparison/plotting example". Though they are mentioning that they are planning to ("TODO (coming soon):" release the Group Relative Policy Optimization reinforcement-learning fine-tuning code, Flow-matching prior (training + pretrained checkpoints), Physics-based ILT reward and lithography simulator, End-to-end inference / mask-optimization pipeline, and some IMO far less necessary Datasets and evaluation scripts ... ... I particularly remembered https://www.semanticscholar.org/reader/765568c040eddfcfc17a578b3a0b82ece5223058 (arXiv:2303.08435v4), which encodes the physics of ["coherent imaging especially with single-wavelength light in linear media with no birefrigence can be appropriately modeled as complex-valued 'phasors' in place of classic intensity amplitude and will provide a good approximation to finer physical reality for tasks that are about understanding the interference pattern at the target from several independent mask openings/light paths that have been understood and their phasors calculated individually (in isolation) as long as they are all fed by the same coherent source in the situation where their combined effect on the image pattern wants to be understood"] directly into the model's mathematical structure through the "Sum of Coherent Sources Approach".

[PDF] Physics-Informed Optical Kernel Regression Using Complex-valu...

An academic search engine that utilizes artificial intelligence methods to provide highly relevant results and novel tools to filter them with ease.

Chips4Makers aka Staf Verhaegen

I don't see anything of substance in that repo; only shotcounting analysis.

Yeah I realized after that message

Chips4Makers aka Staf Verhaegen

Both the exact exposure conditions (NA, conventional/annular/quadruple illumination) and the resist are considered trade secrets and are critical to be able to do OPC.

hmmmm, I thought at least the imaging even if not the chemistry was by now no longer a real secret, it's not like they cook their steppers up in-house, or that this was so bleeding edge that a normal competitor wouldn't already have had plenty of time to try out the options themselves. Though I don't think the actual NA and illumination pattern is actually required to be known to pull off arXiv:2303.08435v4.

4:16 p.m.

But you're right in so far as that by the looks of it, we don't yet have actual runnable code published that would pull off ILT/non-classic OPC without spamming shots for the mask that the mask shop would rapidly start billing a lot extra for. Nor do we have reason to expect to get ground-truth training data of lithography prints resulting from known masks for the relevant layers, as some of those seem to be consumed too indirectly by the processing to be anywhere close enough to directly observable with even a fancy electron microscope (incl. extra element detection and FIB machining and all those) from finished dies, and I certainly don't expect the fab to hand over ground truth reference data for a major process like this one, measured between litho and those follow up steps.

From the repo you linked to you can come to following repo: https://github.com/shelljane/lithobench (and I think there is also a related paper). What I see is that the repo seems to only consider images of the printed structures in best focus and best exposure but ILT is actually mostly needed to optimize the process window e.g. shape variations over the focus and exposure non-uniformity you have in your exposure system. So when I look at that repo I get the feeling of some people want to show AI/ML can solve any problem without knowing fully the actual problem they are solving. BTW, for the open source PDKs you don't need ILT as that would make masks too expensive. You only need it for 22nm and below for 193nm litho. I don't know about EUV as I left litho group @ imec before we came to that stage.

GitHub - shelljane/lithobench: LithoBench: Benchmarking AI Computat...

LithoBench: Benchmarking AI Computational Lithography for Semiconductor Manufacturing - shelljane/lithobench

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Chips4Makers aka Staf Verhaegen

From the repo you linked to you can come to following repo: https://github.com/shelljane/lithobench (and I think there is also a related paper). What I see is that the repo seems to only consider images of the printed structures in best focus and best exposure but ILT is actually mostly needed to optimize the process window e.g. shape variations over the focus and exposure non-uniformity you have in your exposure system. So when I look at that repo I get the feeling of some people want to show AI/ML can solve any problem without knowing fully the actual problem they are solving. BTW, for the open source PDKs you don't need ILT as that would make masks too expensive. You only need it for 22nm and below for 193nm litho. I don't know about EUV as I left litho group @ imec before we came to that stage.

sky130's hand-crafted-tuned-OPC needs are the reason why we can't use the foundry standard cell local-interconnect DRC's outside of those cells; while the earlier ILT works seemed to not put as much focus on mask writer shot economy, the more recent ones like e.g. that LithoGRPO very much put in effort to not use excessive shot count. What you need for 22nm and below is multi-patterning on top of some kind of ILT/OPC tactics, because you're unable to image economic pitches even if you can squeeze desired gate widths out of a single exposure. Nothing about ILT in principle necessitates spending large quantities of mask writer shots, it's only the early works that paid zero respect to the traditional rectangle writers and effectively assumed a pixel writer if not even assuming some kind of grayscale-variable-like phase shift mask (or similar) to gain continuos control.

ILT is just closed loop automatic tuning of OPC features, at least if targeting traditional mask writers. It's just that you can't enumerate the OPC features that would be needed, for all possible affordably printable (if only you knew what mask prints that and is affordable: there is one by definition) structures, unless you're working on some highly regular device pitch (cough FinFET), so for these larger bulk-CMOS processes you either accept the excessive DRC limitations to design density from only using fixed rule based OPC features (banning printable but not-obviously-so fine structures via DRC) or you use an ad-hoc automatic feedback-loop-based algorithm to synthesize affordable OPC features for arbitrary fine structures you encounter during mask gen.

E.g. there has to be a reason why on sky130A, (difftap.2) limits custom FETs to 0.42 width but (difftap.2b) allows standard cells to use FETs with only 0.36 width.

namibj

ILT is just closed loop automatic tuning of OPC features, at least if targeting traditional mask writers. It's just that you can't enumerate the OPC features that would be needed, for all possible affordably printable (if only you knew what mask prints that and is affordable: there is one by definition) structures, unless you're working on some highly regular device pitch (cough FinFET), so for these larger bulk-CMOS processes you either accept the excessive DRC limitations to design density from only using fixed rule based OPC features (banning printable but not-obviously-so fine structures via DRC) or you use an ad-hoc automatic feedback-loop-based algorithm to synthesize affordable OPC features for arbitrary fine structures you encounter during mask gen.

That's not how the ILT term is used in the lithography world. In the lithography world the method of iterating over mask shapes variations to improve the printed image based on a model of your printing system is called model based OPC. ILT is used there for techniques that mathematically compute the mask shapes based on wanted shapes in one go. Some iteration may be done afterwards to increase manufacturability of the mask. (edited)

Where LithoGRPO seems to differ from the proprietary model based OPC tools is that for the latter sub-resolution assist features are added by rules as LithoGRPO puts them and iterates over them in the optimization phase. So the outcome looks like the outcome of the ILT techniques used in the lithography world. (edited)

Chips4Makers aka Staf Verhaegen

Where LithoGRPO seems to differ from the proprietary model based OPC tools is that for the latter sub-resolution assist features are added by rules as LithoGRPO puts them and iterates over them in the optimization phase. So the outcome looks like the outcome of the ILT techniques used in the lithography world. (edited)

Well, yeah, they use modern ML techniques to produce mask shop friendly (at least on an even level with traditional OPC) masks for the desired print, as the shot count metrics provide a horrible loss function landscape if tried to solve with vaguely similar numerical setups as the perfectionist ILTs do (which would work but can't affordably be written with the equipment mask shops want to use to produce masks for these bulk CMOS processes).