wafer.space Community - Do we need OCD IO pads for digital 3v3 design

Sounds like there might be some interest in a pure 3.3V I/O library to try to hit higher performance? It's a bit trickier than my hack method of downsizing the 5V SRAMs to 3.3V (although that worked surprisingly well) because a lot of the I/O pad device sizing is based on ESD targets. And it cannot just be "silicon verified" by doing a functional test---it needs to be zap-tested. The dual voltage I/O library does not need zap testing because nothing touching the pad itself has been modified, only internal core-facing circuits. Its ESD characteristics should be exactly like the original 5V I/O library.

I mean inputs of the dual one reached 188 MHz (and probably limit is tt infra and not pad) and outputs would be fine above 100 M given measured rise/fall time.

But outside of TT, people might still be interested. (I definitely am

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is there a disadvantage to using the OCD cells if everything is 3v3? Worse timing or power or something? I didn't realize you could use the FDs

Hmm, I could see it either way - splitting the power domains maybe reduces noise, joining them maybe increases stability through more pins? Not sure which is preferable.

Leo Moser (mole99)

But outside of TT, people might still be interested. (I definitely am

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I meant that more than likely the IO themselves already go way above what we measured in TT and getting non trivial logic in gf180 meeting 200 MHz is quite the challenge, so it's not like the IO are a giant limiting factor ATM.