

Error in extracting node gf180mcu_fd_sc_mcu7t5v0__fillcap_64_40578/a_3260_375#
Bad Device Location at 585660,629620
Couldn't find device at 585660 629620







.tar.zst if you want, including the script that did that and the git commits involved in it happening.







drc off
gds read {/tmp/tmpk8ys6nzm/chip_top.klayout_editing_03.gds}
load {chip_top}
select top cell
port makeall
ext2spice lvs
extract do resistance
extract all
ext2sim labels on
ext2sim
extresist simplify off
extresist all
ext2spice extresist on
ext2spice resistor tee on
ext2spice cthresh 1
ext2spice subcircuit top on
ext2spice hierarchy off
ext2spice
quit -noprompt




.t0 .t1 and kill the original with the # suffix) and compute the resistance between them.









.nodeset into the DC operating point run to at least be able to simulate select events from the chip state they would happen in.























/nix/store/qwianildz86dh9yhmjbj250a7qjlp7pk-magic-vlsi-8.3.581/lib/magic/tcl/magicdnull has started writing to .res.ext within about 12 hours oro so.














chip_top.res.ext file. So far the only content in the .res.ext file is the VSS net, which has around 2 million nodes in it. So it is slow but appears to be methodically making its way through the extraction.

ResTriangleCheck Is searching for triangles in an undirected graph, right?
That is O(n^(3/2)) not O(n^2); I'll see about fixing that aspect in a few weeks if you remind me.

(log2(n))^2 worse at most if not using hash table base.
O(n) than naive O(n^2) (to a worst case of O(n^1.5) aka O(n^(3/2))) by:
1. As resistors are undirected edges, roughly presume we just want each resistor in both directions in any index structures (minor improvements can later be made).
2. Create an index giving us a list of target nodes for each source node (the resistor metadata is carried as auxiliary data with each list entry).
3. If needed for some access efficiency use a separate index (otherwise use the same and keep a tuple of (list((target_node, resistor_identity_metadata)), length(that_very_list))) to quickly look up how much fan-out happens from grabbing that list from a given key into the first index.
4. Iterate through the list of edges.
5. For each edge, look up both the first and the second node of that edge in the length-index (the second index, from 3.) and decide which one has less fan-out.
6. Look up the one with less fan-out in the first index (from 2.) to get the worst-case-optimal choice of what the second edge is and what the third edge will be for specifically the current iteration (first edge) of (4.).
7. Screen each such-fetched triangle node-triple, specifically the two nodes still dangling (i.e., the non-chosen one from the first edge and the target node of each entry of the second edge), against a hash table or similar set membership test data structure to spend only constant time on each candidate of the third edge (this I think is currently being done since the upgrade to O(n^2); the major trick is just to dynamically choose the less-costly vertex aka join-order for each first edge).
8. You have successfully completed the task of enumerating all triangles in at most O(n^1.5) time.
I'll see to get profiling up so I can hopefully run PEX against a similarly edited GDS of the TinyQV quarter cell submission that "only" has 4 VSS and 4 VDD bond pads and is, well, a quarter the die area (usable area not just filled with power rings/IO cells is smaller), in hopes of that GDS being large enough to exercise poor scaling but small enough to not take as many hours to even just load (such that we could reasonably use it for full profiling runs in the coming performance/throughout enhancement updates I hope to contribute greatly to).
1
8.3.645 and am running on tinyqv_quarter_label_flattened_01.gds (and I choose a cutoff of 0 for the capacitance as that happened only later and I figured I'd rather get this done now and let Xyce worry to possibly threshold that rather than erase the smaller capacitances ahead of it when magic writes out the extraction in the desired spice netlist format) currently with a cycles perf record running with stack tracing using said frame-pointer's; I confirmed it works nicely in KDAB's hotspot for me. Might have to adjust source file search path I guess, will see in a bit.
Figured I'd upload the gds and also the edited but not yet flattened gds here, as they're small enough when compressed.
extEnumTilePerim (tclmagic.so) and below.extEnumTilePerimextBasicOverlap instead of extBasicCouple (the latter the direct parent of extEnumTilePerim).








git clone git://opencircuitdesign.com/magic)









.ext file output is an intermediate form, and all the hard work is done to get to the intermediate form (ext2spice is quick and easy), then the hierarchical format also has the benefit that from the intermediate .ext form, you can quickly get any netlist for any cell in the design, with or without parasitics, without having to go through the extraction process again.



resis/ResMakeRes.c line 395.

cmp assembly instruction.
0.5x0.5 TinyQV flattened gds. I think there was some tool to bundle all the files needed to make unwinding work for you, but I'm sure I'll find a decent way to make it viewable in KDAB's hotspot for you (including decompilation view!) until then.
I'll plan to send you a .tar.zst and necessary instructions for how to feed the data to hotspot via wormhole as discord DM; let me know if that's a problem.
malloc-spam goes, KDE's heaptrack (from the same author as KDAB's hotspot) has done wonders for me when I used it on some photogrammetry/structure-from-motion toolchain TU Darmstadt's MVE.
Small commits like https://github.com/namibj/mapmap_cpu/commit/54076e35bc99ae882672e91b28b8308d681898e7 (heaptrack), https://github.com/namibj/mve/commit/09c252dea56d2e4d78993ee6e0fc5663821d8509 (hotspot), or https://github.com/namibj/mapmap_cpu/commit/fc6ea70ddccfc08f0768cf6f530fe13d179f88ad (iirc this one was highlighted by heaptrack for suspicious allocation intensity, then hotspot was used to get a quantified understanding of how bad it seemed to be to try and estimate how much whole-program speedup could be reasonably expected to be attained, before I looked for a suitable (smol, easy, compatible licence) concurrent union-find library to "easily" vendor into the project and swap out the BFS implementation of the connected-components task for a union-find one. See below for excerpt of the changed file that should make obvious how this kind of problem could be surfaced by heaptrack.), are representative of the impact I managed with those 7 years ago.
/**
* A complet contains a partial component: a list of node, its temporary
* component ID and the ID of seen other complets
*/
using complet = std::tuple<std::vector<luint_t>, luint_t, std::set<luint_t>>;
tbb::concurrent_vector<complet> accrued_complets;
perf record's recording.
It's CPU cycles spent while executing the process in user mode.

Bad Device Location at 210074,478892; it lines up nicely with what seems like it could be a device's bottom left corner, and has that 5/1 scaling applied that magic spoke up at the beginning of the log.
hotspot 1.6.0; the .perfparser pre-digested recording comes soon. It's processing./usr/libexec/hotspot-perfparser)






tinyqv_quarter_label_edited_01 completed on my desktop in just under two hours. I did not get a crash condition. I did, however, encounter two instances of Missing rptr at (...), indicating an attempt to access a resistor structure that had been previously freed, and a bunch of Missing substrate conection of device at (...) which remains to be debugged. I did not get any Bad Device Location errors.
PDK_ROOT=realpath gf180mcu_pdk PDK=gf180mcuD scripts/extract_spice.py /home/namibj/Downloads/tinyqv_quarter_label_flattened_01.gds --cthresh 0 --subcircuit-top --hierarchy-off


Missing substrate connection means that magic could not determine what subnet a device's substrate (or bulk terminal) connects to, so while it does not exactly invalidate the netlist, it means that some devices will have a substrate connection to the default, which would be the label at the pad for one of the VDD or VSS pins, and not somewhere deep inside the substrate's resistor network where it should be. The final output SPICE might be digestible by Xyce. Not sure how ngspice will handle a 2GB netlist.
























nfet_03v3_nvt and hit approximately as (in-)accurately as the regular process corners (ff/fs/sf/ss) already are?
I'd try to make it for this tt experimental shuttle at least to get the MCML VCO + NRZ serialiser completed drawn, and I'd quite like to use them in the upper level of the D-latch DIV2; bias current is externally supplied anyways and should cover a lot of potential variation, it's only really the strength of the memory pair vs. the input pair that really matters due to the tail current source so yeah...
Honestly I am severely surprised they just left it out? Completely?
I'd think we should at least get some etest data, that has to exist, right?
nfet_03v3_nvt device structure that doesn't extract.nfet_06v0_nvt and the nfet_03v3models.)


nfet_03v3_nvt? It did not exist in the original GF PDK. It probably exists in other GF180 processes, where the model might even be similar enough to use as a placeholder until we can characterize the device ourselves. Getting GF to open source that model is a separate question, though.
nfet_03v3 and nfet_06v0 and nfet_06v0_nvt under presumed-same process corner and with sufficiently similar probing parasitics should allow narrowing in these uncertainties of the fairly-naive extrapolation into this missing model "corner"; it'd probably be functional after that.
We already have all the sibling models in the PDK, after all; I don't see what beyond etest qualification ground-truth is missing to properly fit that model corner....
nfet_03v3_nvt should not have parameters s_sab and d_sab. Those parameters exist only for the "drain-side (un)salicided" devices which have the suffix _dss. The dss devices are very different and the nvt device should not be derived from them.


nfet_03v3_nvt should not have parameters s_sab and d_sab. Those parameters exist only for the "drain-side (un)salicided" devices which have the suffix _dss. The dss devices are very different and the nvt device should not be derived from them. 

nfet variants, with the goal being that if one can at least give decent estimations for the range of values that would be plausible/realistic to have there given the other nfet models, then the monte carlo tactic would allow testing if across the ranges of realistic parameter values, the circuit in question would nonetheless stay functional (even if perhaps somewhat derated from the plans), which would allow using it quite liberally in the ttgf0p3 analog test die that goes in Run2.

nfet_03v3_nvt? It did not exist in the original GF PDK. It probably exists in other GF180 processes, where the model might even be similar enough to use as a placeholder until we can characterize the device ourselves. Getting GF to open source that model is a separate question, though. 

nfet_06v0_nvt is only a singular bin..... also doesn't appear to have any missmatch modeling done to it.NAT mask layer on the upcoming runs, but I guess it's easier than modifying the PDK tooling to get rid of it and change what exdact process is run at glofo.)

W/L= 10/1.8; VT0 (@Vds=0.1V,Vgs at Ids maximum Slope, Vt0=Vgs_intercept-0.5*Vds)) after all....

NAT mask layer on the upcoming runs, but I guess it's easier than modifying the PDK tooling to get rid of it and change what exdact process is run at glofo.) 
MVNVT.... sadly https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_04_2.html smells like NDA wall to me
NAT GDS layer just tells the mask generation to not put implants on that transistor ...

NAT GDS layer just tells the mask generation to not put implants on that transistor ... nfet_1v8_lvt.
05v0_nvt device in sky130 works quite well as a cascode on top of a normal 3.3V nFET, and the gates of both devices can be driven with the same voltage, avoiding the need to set up a cascode voltage on the n side.

05v0_nvt device in sky130 works quite well as a cascode on top of a normal 3.3V nFET, and the gates of both devices can be driven with the same voltage, avoiding the need to set up a cascode voltage on the n side. 