26-Apr-2026 21:21:23 | INFO    | Your Klayout version is: KLayout 0.30.7
26-Apr-2026 21:21:24 | INFO    | ## Generating template with for the following rule tables: ['metal1.drc']
26-Apr-2026 21:21:24 | INFO    | ## Your run dir located at: /build/drc_output
26-Apr-2026 21:21:24 | INFO    | ## Generating template with for the following rule tables: ['metal2.drc']
26-Apr-2026 21:21:24 | INFO    | ## Your run dir located at: /build/drc_output
26-Apr-2026 21:21:24 | INFO    | ## Generating template with for the following rule tables: ['metal3.drc']
26-Apr-2026 21:21:24 | INFO    | ## Your run dir located at: /build/drc_output
26-Apr-2026 21:21:24 | INFO    | ## Generating template with for the following rule tables: ['metal4.drc']
26-Apr-2026 21:21:24 | INFO    | ## Your run dir located at: /build/drc_output
26-Apr-2026 21:21:24 | INFO    | ## Generating template with for the following rule tables: ['metal5.drc']
26-Apr-2026 21:21:24 | INFO    | ## Your run dir located at: /build/drc_output
26-Apr-2026 21:21:24 | INFO    | ## Generating template with for the following rule tables: ['metaltop.drc']
26-Apr-2026 21:21:24 | INFO    | ## Your run dir located at: /build/drc_output
26-Apr-2026 21:21:24 | INFO    | ## Generating template with for the following rule tables: ['via1.drc']
26-Apr-2026 21:21:24 | INFO    | ## Your run dir located at: /build/drc_output
26-Apr-2026 21:21:24 | INFO    | ## Generating template with for the following rule tables: ['via2.drc']
26-Apr-2026 21:21:24 | INFO    | ## Your run dir located at: /build/drc_output
26-Apr-2026 21:21:24 | INFO    | ## Generating template with for the following rule tables: ['via3.drc']
26-Apr-2026 21:21:24 | INFO    | ## Your run dir located at: /build/drc_output
26-Apr-2026 21:21:24 | INFO    | ## Generating template with for the following rule tables: ['via4.drc']
26-Apr-2026 21:21:24 | INFO    | ## Your run dir located at: /build/drc_output
26-Apr-2026 21:21:24 | INFO    | ## Generating template with for the following rule tables: ['contact.drc']
26-Apr-2026 21:21:24 | INFO    | ## Your run dir located at: /build/drc_output
26-Apr-2026 21:21:24 | INFO    | ## Generating template with for the following rule tables: ['geom.drc']
26-Apr-2026 21:21:24 | INFO    | ## Your run dir located at: /build/drc_output
26-Apr-2026 21:21:24 | INFO    | Running Global Foundries 180nm MCU /nix/store/mx9bz1vdns0id1l860p477bkgdwskfa8-aegis-tapeout-luna_1/luna_1.gds checks on design metal1 on cell AegisFPGA:
26-Apr-2026 21:21:24 | INFO    | Running Global Foundries 180nm MCU /nix/store/mx9bz1vdns0id1l860p477bkgdwskfa8-aegis-tapeout-luna_1/luna_1.gds checks on design metal2 on cell AegisFPGA:
26-Apr-2026 21:21:24 | INFO    | Running Global Foundries 180nm MCU /nix/store/mx9bz1vdns0id1l860p477bkgdwskfa8-aegis-tapeout-luna_1/luna_1.gds checks on design metal3 on cell AegisFPGA:
26-Apr-2026 21:21:24 | INFO    | Running Global Foundries 180nm MCU /nix/store/mx9bz1vdns0id1l860p477bkgdwskfa8-aegis-tapeout-luna_1/luna_1.gds checks on design metal4 on cell AegisFPGA:
26-Apr-2026 21:21:24 | INFO    | Running Global Foundries 180nm MCU /nix/store/mx9bz1vdns0id1l860p477bkgdwskfa8-aegis-tapeout-luna_1/luna_1.gds checks on design metal5 on cell AegisFPGA:
26-Apr-2026 21:21:24 | INFO    | Running Global Foundries 180nm MCU /nix/store/mx9bz1vdns0id1l860p477bkgdwskfa8-aegis-tapeout-luna_1/luna_1.gds checks on design metaltop on cell AegisFPGA:
26-Apr-2026 21:21:24 | INFO    | Running Global Foundries 180nm MCU /nix/store/mx9bz1vdns0id1l860p477bkgdwskfa8-aegis-tapeout-luna_1/luna_1.gds checks on design via1 on cell AegisFPGA:
26-Apr-2026 21:21:24 | INFO    | Running Global Foundries 180nm MCU /nix/store/mx9bz1vdns0id1l860p477bkgdwskfa8-aegis-tapeout-luna_1/luna_1.gds checks on design via2 on cell AegisFPGA:
26-Apr-2026 21:21:24 | INFO    | Running Global Foundries 180nm MCU /nix/store/mx9bz1vdns0id1l860p477bkgdwskfa8-aegis-tapeout-luna_1/luna_1.gds checks on design via3 on cell AegisFPGA:
26-Apr-2026 21:21:24 | INFO    | Running Global Foundries 180nm MCU /nix/store/mx9bz1vdns0id1l860p477bkgdwskfa8-aegis-tapeout-luna_1/luna_1.gds checks on design via4 on cell AegisFPGA:
26-Apr-2026 21:21:24 | INFO    | Running Global Foundries 180nm MCU /nix/store/mx9bz1vdns0id1l860p477bkgdwskfa8-aegis-tapeout-luna_1/luna_1.gds checks on design contact on cell AegisFPGA:
26-Apr-2026 21:21:24 | INFO    | Running Global Foundries 180nm MCU /nix/store/mx9bz1vdns0id1l860p477bkgdwskfa8-aegis-tapeout-luna_1/luna_1.gds checks on design geom on cell AegisFPGA:
26-Apr-2026 21:54:06 | ERROR   | Klayout DRC run is not clean.
26-Apr-2026 21:54:06 | ERROR   | Violated rules are : {'M1.2b', 'V2.2a', 'M2.1', 'M4.2a', 'M1.2a', 'V1.1', 'M1.1', 'M3.2a', 'V2.1', 'M2.2a', 'M3.1', 'V1.3c', 'V1.2a'}