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Between 2026-06-30 11:59 p.m. and 2026-08-01 12:00 a.m.
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.nodeset's to cover all multistable/regenerative-feedback node voltages,
conparam entry that happens after the mosfet:gainscale and mosfet:nltermscale entries, which will be essentially the output conductance of the current-type B-source which hard-forces the stateful digital logic cell's internal node voltage to the reference DC static voltage of the desired internal state of that particular cell, and is ramped from a very high conductance (strong but still sufficciently numerically behaved especially when it comes to transitioning out of the forced state; I'd probably just start with 1 siemens for any vaguely normal CMOS SCL internal nodes) down to literally 0 (which will have it be open-circuit at transient sim runtime). The parameter names legal to put into conparam are the same ones that are also legal to .STEP (the docs for how to casually do .STEP are far far easier to approach/read/understand than the fancy continuation stuffs).
.options loca stepper=1 predictor=1 stepcontrol=1 could be semi-necessary to (properly/reliably) handle the effects of combinatorial loops through the (non-transparent at the time of the continuation solving!) flip-flops; if the continuation DC OP point solve ahead of the transient sim itself takes too long it'd be worth testing whether it's sufficciently robust with the tangent predictor 0 and thus the downgrade from the arc-length continuation stepper=1 to stepper=0.
Though I guess maybe it has to do continuation over the output resistance and push that out to near-infinity in the continuation solve process (default is like 100 exa); the specified parameter constant value applicable outside of the special circumstances in which the LOCA does continuation on it, will need to be a sentinel (I'd suggest exact 0 or "anything negative"), as it shall be as non-interacting and as sparsified-away by the linear solver and all as possible (it's not a problem because the discintinuity doesn't happen while a non-linear solver tries to solve the system of equations and could have called the behavioral function with node voltages/branch currents far from anythign physical, because that's just discintinuos in a parameter, and that parameter doesn't change during any transient time integration...).
Overall the idea I'm proposing is to use gate-level digital sim (post-techmapping (and any retiming and other such intrusive changes to the logic) verilog-sim basically 
) to fast-forward to an interesting moment, snapshot all stateful state, map that against pre-computed DC op points of the cell library, use the LVS matching provisions to match that state to post-PEX SPICE node identifiers, emit a spice file to-be-.include'd full of those continuation-capable cell's-internal-node-forcing B-sources (test if things are faster when forcing combinatorial nets as well, or if the additional effort expended negates the faster convergence; .nodeset is likely cheaper for those though it's just not reliable), and start the .tran sim..nodeset's to cover all multistable/regenerative-feedback node voltages,
conparam entry that happens after the mosfet:gainscale and mosfet:nltermscale entries, which will be essentially the output conductance of the current-type B-source which hard-forces the stateful digital logic cell's internal node voltage to the reference DC static voltage of the desired internal state of that particular cell, and is ramped from a very high conductance (strong but still sufficciently numerically behaved especially when it comes to transitioning out of the forced state; I'd probably just start with 1 siemens for any vaguely normal CMOS SCL internal nodes) down to literally 0 (which will have it be open-circuit at transient sim runtime). The parameter names legal to put into conparam are the same ones that are also legal to .STEP (the docs for how to casually do .STEP are far far easier to approach/read/understand than the fancy continuation stuffs).
.options loca stepper=1 predictor=1 stepcontrol=1 could be semi-necessary to (properly/reliably) handle the effects of combinatorial loops through the (non-transparent at the time of the continuation solving!) flip-flops; if the continuation DC OP point solve ahead of the transient sim itself takes too long it'd be worth testing whether it's sufficciently robust with the tangent predictor 0 and thus the downgrade from the arc-length continuation stepper=1 to stepper=0.
Though I guess maybe it has to do continuation over the output resistance and push that out to near-infinity in the continuation solve process (default is like 100 exa); the specified parameter constant value applicable outside of the special circumstances in which the LOCA does continuation on it, will need to be a sentinel (I'd suggest exact 0 or "anything negative"), as it shall be as non-interacting and as sparsified-away by the linear solver and all as possible (it's not a problem because the discintinuity doesn't happen while a non-linear solver tries to solve the system of equations and could have called the behavioral function with node voltages/branch currents far from anythign physical, because that's just discintinuos in a parameter, and that parameter doesn't change during any transient time integration...).
Overall the idea I'm proposing is to use gate-level digital sim (post-techmapping (and any retiming and other such intrusive changes to the logic) verilog-sim basically ) to fast-forward to an interesting moment, snapshot all stateful state, map that against pre-computed DC op points of the cell library, use the LVS matching provisions to match that state to post-PEX SPICE node identifiers, emit a spice file to-be-.include'd full of those continuation-capable cell's-internal-node-forcing B-sources (test if things are faster when forcing combinatorial nets as well, or if the additional effort expended negates the faster convergence; .nodeset is likely cheaper for those though it's just not reliable), and start the .tran sim. 
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NAT.4/NAT.5 minimum 1.8,
3. Un-salicided poly resistors narrower than the (I can only presume matching/process-control related) existing coded minimum widths: PRES.1 (0.8), LRES.1 (0.8), HRES.2 (1.0),
4. Y.PL.2 mentions 0.13 drawn channel length on thin oxide; I assume the short channel effects (possibly HCI) are generally considered too severe for other usage, but it's vendor lock to Yield Microelectronics Corporation is similarly restrictive to open source EEPROM on gf18mcuD as the proprietary-core-only tiny transistors on sky130 are to dense open source SRAM.
Like I wish I understood better what's keeping us from being allowed marking layers to not have to bother their engineers about structures that land between electrically recommended sizing and what the lithography can manufacture without risking damage to equipment or the rest of the wafer.
Could it be that some of this is from "Google-sponsored-runs" open PDK philosophy where the DRC co-writer (Google) had incentive to keep designers from submitting chips that don't work? 1 1
Please dig in and report any issues! 3 2 1
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.gds, of which I expect to have to delete all labels but the pad labels myself, followed by fully flattening it. If you have any conventions on pad labeling, I'd prefer those to be applied already and this includes separating the VDD and the VSS pads individually.) PEX http://www.opencircuitdesign.com/magic//howto.html
One with just capacitances and one with resistors and capacitances. 1PEX http://www.opencircuitdesign.com/magic//howto.html
One with just capacitances and one with resistors and capacitances. .subckt fl_mcpu32 VSS VDD le clk rst_n rst_override_n din[0] clk_n din[11] din[10]
+ din[9] din[8] din[7] din[6] din[5] din[4] din[3] din[2] din[1] din[12] din[13] din[15]
+ din[14] address[0] address[1] address[11] address[7] address[8] address[6] address[4]
+ address[3] address[13] address[14] address[12] address[9] address[2] address[15]
+ address[10] address[5] dout[1] dout[2] dout[3] dout[4] dout[5] dout[6] dout[7] dout[15]
+ dout[14] dout[13] dout[12] dout[11] dout[10] dout[9] dout[8] dout[0] oeb bus_enable
+ web unused[0] unused[1] unused[2] unused[3] unused[4] unused[5] unused[6]
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