wafer.space Community

Greetings! New here and hoping to get something ready in time for Run 3.

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djsftree

Greetings! New here and hoping to get something ready in time for Run 3.

Sweet! Want to share what you're hoping to make?

I see mithro has been adding 1x1_max_all

will the pcb templates be updates for the new slot sizes? also, is it possible for another KGD to be assembled , like an external psram at time of assembly, if a wire bond plan is invluded?

djsftree

I see mithro has been adding 1x1_max_all

will the pcb templates be updates for the new slot sizes? also, is it possible for another KGD to be assembled , like an external psram at time of assembly, if a wire bond plan is invluded?

Sorry, I don't know what you mean by 1x1_max_all but I don't think we'll be doing any kinds of multi die packaging for a while if that's what you're referring to. Mouser and others stock PSRAM you can add to your motherboard https://www.mouser.com/en/ProductDetail/878-APS6404L-3SQR-SN edit:

will the pcb templates be updates for the new slot sizes?

Yes, all standard slot sizes will have COB available, you do not need to do custom bonding diagrams, just use the default pad structure (VSS, VDD are the only ones that need to be the same) (edited)

https://mithro.github.io/gf180mcu-project-template/

2:01 p.m.

linked to from just below slot sizes table https://www.crowdsupply.com/wafer-space/gf180mcu-run-3/ , 1x1_max_all

wafer.space GF180MCU Run 3

Fabricate 1,000 chips of your own design

2:02 p.m.

“Configuration Variants”

2:05 p.m.

i assume that “mithro“ is part of the wafer space team?

djsftree

i assume that “mithro“ is part of the wafer space team?

Yep, Tim is running the show. If the attached picture is what you're referring to, these are some theoretical maximums you could achieve on the 1x1 die. If you want the COB option through wafer.space you will need to conform to the standards defined in https://github.com/wafer-space/gf180mcu-project-template/tree/main/librelane/slots Hope that helps!

gf180mcu-project-template/librelane/slots at main · wafer-space/gf...

Project template for wafer.space MPW runs using the gf180mcu PDK - wafer-space/gf180mcu-project-template

I wouldn't however count what you find in his personal repo to be anything authoritative. Just because he pushed a different template in his repo doesn't mean it's included as a CoB option. As Andrew pointed above, the official supported template is under the wafer-space org. (edited)

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noted, wafer space org over crowd supply page.

djsftree

noted, wafer space org over crowd supply page.

To be clear, you're more than able to do whatever you want on your die and have any amount of pads in any configuration of your choosing. Only specifically if you're choosing the COB option do you need to conform to anything other than overall dimensions

The platform has a checkbox for CoB that you can select. If enabled, the precheck ensures that your pads are compatible and will throw an error otherwise. Note that you still need to purchase the CoB packaging option.

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Andrew Wingate

To be clear, you're more than able to do whatever you want on your die and have any amount of pads in any configuration of your choosing. Only specifically if you're choosing the COB option do you need to conform to anything other than overall dimensions

Yeah; once we get feedback on whether what I did for FC01 is acceptable in future runs, though perhaps with mandated machine QR code in the corner; (I am under the belief that it would merely require a flag on platform.wafer.space to select "I am a flip chip die, not a wire bond die", to select the alternate DRC deck): I expect that even the full freedom of the flip-chip DRC deck will be allowed. @Leo Moser (mole99) might be able to tell us if that general allowance of subjecting a submitted chip to the flip chip DRC deck is looking favorable or if it'll likely take until after Run3.

Wafer.Space run 3 deadlines just went up on the website and nothing was posted in #announcements ??

Tim Edwards

Wafer.Space run 3 deadlines just went up on the website and nothing was posted in #announcements ??

We where all gunning for buying the first slot so we didn't tell you.

(edited)

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1x1_flip_chip_max_all

(edited)

Tim Edwards

Wafer.Space run 3 deadlines just went up on the website and nothing was posted in #announcements ??

Done, thanks!

djsftree

Click to see attachment 🖼️

how are you gonna fan that out?

initially, would simply be a test die, with a bunch of analog, passives and an inductor ring test. would be a 6 layer laser drilled pcb.

How are you getting it bumped ?

tnt

How are you getting it bumped ?

ENIG on zincate seems mature; a variant retains wire bonding ability and wouldn't turn the rest of the wafer useless. (I'm less worried about that part of the entire ordeal.)

djsftree

initially, would simply be a test die, with a bunch of analog, passives and an inductor ring test. would be a 6 layer laser drilled pcb.

Happy to work with you on making flip chip practical!

https://www.cil-uk.co.uk/news/cil-brings-wlcsp-flip-chip-wafer-interposer-bga-solder-bumping-to-the-uk-for-advanced-semiconductor-packaging/

CIL brings Flip Chip / WLCSP / Wafer / Interposer / BGA solder bum...

djsftree

https://www.cil-uk.co.uk/news/cil-brings-wlcsp-flip-chip-wafer-interposer-bga-solder-bumping-to-the-uk-for-advanced-semiconductor-packaging/

I mean if they're gonna do it for affordable pricing....

12:08 p.m.

@djsftree You've seen the test die on Run2, right?

early days, I have a 138 days

djsftree

early days, I have a 138 days

To figure out what's needed to then arrange/schedule and design, it passes faster than you'd think

FC01 ?

djsftree

FC01 ?

Yeah

12:28 p.m.

The big pads are for LGA testing; the small ones are more for testing anisotropic conductive film attachment to JLC 's 1/3 oz 2L flex with it's 2~3 mil min trace/space specs, as a 1D array that can go on the edge or with care even in the middle of a die.

@namibj : We did flip-chip in the early days of the Efabless open MPW runs, and the problem that we had was that (1) it was ridiculously expensive, and (2) it took a ridiculously long time to get done. Eventually we switched to wirebonding because it was just easier, quicker, and cheaper all around. Also I ended up with a padframe design that was good for flip-chip but suboptimal for wirebonding and we were stuck with that solution, which is still being used for wirebond packages. . . Other than that, the flip-chip solution was great! If you can figure out how to overcome the cost and delay issues, then it is definitely worth having.

Advanced Packaging Facility at University of Southampton - https://www.youtube.com/watch?v=ICRDBpmev4o

TPT-Wirebonder

Stud Bump Bonding without Tail

Yeah that's also a potential approach.

HB100 looks awesome (edited)

1:13 p.m.

https://www.youtube.com/watch?v=iIb7I31I8d8

TPT-Wirebonder

HB100 Wire Bonder Bump Bonding

1:14 p.m.

https://www.tpt.de/wp-content/uploads/00_Media/99_Elemente_und_Platzhalter/Datenbl%C3%A4tter/HB100_Datasheet_2025.pdf

1:19 p.m.

neat bit of wquipment

@Tim Edwards Oh wow, I had heard qfn was more expensive than the wlcsp and that's why were were getting 100 instead of 300 wlcsp.

tnt

@Tim Edwards Oh wow, I had heard qfn was more expensive than the wlcsp and that's why were were getting 100 instead of 300 wlcsp.

The set up cost is the issue in classic WLCSP services; being wafer level the unit economics are otherwise great

@tnt : In theory, or at least in mass production, yes, WLCSP is cheaper. But in low quantities like we do, that's not the case. And yes, once the WLCSP is paid for, it's as easy to do 300 parts as it is to do 100, and somewhere in there the WLCSP becomes cheaper per part, but at least at Efabless we didn't have that much demand for 300+ parts per customer, and the assembly prices also add up.

So it seems to me, gold stud bumping is a wire-bonder operation. It's a modified wirebonder placing and shearing a ball. Probably more complex than that but I wonder if the company that wafer space are using for wire bonding can do gold/shear balls.

I'm working towards not needing the expensive parts of the traditional WLCSP processing.

djsftree

So it seems to me, gold stud bumping is a wire-bonder operation. It's a modified wirebonder placing and shearing a ball. Probably more complex than that but I wonder if the company that wafer space are using for wire bonding can do gold/shear balls.

First problem is we're dealing with Al topmetal

My plan is to just electroless plate bumps up for fancier approaches than using the copper traces of the flex as the gap defining bumps.

wafer.space chip spotted at HeiChips

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@namibj : I know somebody (my former boss at MultiGiG) who has a process for cheap bump bonding. He has been talking with Tim Ansell and they may be working on a solution for Wafer.Space. I don't know any details beyond that, but you should probably ask Tim Ansell about it before delving too deeply into your own solution.

Tim Edwards

@namibj : I know somebody (my former boss at MultiGiG) who has a process for cheap bump bonding. He has been talking with Tim Ansell and they may be working on a solution for Wafer.Space. I don't know any details beyond that, but you should probably ask Tim Ansell about it before delving too deeply into your own solution.

Ahhh, ok

namibj

The big pads are for LGA testing; the small ones are more for testing anisotropic conductive film attachment to JLC 's 1/3 oz 2L flex with it's 2~3 mil min trace/space specs, as a 1D array that can go on the edge or with care even in the middle of a die.

anisotropic conductive film attachment to JLC 's 1/3 oz 2L flex -- 200 µm pitch, 74 bars, or potentional "soldering" (edited)

7:41 p.m.

"electroless plate bumps up for fancier approaches than using the copper traces of the flex as the gap defining bumps" - sounds interesting too!

yeah; notably it hopefully opens up approaches that rely on e.g. solder mask defined pads or at least similar structures that can include vias; with ACF there's likely actually no need for solder mask as funny as that sounds, because everything is defined by bumps/surface topography

djsftree

anisotropic conductive film attachment to JLC 's 1/3 oz 2L flex -- 200 µm pitch, 74 bars, or potentional "soldering" (edited)

notably that can integrate with the classic padframe structure in a way that you could arrange for them to get wedge bonded if after tapeout the opportunity of the specific flip chip approach dries up.

namibj

I'm working towards not needing the expensive parts of the traditional WLCSP processing.

One of the disadvantages I see for WLCSP is that if you make the bond pad bump compatible in size and pitch for direct PCB bonding you limit the amount of pads/area. At imec the packaging people were also worried about difference in thermal expansion between silicon and PCB leading to cracked joints after repeated thermal cycling of your system (e.g. turning on and off). A more classic alternative to WLCSP is flip chip packaging with a so called substrate connecting out a tighter bump pitch to a bigger BGA pitch that is PCB compatible. I believe main NRE cost was the design of the substrate but this could be shared if we standardize the bump array on silicon. If somebody wants to investigate further, imec was using Greatek for small volume packaging.

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Chips4Makers aka Staf Verhaegen

One of the disadvantages I see for WLCSP is that if you make the bond pad bump compatible in size and pitch for direct PCB bonding you limit the amount of pads/area. At imec the packaging people were also worried about difference in thermal expansion between silicon and PCB leading to cracked joints after repeated thermal cycling of your system (e.g. turning on and off). A more classic alternative to WLCSP is flip chip packaging with a so called substrate connecting out a tighter bump pitch to a bigger BGA pitch that is PCB compatible. I believe main NRE cost was the design of the substrate but this could be shared if we standardize the bump array on silicon. If somebody wants to investigate further, imec was using Greatek for small volume packaging.

Yeah, for the record I'm not aiming at large pitch other than perhaps some power devices to be tightly integrated with epc-co (or other's) GaN-on-silicon devices, and for density reasons typically not regular FR4.

added offscreen rendering and anti aliasing to GDS3D and a little spinn to mp4

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4:18 p.m.

developing the tech file for GDS3D for gf180mcud

gf180mcu_fd_io__bi_24t

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djsftree

developing the tech file for GDS3D for gf180mcud

awesome!

7:20 a.m.

i've tried making one too

7:20 a.m.

since i wanted to view mine in gds3d as well

Take a look - https://agentdavo.github.io/GDS3D/

djsftree

Take a look - https://agentdavo.github.io/GDS3D/

Wow, never realized there were so many standard cells! Cool!

Interesting to see the cell sizes across the libraries. @Tholin's being the smallest

i'll look into that

djsftree

i'll look into that

One more request: could you look at unloading the elements that are out of view ? It's a great website that I could see myself using but as of now it's so resource heavy that the tab crashes after I scroll down a bit.

Andrew Wingate

Interesting to see the cell sizes across the libraries. @Tholin's being the smallest

gf180mcu_as_sc_mcu7t3v3__nand2_2 - the 3.3V device is smaller

djsftree

gf180mcu_as_sc_mcu7t3v3__nand2_2 - the 3.3V device is smaller

I was aware of that. | Still super cool. Nice job!

Essen

One more request: could you look at unloading the elements that are out of view ? It's a great website that I could see myself using but as of now it's so resource heavy that the tab crashes after I scroll down a bit.

done, when github pages catches up (10mins) should be ok

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djsftree

done, when github pages catches up (10mins) should be ok

much better

(edited)

very cool visualizations!

try again in 15 mins (edited)

hopefully a little neater now

djsftree

try again in 15 mins (edited)

Check out my project and load some chips

https://alpharomerojl.github.io/reticle/

Reticle

Browser-native, GPU-accelerated editor for very large hierarchical 2D IC-layout scenes.

outofnades

Check out my project and load some chips

https://alpharomerojl.github.io/reticle/

Neat! Want to tell us a bit about it?

finished the redesign - take a look - https://agentdavo.github.io/GDS3D/ 703 cells across 11 libraries; 703 rendered so far.

9:13 a.m.

Explode distance is scaled per library: the offset is absolute in microns, so the value that suits a 350 µm I/O pad would throw a 3 µm standard cell off screen.

9:14 a.m.

if you tap on a video a modal pops up with LEF and Liberty info

Andrew Wingate

Interesting to see the cell sizes across the libraries. @Tholin's being the smallest

well, thin oxide DRCs + 7-track.....

Chips4Makers aka Staf Verhaegen

One of the disadvantages I see for WLCSP is that if you make the bond pad bump compatible in size and pitch for direct PCB bonding you limit the amount of pads/area. At imec the packaging people were also worried about difference in thermal expansion between silicon and PCB leading to cracked joints after repeated thermal cycling of your system (e.g. turning on and off). A more classic alternative to WLCSP is flip chip packaging with a so called substrate connecting out a tighter bump pitch to a bigger BGA pitch that is PCB compatible. I believe main NRE cost was the design of the substrate but this could be shared if we standardize the bump array on silicon. If somebody wants to investigate further, imec was using Greatek for small volume packaging.

I believe under our circumstances we should likely be free to do a modular bond-out substrate that can hold a full die or a half-die; depending on precision and need for gaps and how wide the dice line is (I fear it's not actually a positive width, if we're doing guided crystal fracture to split the substrate bulk), it could even be feasible to co-package two half dies in the space of a full die (I think some here have been working on chiplet/transputer like arrangements). I have to focus on the SerDes getting onto IHP SG13CMOS5L now though; reason being that silicon being sponsored and that porcess being not unlikely so much faster that I could pull off 25G with the exact same analog frontend topology that would do 10G on gf180mcuD. And hopefully we can have a silicon-tested/SPICE-extraction-calibrated thin oxide SCL on gf180mcuD by the time the finalization of data path widths happens for the SerDes instance that I hope to get onto Run4. Because I do quite want to have "reasonable" confidence in the SCL part not being the reason the SerDes fails to reach protocol speeds, and especially on the larger gf180mcuD I feel like overly wide datapaths on the SCL side would have substantial potential for dragging it all towards "large area need, PA not even included".

have a transputer t9000 inspired fpu with mxfp4, q8, and some t&l ops running at 50mhz on gf180

6:32 p.m.

6:33 p.m.

linux 7 , tinycc transputer compiler

added a dl mp4 button of the vid if you want to use for educationals.

7:09 p.m.

https://agentdavo.github.io/GDS3D/

serdes on gf180mcuD would be great, or low freq multiphase ddr3 like interface 1.5V power domain optimised.

djsftree

serdes on gf180mcuD would be great, or low freq multiphase ddr3 like interface 1.5V power domain optimised.

Well you're not along on the SerDes wish; do you have any preference as to the TX or the RX if you'd only get one or if both being the same level of fast would be way more expensive than only one being truly fast and the other direction running considerably slower?

tnt

I wouldn't however count what you find in his personal repo to be anything authoritative. Just because he pushed a different template in his repo doesn't mean it's included as a CoB option. As Andrew pointed above, the official supported template is under the wafer-space org. (edited)

@djsftree stuff under my personal repo are experiments that are not always connected to reality in any way.

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djsftree

So it seems to me, gold stud bumping is a wire-bonder operation. It's a modified wirebonder placing and shearing a ball. Probably more complex than that but I wonder if the company that wafer space are using for wire bonding can do gold/shear balls.

Only Al bonds at the moment. @stuart is your person for custom wire bonding contracts.

Looking at the quarter slot. Is there an option for wire bonding e.g. only 1/5th of the dies and paying $300?

Archit3ch

Looking at the quarter slot. Is there an option for wire bonding e.g. only 1/5th of the dies and paying $300?

There is a fixed cost with doing things at the moment that means it isn't really possible. I'm trying to work with a number of PCBA houses so they can do wire bonding following standard templates as part of normal PCBA through their website and such. @stuart and @Lauri are helping figure out that.

Archit3ch

Looking at the quarter slot. Is there an option for wire bonding e.g. only 1/5th of the dies and paying $300?

The eventual hope is that I can ship your parts direct to a place like NextPCB and they do what ever wire bonding you want in an even more cost effective manner.

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Do let me know if that service becomes available before the run 3 deadline (or I guess before the slots run out). Even as a one-off agreement with the PCBA houses before you roll out the service for everyone.

https://agentdavo.github.io/GDS3D/index3d.html — actual pdk data now, using custom webgl2 renderer

can also cooy a modal url to share or embed

example https://agentdavo.github.io/GDS3D/index3d.html#c=gf180mcu_as_sc_mcu7t3v3__ao211_4&az=-0.716&el=0.633&spin=0&pin=VSS

Okay, I am also intending to make more updates to my SCL for run 3. Suggestions?

10:04 a.m.

My personal goal is it to finish some missing oai parts and then see what’s missing to get it to work with vlsiffra

Tholin

Okay, I am also intending to make more updates to my SCL for run 3. Suggestions?

A clock gate?

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How do those work? Is it like a latch?

The sky130 cell has a schematic: https://sky130-unofficial.readthedocs.io/en/latest/contents/libraries/sky130_fd_sc_hd/cells/dlclkp/README.html

10:41 a.m.

Basically a latch plus making sure there aren't any glitches

Ah, the enable signal is synched to the clock (edited)

10:42 a.m.

I don’t think I’ll be able to characterize that

10:42 a.m.

Beyond propagation delay with the gate enabled

A clock gate would definitely be nice, even if it's not properly characterized yet. Also, I heard a new open-source characterization tool is coming out soon. I'll let you know once I know more.

1

I’m pretty happy with lctime since it actually lets me automate it

10:59 a.m.

But all the characterization tools so far lack the ability to automatically determine the maximum capacitive load on a cell to keep within a max transition constraint.

11:00 a.m.

Its the one remaining manual step for me.

Can I have multiple power domains using the foundry IO pads? Like, can I insert breakers to have a single isolated VDD pad?

12:52 p.m.

I do not know how to do this, but its the one puzzle piece I’m missing currently to get started on my submission

12:52 p.m.

Fallback would be using an analog pad for that supply

To clarify: I know the __brk macros exist, I just don’t know how to instantiate them

Any reason you want to use that rather than using an analog pad ? The downsides is you're breaking your ring ... The upside is you don't have diodes to IO supply ...

The two digital input pads tied related to that supply

1:18 p.m.

Yeah!

Ah so it's not just a voltage input you want to actually supply some IO pads off that supply. Got it.

And an output

1:19 p.m.

I need break -> VDD -> input -> input -> output -> break

You might want a ground pad there too.

1:23 p.m.

Because although the brk doesn't break VSS, it does break DVSS. And yeah, those are eventually electrically connected in the foundry IO, but then your ESD path to ground (and low drive too) takes a very long path instead of the very strong DVSS connections.

1:27 p.m.

As so how to use them, I'd just instanciate them in the verilog and then use a custom pad placement script to get those instance and put them in the right spot. At least that's how I would try it.

Yes, LibreLane's default padring generation script treats the breaker cell just like any other I/O cell and tries to space everything equidistant. So a custom padring script makes sense.

I need to be careful not to break compatibility with the COB check

1:47 p.m.

I don’t even know what all that one checks for

Leo Moser (mole99)

Yes, LibreLane's default padring generation script treats the breaker cell just like any other I/O cell and tries to space everything equidistant. So a custom padring script makes sense.

Huh, that was easier to figure out than I thought. I got two breakers, right where I need them.

2:09 p.m.

Its a bit jank, I hardcoded where it places them

2:09 p.m.

But I got it

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tnt

Because although the brk doesn't break VSS, it does break DVSS. And yeah, those are eventually electrically connected in the foundry IO, but then your ESD path to ground (and low drive too) takes a very long path instead of the very strong DVSS connections.

Okay, so, ground will not be broken up, effectively? That is good news, actually.

Tholin

I need to be careful not to break compatibility with the COB check

If the COB check checks for the locations of ground AND power pads, I might have issues with laying things out efficiently later down the line, but I can make it work. If it’ll throw a fuss at me inserting additional power pads, that would be a problem.

@Tholin Huh ... "not broken up" but you really want a ground pad for things to work

Ground should be common between the two circuits on this die

Tholin

If the COB check checks for the locations of ground AND power pads, I might have issues with laying things out efficiently later down the line, but I can make it work. If it’ll throw a fuss at me inserting additional power pads, that would be a problem.

The CoB checks only verifies the passiviation openings - what they bond to doesn't matter.

But isn’t ground and/or power tied to a copper plane on the breakout board?

2:40 p.m.

So I practically can’t move those without creating shorts.

Tholin

But isn’t ground and/or power tied to a copper plane on the breakout board?

The COB as it stands, ground are tied together. power are all separate, but they all each have a decoupling cap on the wire.

Alright, so I can move the power pads

I finished pinout planning and setting up the padring just as I’m informed there are barely any quarter slots and I’d have better chances with a horizontal half-width

1

3:04 p.m.

a!

1

3:07 p.m.

The 1 by 0.5 doesn’t have the power and ground pads placed as conveniently as the 0.5 by 0.5

Tholin

I finished pinout planning and setting up the padring just as I’m informed there are barely any quarter slots and I’d have better chances with a horizontal half-width

Oh what? It got rid of all my beautiful markings on export.

1

3:11 p.m.

You see how that works perfectly, right?

3:16 p.m.

On 1 by 0.5, the longest run of non-ground pads is this, which splits the die into thirds.

3:17 p.m.

Although this would be able to switch more current

3:19 p.m.

Probably an unhealthy amount, so that’s not really the goal

1

Well, lets try this, I suppose

Tholin

I finished pinout planning and setting up the padring just as I’m informed there are barely any quarter slots and I’d have better chances with a horizontal half-width

For ws-run 3, there will probably be 9 quarter slots again. But since they can now be purchased, they may get used up quickly. True.

Tholin

Okay, I am also intending to make more updates to my SCL for run 3. Suggestions?

Buffers that are designed to maintain duty-cycle (thus preventing long paths from swallowing up short/fast pulses? The TSP-DFF you had looked at? And, importantly, getting some proper full characterization work going including characterized static power, and maybe adding some less-conservative "ss/sf/ff/fs" corners that aim at something like 70~90% yield (looking only at global process variations for that figure; treatment of other process variations would still be done the normal way, and this is IMO basically about being able to plan for a less-ambitious yield of extended-temperature-and-voltage-range chips while still checking the normal ways that full yield is expected if the chips are treated as "limited temperature range, and needs a voltage supply better than a 7805-grade", by basically accepting that with some acceptable risk the devices built from the chips would need to employ an actual heat sink for the chip, perhaps even a fan, and would need a fancier-than-baseline power supply). I believe Xyce's intrusive-PCE and/or embedded-sampling would work effectively and affordably for this number of fingers/devices in a DUT, for getting statistically confident and reasonably-tight bounds on mismatch-induced variations in any given cell's delays, so that OpenSTA may appropriately consider the limited predictability of gate delays when figuring whether a PnR "solution" will work out.

The clock buffers are supposed to be delay-balanced

@azonenberg can you send @Tim Edwards the information on what hardware measuring/testing equipment abilities you do have for the multi-gigabit Ser[Des] we're proposing like right now for IHP SG13CMOS5L? Sorry to be so sudden, I forgot it was part of what's technically the "proposal deadline affected information-to-file". I'm expecting your scope to suffice to do appropriate reasonably representative BER measurements with the CDR shoved into ngacopeclient such that we can cope with the TX Baudrate being set by a non-PLL-governed VCO? Like I expect that to cause substantial amounts of low-frequency FM far out of the normal +-100ppm of BASE-R, but that's not gonna be a problem, right?

namibj

@azonenberg can you send @Tim Edwards the information on what hardware measuring/testing equipment abilities you do have for the multi-gigabit Ser[Des] we're proposing like right now for IHP SG13CMOS5L? Sorry to be so sudden, I forgot it was part of what's technically the "proposal deadline affected information-to-file". I'm expecting your scope to suffice to do appropriate reasonably representative BER measurements with the CDR shoved into ngacopeclient such that we can cope with the TX Baudrate being set by a non-PLL-governed VCO? Like I expect that to cause substantial amounts of low-frequency FM far out of the normal +-100ppm of BASE-R, but that's not gonna be a problem, right?

The vendor CDR package lets you tweak the bandwidth of the loop pretty flexibly

7:12 p.m.

the ngscopeclient CDR is not currently tunable, but has wide bandwidth and will track low frequency jitter or spread spectrum no problem

7:13 p.m.

i actually use it all the time to measure the stability of a clock signal

7:13 p.m.

like, i can lock my soft PLL to the input data and recover the clock then plot frequency over time with some smoothing to measure drift in the source oscillator

7:14 p.m.

the bigger question is, for real use, how much noise a real e.g. FPGA based receiver can tolerate. but if the goal is just to validate the driver, it'll work no problem

7:15 p.m.

Equipment wise I have a teledyne lecroy SDA816Zi-A with probes including but not limited to D1605, D1330, D420-A, D420

7:15 p.m.

and a MultiLane ML4039 BERT that may or may not be able to lock to the signal depending on how stable the clock is

7:15 p.m.

if you are able to output a 1/32, i think, rate reference clock it will help the BERT track it

azonenberg

the bigger question is, for real use, how much noise a real e.g. FPGA based receiver can tolerate. but if the goal is just to validate the driver, it'll work no problem

For real use one would add a PLL to it, that's just one more thing to go wrong and result in the IHP chips being DOA (for the high speed TX).

yeah makes sense

7:29 p.m.

Could you possibly add a divided vco clock out and expose the vco control voltage so it would be possible (but not mandatory) to close the loop externally? (edited)

azonenberg

if you are able to output a 1/32, i think, rate reference clock it will help the BERT track it

We expect a Baud/512~Baud/64 divided reference feed for the hopefully-deadline-meeting RX, with an off-die CDR getting provided edge sampler information via GPIOs (if I can DDR and ofc relative to that reference clock fed in), where the on-die PLL only does simple stupid integer-PLL and the synthesizer of this reference clock has to take care of possibly even bit-slipping until the PRBS receiver accepts it (not sure if it's sensitive if it's parallelized). Because I figured we don't actually have to do any of the hard parts of CDR on-die just to make this testable.

azonenberg

Could you possibly add a divided vco clock out and expose the vco control voltage so it would be possible (but not mandatory) to close the loop externally? (edited)

I'm fully expecting such to be included, at sufficient quality to at least make testing not-hard.

I specifically say 1/32 because i believe that is what the BERT needs (I'd have to double check but i'm ~95% sure it's 1/32)

7:41 p.m.

so if i get exactly that, the bert is in play

7:41 p.m.

if not, i can only use the scope

7:41 p.m.

(for the TX)

namibj

I'm fully expecting such to be included, at sufficient quality to at least make testing not-hard.

@azonenberg Maybe the RX PLL can even be connected to the TX VCO/clock tree, we'll see. First we do a simple TX and when there's a DRC clean layout for it that has at least 30% yield for "good", and 80% yield for "testable", only then do we put any substantial design effort into any fancy FIR, beyond-trivial pad capacitance matching/compensation, and ESPECIALLY any RX design, at least anything beyond trying to vaguely understand sensitivity time window for a strong arm latch implementation on that very process (as that strongly guides planning of how small of an UI to aim for in the RX, and it's area requirements gonna give a substantial hint on how large/compact the analog circuity would roughly be and from that whether it may fit into the same slot as the TX or whether it would need it's own slot to reach any comfy good performance/TX-matching-speed).

azonenberg

so if i get exactly that, the bert is in play

Could so with an external frequency synthesizer for ya

azonenberg

the ngscopeclient CDR is not currently tunable, but has wide bandwidth and will track low frequency jitter or spread spectrum no problem

I'm thinking like +-5% drift in Baud rate due to hard-to-prevent temperature variations from airflow variations as you're reaching around the DUT on the bench (fiddling with the test gear stacked at the back of the workbench, or anything vaguely like it that explains some good thermal drift if a frequency is more manually adjusted through e.g. a zoomed-in spectrum analyzer on a 1:10 power divider (needs only a little bit of signal

) and a hand occasionally reaching for the know of the bench top PSU. Or something

azonenberg

the bigger question is, for real use, how much noise a real e.g. FPGA based receiver can tolerate. but if the goal is just to validate the driver, it'll work no problem

I'm confident a reasonable PLL implemented later is not hard to analytically adjust the jitter-vs.-frequency (UI_pk-pk vs. frequency) effects of the observed free running VCO of, to know if that particular PLL option would bring the TX jitter spectrum into compliance with 802.3.

Tholin

On 1 by 0.5, the longest run of non-ground pads is this, which splits the die into thirds.

You're not mandated to short the pad opening's exposed metal of a COB's "ground pad" to anything particular inside.... just in case you thought otherwise.

5% drift would be tricky if it's short term. 0.5% i could probably handle? I've never actually tested how far i can push the PLL. but also over what time horizon

2:22 a.m.

like it would be pretty easy to just grab a single waveform at a time and track whatever baud rate its running at and assume thermal drift over that 1ms window is negligible

azonenberg

like it would be pretty easy to just grab a single waveform at a time and track whatever baud rate its running at and assume thermal drift over that 1ms window is negligible

oh yeah that 5% if more over like 10s timescales or thereabouts, it's more a concern with a CDR PLL perhaps utilizing a relatively narrow-band pre-filter for the rate it's looking out for, and thus "keeping itself" from actually-following the signal, or perhaps just initially failing to find a lock in the first place.

on a per-capture basis i can change the nominal rate in software. If we are talking to a hardware device, it's an issue

At that point might as well point a thunderscope at it and spectrum-analyzer find the sub-harmonic of the baud rate where some relevant lower speed pattern content exists, like the 805.664062 megahertz of the 25GBASE-R's 64b/66b blocks that include their oh-so-important sync header. But yeah, I do not expect it to need to run free for testing, I think it can be used with an external PLL to be properly tested with "normal" gear.