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      "content": "Very cool! Documentation of instruction format could use some improvement though. It took me a while to figure out that this architecture **CAN** in fact read memory, as the opcode is actually only 3 bits (not 4 like in the readme) and the top bit is actually the \"read memory bit\". Predicates aren't defined either, so I'm still a bit confused on what bits to set for the C/Z/Invert predicate bits to do something logical, or if there's a way to make an unconditional instruction.",
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      "content": "And if I'm correct the only way to branch is by writing to the PC register? Which combined with predicates instructions allows for conditional branching, nice",
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      "content": "Also I think there's no way to add reg + reg, you can only add reg + imm or reg + mem?",
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      "content": "documentation, indeed, needs improvement",
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      "content": "the opcode is actually 3-bit, as you stated",
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      "content": "but there is a modifier for the ADD/ADC mnemonics in line 35 of as16.v: `ADD, ADC : {carry, result} = grf_dout + OR_q + (!IR_q[8] & C_q);`",
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      "content": "Though bit 8 is just one of the normal opcode bits, specifically the low bit that distinguishes between ADD and ADC. So still a 3-bit opcode",
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      "content": "exactly.",
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      "content": "Oh also it looks like you can only read and write to constant memory addresses? No array indexing or stack?",
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      "content": "Unless you do some self modifying code shenanigans, I guess...",
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      "content": "well, `EA_ED` does let you add a reg to an offset to form an address...",
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      "content": "Ah, missed that",
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      "content": "I also don't see how sram is connected to anything in the core module. Seems unconnected?",
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      "content": "exactly",
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      "content": "kinda just hardwired it outside from the cpu",
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      "content": "So you're planning to use an external SRAM chip and ignore the internal SRAM you're generating?",
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      "content": "yep",
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      "content": "just going to treat the as16 as a microprocessor",
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      "content": "besides, i kinda rushed the design in those 3 days",
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      "content": "Gotcha, yeah that was a very quick window haha",
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      "content": "overall, i'm kinda happy for my first tapeout",
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      "content": "Yeah looks like it'll be a fun chip to play around with!",
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      "content": "congrats \uD83D\uDE42",
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      "content": "thx",
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      "content": "i'm not sure how i'm going to wirebond it",
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      "content": "as i didn't choose for COB packaging",
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      "content": "i'll probably have to find some national facility to do it for me as an \"academic institution\"",
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      "content": "hmm, I wonder if it would be feasible for WS to provide at least one CoB-packaged chip even if you elected to not have them all packaged. Could be really useful for initial testing, and I'd think it would logistically be not too difficult to do one extra CoB wirebonding per design. Main challenge would be to keep them separated without accidentally mixing them up I guess. cc @Tim 'mithro' Ansell for the idea",
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      "content": "fair enough",
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