wafer.space Community - Most if not all of the DRC errors should

12:47 p.m.

Nice! I'm currently integrating the KLayout DRC deck into the gf180mcu LibreLane setup. This should catch any additional errors.

12:49 p.m.

If you can still recall, it would be great if you could let @Tim Edwards know which errors didn't show up in magic DRC.

CO.6a: Metal1 end-of-line overlap contact

1:13 p.m.

Example being the version of the aoi22_2 cell at this commit: https://github.com/AvalonSemiconductors/gf180mcu_as_sc_mcu7t3v3/blob/112ea06e961bfe76b10c66805db09410885fccf4/pdk/libs.ref/gf180mcu_as_sc_mcu7t3v3/mag/gf180mcu_as_sc_mcu7t3v3__aoi22_2.mag

gf180mcu_as_sc_mcu7t3v3/pdk/libs.ref/gf180mcu_as_sc_mcu7t3v3/mag/gf...

Custom Standard Cell Library for GF180MCU process node on open PDK. - AvalonSemiconductors/gf180mcu_as_sc_mcu7t3v3

As far as I can tell, the rule is implemented correctly in magic, and I don't see any error in that layout.

I got it after running a flow

But I'm looking at the layout and I don't see an error. Was there a coordinate shown indicating where the error is (or where it thinks the error is)? (edited)

1:30 p.m.

And what tool flagged an error?

It indeed does not show up if the DRC in run on the cell in isolation.

1:30 p.m.

I got it after running KLayout DRC on a flow output

I don't get how that's possible, other than a bad implementation in klayout. How can a minimum overlap be satisified within a cell but violating in a larger context?

It would definitely be useful to have the flow output in order to reproduce the error.

Here’s the whole run.

latest.zip

6.51 MB

1:42 p.m.

@Tholin : I can't find the error anywhere in the files. Where should I be looking?

Currently, you have to run KLayout DRC separately through

python $PDK_ROOT/$PDK/libs.tech/klayout/drc/run_drc.py --variant=D --run_dir=drc --path=runs/latest/final/gds/user_project_example.gds

2:49 p.m.

Which is what I’m doing manually after each run.

That might require klayout with ruby support (which I haven't tried to compile yet)? I get ERROR: Can't run macro (no interpreter): /home/tim/devel/open_pdks/Tholin/latest/drc/main.drc. Can you post the DRC database output from klayout?

user_project_example_main.lyrdb

118.29 KB

It appears that whether or not this is a rule violation entirely depends on the definition of "end of line". Since the DRC document does not (as far as I could find) define "end of line", then it remains unknown whether the klayout rule is overly conservative or if the magic rule is not conservative enough. If the latter, I'm not sure that there is an edge rule in magic that would capture the rule intent.