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      "content": "I'm not sure it will change anything at all.",
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      "content": "Yeah right, I think namibj told me earlier that the substrate is not really simulated properly.",
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      "content": "I've drawn my tap cells like those generated in klayout (on one side, made of psd/psc) but I feel like I don't really know what I am doing and hoping that simulations can later spot my issues.",
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      "content": "I wouldn't count on it.",
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      "content": "But wether that matters or not depends a lot of what you're doing.",
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      "content": "My understanding is it's mostly about tiny noise and cross talk between circuits, catching stray substrate currents. If you're circuit isn't super low noise or that sensitive, should be just fine",
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      "content": "Just my 2 ct.",
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      "content": "Appreciate all cents i can get \uD83D\uDE42 I'm fine with a bit of noise. Its mostly latch-up I want to be sure I avoid, but maybe its not such a large problem. I have been browsing some designs and I think my method is fine.",
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      "content": "Latchup you should be fine. The DRC will check there are enough taps and if there are wired to the proper rail it's all good.",
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