wafer.space Community - Sylvain is working on a ROM compiler.

8:40 a.m.

Yes, although depending on the content a yosys ROM can be smaller, that's only true if the content can simplify well. If not, it quickly grows and the routing mess it creates also can make P&R a real pain. I have been drafing how to adapt it to gf180. Some of the tricks and structure I used in sky130 don't really apply here ( actually then end up being counter productive ) but I have a few things up my sleeve that I hope will pan out. Priority ATM is however to validate the sky130 one. Although it's been silicon proven as far as it outputs the right data, the whole timing validation remains to be done and that's not a small thing

(edited)

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Thank you both. I guess a possible sythesis based solution could be to have a librelane step that builds a macro for the rom (cached om rom content), which would give the benefits @Leo Moser (mole99) mentioned without needing to port to every process. (edited)

I don't see how that would work. If you use a normal synthesis process to build a ROM, the size of that macro is heavily dependent on the ROM content. If you change the rom content, the size would change.

I think the idea is to avoid paying the ROM's PnR cost each time?

tnt

I don't see how that would work. If you use a normal synthesis process to build a ROM, the size of that macro is heavily dependent on the ROM content. If you change the rom content, the size would change.

true.. isn't that also the case for a ram generator? I guess you could configure a macro block size, pins etc (edited)

namibj

I think the idea is to avoid paying the ROM's PnR cost each time?

could cache based on pdk and hash of rom contents

Rob Taylor

true.. isn't that also the case for a ram generator? I guess you could configure a macro block size, pins etc (edited)

I wonder if there's a way to calculate what the max area could be for a given rom size. I'm finding it hard to think about that though

Rob Taylor

true.. isn't that also the case for a ram generator? I guess you could configure a macro block size, pins etc (edited)

The benefit of synthesis (via abc) ROM would be to be smaller than a mask ROM.

Rob Taylor

I wonder if there's a way to calculate what the max area could be for a given rom size. I'm finding it hard to think about that though

Design a mask ROM.

namibj

Design a mask ROM.

cool. let me know if you do anything in this space

I'm not expecting to

Rob Taylor

cool. let me know if you do anything in this space

(Though I am looking towards perhaps a RAM setup that would allow mapping a short history of nominal transmit symbols to a DAC code; and that in a way that can efficciently be run with a good amount of interleaving/C-slowed action applied, like 4 or 8 or so times slower RAM-bitline-action than the symbol rate of the stream.) (Such approach is highly capable of mitigating data-dependent output waveform distortion, even in ways that are non-trivial interactions with a particular instance's bond wire inductance and PVT variations, notably having rather little penalty for multi-level signalling (e.g. PAM3/4/5) compared to classic binary "virtual" shift register approaches to the task of mitigating data-dependent waveform distortion.) (edited)

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namibj

I'm not expecting to

ah well