wafer.space Community - 🤪-off-topic

BreakingTaps 2025-12-01 3:09 a.m.

BreakingTaps

I feel like I've seen this program before and it looks very nice, could i ask what it is

btop! https://github.com/aristocratos/btop

GitHub - aristocratos/btop: A monitor of resources

A monitor of resources. Contribute to aristocratos/btop development by creating an account on GitHub.

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I generally use htop

looks like this'll be roughly what I tape out, modulo a few last minute tweaks!

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gorgeous!

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BreakingTaps

looks like this'll be roughly what I tape out, modulo a few last minute tweaks!

Memory Bank

haha yeah, it's basically memory with a some logic thrown in for fun

(edited)

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BreakingTaps

looks like this'll be roughly what I tape out, modulo a few last minute tweaks!

That is pretty cool! Specially seeing the SRAM layout.

thanks! took some finagling to get everything placed nicely. I knocked together a quick tool to make it easier to hand edit/place macro blocks, i'll upload it tonight when I get home in case anyone else wants to use it.

11:46 p.m.

not entirely certain this is needed now that I discovered the 9T cells, but having everything physically close instead of columns helped get timing issues under control

@BreakingTaps - Also this is very on topic....

BreakingTaps

looks like this'll be roughly what I tape out, modulo a few last minute tweaks!

For some reason discord won't let me forward your message to #general....

BreakingTaps

thanks! took some finagling to get everything placed nicely. I knocked together a quick tool to make it easier to hand edit/place macro blocks, i'll upload it tonight when I get home in case anyone else wants to use it.

Cool!

Nice to see all the wafer.space logos that were not picked:

9:22 a.m.

https://www.freelancer.in/contest/logo-design-for-waferspace-2545806/entries

Logo design for Wafer.Space

I'm in need of a logo for my new Singaporean company, [login to view URL], which is "semiconductor pooling service" in a similar vein to OHS Park ([login to view URL]) and Dirty PCBs ([login to view URL]) except for silicon integrated circuits. The logo should take inspiration from;

Space (stars, moons, planets, comets, rocket ships, Sci-F...

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urish

https://www.freelancer.in/contest/logo-design-for-waferspace-2545806/entries

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Nice!

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urish

Nice to see all the wafer.space logos that were not picked:

I never noticed the dies in the logo are 'W' and 'S' for wafer.space. Thought that was neat.

Hah! missed that as well, clever

Same here

asic destroyer

Click to see attachment 🖼️

Wanna share the code which produces that?

7:26 a.m.

The W and S where inspired by things like the hidden arrow in the Fedex logo

off to camp in the woods for the weekend, hope nothing breaks while I'm gone

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BreakingTaps

off to camp in the woods for the weekend, hope nothing breaks while I'm gone

Enjoy!

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Are there MPW shuttles out there for "more" modern nodes, say 22-65nm? Obviously would need NDA and probably be a lot more expensive. Was just curious now that I've been bitten by the silicon bug

5:19 p.m.

or do you have to go and buy a full wafer from the fab at more modern nodes?

Check out Europractice and muse semi for some

5:22 p.m.

Surprisingly, signing the NDA can sometimes take longer than the shuttle's turnaround

will take a look, thanks!

5:27 p.m.

and oof, that sounds awful. why so long for NDA and paperwork?

I ask - why NDA at all?

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hah yeah that's fair. especially for older nodes, it's not like there's a lot of cutting edge IP that could be reverse engineered there... presumably the industry knows all the tricks already and has applied it to the latest nodes

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BreakingTaps

Are there MPW shuttles out there for "more" modern nodes, say 22-65nm? Obviously would need NDA and probably be a lot more expensive. Was just curious now that I've been bitten by the silicon bug

I think my employer has used IMEC for MPW tapeouts on non-cutting-edge TSMC (e.g. 40LP): https://www.imeciclink.com/en/asic-fabrication/mpw-schedules-2025

MPW schedules 2025 | IC-Link by imec

IC-Link offers the multi-project wafer (MPW) services through leading foundries and fabs. Find out the scheduled runs below.

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7:51 p.m.

it's more of a "send an email and talk to a guy" experience rather than an online shopping experience

7:53 p.m.

also I don't think just booking an MPW slot is enough to actually get your hands on the design rule manual, foundry cell libraries and foundry RAM compiler etc for your process. That part probably involves talking directly to TSMC. I've luckily been insulated from this

7:55 p.m.

The real magic of wafer.space for me so far has been that the PDK is open, and equally importantly that people like Leo have done a ton of work to put a baseline flow together so you can get to GDS on day 1 and then iterate from there (edited)

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fascinating. I knew the industry was pretty locked down, didn't realize it was to that degree

8:30 p.m.

makes me appreciate TT and wafer.space even more!

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Some of us have been fighting the industry mindset for decades. It's a wonderful feeling to see some progress come out of all of that, finally.

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https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs

Here’s a more professional and polished version of your Markdown — ready to paste directly into your README.md:

I...would suggest getting rid of that line

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BreakingTaps

and oof, that sounds awful. why so long for NDA and paperwork?

Because lawyers are involved and nobody really has an incentive to make it better.

Lofty

https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs

Here’s a more professional and polished version of your Markdown — ready to paste directly into your README.md:

I...would suggest getting rid of that line

I assume @Andrew Wingate asked an AI to make his words seem more professional and had a copy and paste oppsie.

Lmao. Oops

BreakingTaps

fascinating. I knew the industry was pretty locked down, didn't realize it was to that degree

BTW Most foundries have MPW programs. My understand is that most of these MPW programs lose the foundry money which leads to them being very restrictive about what you can do with their MPW program. Both EuroPractice / MOSIS also lose money and can only continue to run with government grants and such. (edited)

2:13 a.m.

I did this comparison back in 2022 - https://docs.google.com/document/d/1rGOHsDU8XALX7jKw31Q59y3njZ0865T2qZPzhHIjIYo/edit?tab=t.0

MPW Program Comparisons (2022)

MPW Program Comparisons (2022) Program Name Google’s OpenMPW program chipIgnite EuroPractice MUSE MOSIS CMC Operated by Efabless Efabless IMEC MUSE MOSIS CMC Location Worldwide Worldwide Europe US US Canada Created 2020 2021 1995 2018 1981 Commercial Allowed ...

2:14 a.m.

One of my goals with wafer.space is to show that you can run an MPW service for profit (with both the MPW company is making money, the foundry is making money) and then slowly take over the rest of GF's MPW program.

2:14 a.m.

(goals might be the wrong word -- maybe dreams?)

2:15 a.m.

My (very limited) understanding is their current MPW program consumes somewhere between $50m and $100m in ongoing funding every year.

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woah crazy, I didn't realize they were net-negatives to the foundry. guess they view it as a necessary evil and "marketing", but not something they really want to support

Hello @Tim 'mithro' Ansell could you create a new channel for PCB design where we can discuss?

https://github.com/Ravenslofty/blog/issues/17 Perhaps this will inspire some people to help me ^^;

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asic destroyer

Hello @Tim 'mithro' Ansell could you create a new channel for PCB design where we can discuss?

I think most people have been using the #📦-cob channel for now?

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hey @Tim 'mithro' Ansell nice community! this is alex from linkedin :)

Tea-Rex

hey @Tim 'mithro' Ansell nice community! this is alex from linkedin :)

You'll have to remind me who that is, I have a terrible memory

No worries

pushed the button this morning, exciting / terrifying! Cheers to all the folks who made Wafer.space possible. even if my silicon comes back totally useless it was a fun project. excited to make a video about it and share WS more widely with folks!

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BreakingTaps

pushed the button this morning, exciting / terrifying! Cheers to all the folks who made Wafer.space possible. even if my silicon comes back totally useless it was a fun project. excited to make a video about it and share WS more widely with folks!

Now you have your life back.

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at least for a little while, then I have to write an assembler/compiler/simulator and documentation

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AI is your friend

8:30 p.m.

5 minutes job

I found a few more minor bugs in my RTL. Cutting it a little close now!

10:25 p.m.

Turned of all the DRC and just crossing my fingers the precheck passes first try.

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asic destroyer

5 minutes job

hah, well, with a TTA all the tricky work is in the compiler (the compiler handles all the timing, register bypassing, etc etc)

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Tholin

Turned of all the DRC and just crossing my fingers the precheck passes first try.

Die Panik hatte ich auch gestern!

Tholin

I found a few more minor bugs in my RTL. Cutting it a little close now!

Same here

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If I don’t get zero antenna violations on this current run, its toast!

11:16 p.m.

Its clear

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11:16 p.m.

I opened the GDSII in KLayout and did a DRC check with my own eyeballs, since I’m just looking for the PDN bug.

Precheck running

BreakingTaps

pushed the button this morning, exciting / terrifying! Cheers to all the folks who made Wafer.space possible. even if my silicon comes back totally useless it was a fun project. excited to make a video about it and share WS more widely with folks!

Thank you for getting involved. I'm super excited to see the eventual video. If you need anything from us to help make the video better please don't hesitate to ask!

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Tholin

I opened the GDSII in KLayout and did a DRC check with my own eyeballs, since I’m just looking for the PDN bug.

I think that is called the "real industry flow"

Tholin

Turned of all the DRC and just crossing my fingers the precheck passes first try.

How does the precheck runtime on platform.wafer.space compare to your local runtime?

Tim 'mithro' Ansell

Thank you for getting involved. I'm super excited to see the eventual video. If you need anything from us to help make the video better please don't hesitate to ask!

I look forward to watching it!

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Tim 'mithro' Ansell

How does the precheck runtime on platform.wafer.space compare to your local runtime?

The precheck on platform.wafer.space is running at least 30 minutes faster (on a 4 to 5 hour check) compared to an AWS EC2 c6a.4xlarge instance. I will try to get more accurate numbers.

@Thorben - That is a useful comparison! The prechecker machines are 2 * Hetzner EX63 with Intel Core Ultra 7 265 (Arrow Lake) and 20 (8 Performance + 12 Efficiency) cores with 192GB of memory.

Tim 'mithro' Ansell

How does the precheck runtime on platform.wafer.space compare to your local runtime?

This is probably much faster than running the precheck locally.

Tim 'mithro' Ansell

I think that is called the "real industry flow"

Another example of real industry:

10:26 a.m.

That footnote won’t stop me from trying, because I choose not to read it!

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I wrote an article about the Wafer.Space GF180MCU Run 1 for the Japanese technology magazine I/O( https://www.kohgakusha.co.jp/io/ , The release date is the 18/Jan, Japan Only). I hope to see more submissions from Japan next time.

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Noritsuna Imamura

I wrote an article about the Wafer.Space GF180MCU Run 1 for the Japanese technology magazine I/O( https://www.kohgakusha.co.jp/io/ , The release date is the 18/Jan, Japan Only). I hope to see more submissions from Japan next time.

Do you need a high quality wafer.space logo to embed in it?

Tim 'mithro' Ansell

Do you need a high quality wafer.space logo to embed in it?

It has already been submitted, so it is not necessary.

Tim 'mithro' Ansell

@Thorben - That is a useful comparison! The prechecker machines are 2 * Hetzner EX63 with Intel Core Ultra 7 265 (Arrow Lake) and 20 (8 Performance + 12 Efficiency) cores with 192GB of memory.

Even better, averaging over 3 runs each, the 1.5.5. precheck on my design took ~6:04 hours on the AWS EC2 c6a.4xlarge instance and ~4:24 hours on platform.wafer.space. A full 100 minutes saved

I took part in a lightning talk competition for the Chicago Python users group. chipy For what it's worth I won!!

Here were the slides from my talk. https://docs.google.com/presentation/d/1aJlZnewZyQ7TH-IltYSDIhDfgPEW-apW4D6T0YGUq8k/edit?usp=sharing

LibreLane and Open Silicon

LibreLane and Open Silicon Python runs on chips. Python can be used to help make chips. A little on making chips, open silicon, and the state of the industry.

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@Tim 'mithro' Ansell @Leo Moser (mole99) It’s crazy — I started my gate-level simulation on December 3rd, and 18 days later, today December 21st, I can finally see the first kernel messages… maybe in two weeks it’ll boot into the console.

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12:45 p.m.

This gate-level simulation runs against the Micron SDRAM model, so we’re simulating real SDRAM accesses.

12:48 p.m.

We have two caches: a 2-way set-associative instruction cache and a direct-mapped data cache. We also have 4-way I-TLB and 4-way D-TLB MMU caches.

12:49 p.m.

I can’t believe that 300k lines of Verilog generated by Yosys (thanx @Lofty) can actually work… that’s crazy. (edited)

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12:52 p.m.

@Leo Moser (mole99) helped a lot with LibreLane, and his name is immortalized on the chip. Thanks, Leo Moser. (edited)

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facts about my remote machine: cpu: AMD Ryzen Threadripper 7960X s (48) @ 5.3GHz gpu: AMD ATI Radeon RX 470/480/570/570X/580/580X/590 memory: 47.43 GiB / 251.20 GiB (18%)

asic destroyer

@Tim 'mithro' Ansell @Leo Moser (mole99) It’s crazy — I started my gate-level simulation on December 3rd, and 18 days later, today December 21st, I can finally see the first kernel messages… maybe in two weeks it’ll boot into the console.

I wouldn't have the patience to wait for that!

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Tim 'mithro' Ansell

I wouldn't have the patience to wait for that!

Linux booting is great, but that’s an integration milestone, not verification. Nobody runs full OS workloads in gate level simulation. That’s what FPGA or emulation is for (Shen & Lipasti). https://books.google.de/books/about/Modern_Processor_Design.html?id=VIWLAAAACAAJ&redir_esc=y

Modern Processor Design

asic destroyer

Linux booting is great, but that’s an integration milestone, not verification. Nobody runs full OS workloads in gate level simulation. That’s what FPGA or emulation is for (Shen & Lipasti). https://books.google.de/books/about/Modern_Processor_Design.html?id=VIWLAAAACAAJ&redir_esc=y

I have lots of thoughts about modern processor design coming from my time in Google's compiler & toolchain group.

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9:34 p.m.

But I already try to do way too many things at the same time

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@Tim 'mithro' Ansell , I was excited for three weeks and checked every day, monitoring internal states. I wasn’t sure it would run. If it had run on my local PC, the noise would’ve killed me. Seeing the first output on remote machine today, I shouted with joy.

after the final reticle is stitched and approved by GF, would love to see an image of the combined GDS for it

4:52 p.m.

would be neat to see all the projects laid out

Unfortunately while a number of projects have put a bunch of effort into aesthetics, some designs are just "how much logic can we cram into the die area" like mine ^^;

5:26 p.m.

Like, mine is 110kgates :p

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Lofty

Unfortunately while a number of projects have put a bunch of effort into aesthetics, some designs are just "how much logic can we cram into the die area" like mine ^^;

How do you calculate it?

asic destroyer

How do you calculate it?

Yosys tells you

stage 6?

5:33 p.m.

I have in metrics.csv design__instance__count__stdcell,136515 (edited)

You can use `s to avoid formatting: "`a__b__c`"->a__b__c

5:37 p.m.

(Or backslashes if you don't want the code formatting)

Lofty

Unfortunately while a number of projects have put a bunch of effort into aesthetics, some designs are just "how much logic can we cram into the die area" like mine ^^;

hehe mine is similar, bunch of sram blocks and logic crammed in the middle

=== chip_top ===

   Number of wires:             115772
   Number of wire bits:         115823
   Number of public wires:        7676
   Number of public wire bits:    7727
   Number of ports:                  5
   Number of port bits:             56
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:             115789

yosys-synthesis.log

=== chip_top ===

   Number of wires:              66338
   Number of wire bits:          66391
   Number of public wires:       10925
   Number of public wire bits:   10978
   Number of ports:                  3
   Number of port bits:             56
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              66210

5:50 p.m.

@Lofty, I have a question for understanding: behind the standard cells, are there smaller/bigger “cells” like SRAM? I’d like to know how many transistors there are.

asic destroyer

@Lofty, I have a question for understanding: behind the standard cells, are there smaller/bigger “cells” like SRAM? I’d like to know how many transistors there are.

it's worth pointing out that yosys' definition of cell is "an instantiated thing", which would include SRAM blocks, yes

5:51 p.m.

but even then, it's a bit tricky to count transistors

I’m using 21 SRAM 512×8 cells.

5:54 p.m.

I was only confused because of the word gates.

asic destroyer

I have in metrics.csv design__instance__count__stdcell,136515 (edited)

$ grep "design__instance__count__stdcell" final/metrics.csv
design__instance__count__stdcell,212713

asic destroyer

stage 6?

@Lofty

yes, stage 6

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asic destroyer

I have in metrics.csv design__instance__count__stdcell,136515 (edited)

sorry! Wrong reply

6:01 p.m.

But it's not transistor count

as I said, transistor count is hard to calculate.

I’m not very familiar with this. I thought the primitives might contain such metadata.

yes and no.

6:05 p.m.

the "source" of the gates is gonna be the spice simulation models

6:05 p.m.

but...two transistors in parallel behave identically to a single transistor that is twice as wide

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6:07 p.m.

and this isn't just theoretical

6:07 p.m.

.SUBCKT gf180mcu_fd_sc_mcu7t5v0__inv_1 I ZN VDD VNW VPW VSS
X_i_0 ZN I VSS VPW nfet_05v0 W=8.2e-07 L=6e-07
X_i_1 ZN I VDD VNW pfet_05v0 W=1.22e-06 L=5e-07
.ENDS

here's a size-1 inverter

6:08 p.m.

.SUBCKT gf180mcu_fd_sc_mcu7t5v0__inv_2 I ZN VDD VNW VPW VSS
X_i_0_0 ZN I VSS VPW nfet_05v0 W=8.2e-07 L=6e-07
X_i_0_1 VSS I ZN VPW nfet_05v0 W=8.2e-07 L=6e-07
X_i_1_0 ZN I VDD VNW pfet_05v0 W=1.22e-06 L=5e-07
X_i_1_1 VDD I ZN VNW pfet_05v0 W=1.22e-06 L=5e-07
.ENDS

here's a size-2 inverter

6:08 p.m.

so, do we say that the size-2 inverter has 4 transistors and the size-1 inverter has 2?

6:08 p.m.

even though the size-2 inverter can be implemented with 2 transistors of twice the width?

6:09 p.m.

I don't know, I think "number of transistors" is not a useful metric

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cat ./libs.ref/gf180mcu_fd_ip_sram/spice/gf180mcu_fd_ip_sram__sram512x8m8wm1.spice | grep fet | wc -l
2189

6:16 p.m.

crazy, why so little?

6:16 p.m.

@tnt

4T cells perhaps? 2048 for the bits and rest is the plumbing?

IDK

It's definitely a 6T cell

6:20 p.m.

But it's also not a flat model ...

6:20 p.m.

It uses subckt instances and such ...

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With a 6T cell, we have around 30k to 40k transistors.

I miss the sound of running LibreLane ASIC builds. My room gets so hot when my i9-14900K is under load.

can always start on your next tapeout project

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asic destroyer

I miss the sound of running LibreLane ASIC builds. My room gets so hot when my i9-14900K is under load.

Ha, it's 45C here in Adelaide at the moment. I'm keeping most of my servers in the off position at the moment.

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Tim 'mithro' Ansell

Ha, it's 45C here in Adelaide at the moment. I'm keeping most of my servers in the off position at the moment.

Holy shit that's hot. That's 113 in Freedom Units for those that need it Stay cool!

@Tim 'mithro' Ansell Would you guys be looking at sky130nm as well or is it just gf180nm for now?

chvsnaveen12

@Tim 'mithro' Ansell Would you guys be looking at sky130nm as well or is it just gf180nm for now?

Just gf180mcu