wafer.space Community - 🤪-off-topic

Looking like Tiny Tapeout may need a second slot

@Andrew Wingate Repo already ready https://github.com/TinyTapeout/tinytapeout-gf-26b

tnt

@Andrew Wingate Repo already ready https://github.com/TinyTapeout/tinytapeout-gf-26b

Nice!! You guys should consider showing more Open Shuttles on your homepage https://www.tinytapeout.com/

Tiny Tapeout - Tiny Tapeout

Tiny Tapeout makes it more accessible than ever to get your designs manufactured on a real chip!

But they're not open yet

( As in, you can't submit it yet ).

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100% filled!! That's awesome Tiny Tapeout Team!!!

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Who from this crowd is going to be at FSiC 2026 (https://wiki.f-si.org/index.php/FSiC2026) in Ljubljana in three weeks? I see that at least @Leo Moser (mole99), @Simi, @Chips4Makers aka Staf Verhaegen and myself are giving presentations there. Anybody else presenting or attending?

FSiC2026

Free Silicon Conference 2026 (FSiC2026) - free and open-source EDA and free and open-source silicon, 6-8 July 2026, University of Ljubljana, Slovenia

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1:02 p.m.

I'm presenting too.

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1:03 p.m.

I'm presenting work I did on a custom SRAM register file on sky130 and the test chips are currently with fedex which was supposed to delivery today but delayed it to tomorrow ... result of which will decide if my talk is going to be a post-mortem or not

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Ah yes, right on Monday morning, I see. Looking forward to it

Wait, are you Thorben Moos btw ?

Yes

Oh your bio link seems to indicate yes

When looking at the program I had noticed someone else was coming from Belgium and even more from my Alma Mater

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1:08 p.m.

Did you do the bonding at Winfab ? I was pondering pinging Christian (Renaux) about getting some time on the bonding machine if I ever needed to ...

Ha, very nice, did not know you're from here

Yes, Christian from Winfab brought me the bonded samples on Friday. They are a little bit protective of their bonding machine at the moment, but as far as I know it's not used too much. And they seem to be getting a new semi-automated one soon (for some definition of soon). Then there's probably more availability and you have a fallback if one is temporarily out of order.

Yeah, I studied there INGI then ELEC (was still FSA at the time). And worked for intopix (a ucl spinoff) even before it was spunoff and I so I was in Maxwell for a year or so and also did some odd jobs for Quisquater and FX

Cool, will be a pleasure to chat with you in Slovenia

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Same

now that I'm no longer actively suffering from whatever that bread contained, let's hurry back to get this serializer worked on before anything is too late for it.

VCO core, with enough fingers to let me tap off a single-finger feed to a clock tree without this causing undue load, probably do be aiming at exactly the 2.5 GHz though, maybe probably better like 3 GHz to handle a bit of layout parasitics and process variation. Then clock buffer. Then a latch fast enough to accomplish a DIV2 off of this. Then a mux2 at least that would act as the final MUX in a C2 arrangement. Then draw at least a plain serializer MUX tree up to have a fallback to submit; the base clock buf cells should be sufficient speed. After, see how much time is left, and see how good an inductor would be needed to clock the input-multiplexed current-mode C4 MUX (the pseudo-nmos style architecture of it). If success, try to make an inductor that's good enough for pulling off a C4 architecture. If success, go and implement the C4 with FIR taps furnished at the CLK/2 level (i.e., C8). If inductor trials not success, instead go for some FIR taps at still CLK/2.

You're not targetting gf0p3 are you ?

tnt

You're not targetting gf0p3 are you ?

Well, kinda; thanks for me realizing now that it's not a week but just 4 days.

Gave a lightning talk at the Chicago Python Users Group (Chipy) Hard to talk about much of anything in 5 min, but figured I'd share https://youtu.be/0ROkPEg5Jl8

Chicago Python Users Group

ChiPy main Meeting 2026.06 - Andrew Wingate - Open Silicon ...

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namibj

VCO core, with enough fingers to let me tap off a single-finger feed to a clock tree without this causing undue load, probably do be aiming at exactly the 2.5 GHz though, maybe probably better like 3 GHz to handle a bit of layout parasitics and process variation. Then clock buffer. Then a latch fast enough to accomplish a DIV2 off of this. Then a mux2 at least that would act as the final MUX in a C2 arrangement. Then draw at least a plain serializer MUX tree up to have a fallback to submit; the base clock buf cells should be sufficient speed. After, see how much time is left, and see how good an inductor would be needed to clock the input-multiplexed current-mode C4 MUX (the pseudo-nmos style architecture of it). If success, try to make an inductor that's good enough for pulling off a C4 architecture. If success, go and implement the C4 with FIR taps furnished at the CLK/2 level (i.e., C8). If inductor trials not success, instead go for some FIR taps at still CLK/2.

Oscillation success:

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clock buffer at FO4, though with limited fancyness of harness

7:22 p.m.

food break; then a latch that can DIV2 off of that.

namibj

clock buffer at FO4, though with limited fancyness of harness

forward device's drain current density oscillating between approximately 16 and 72 A/m

namibj

VCO core, with enough fingers to let me tap off a single-finger feed to a clock tree without this causing undue load, probably do be aiming at exactly the 2.5 GHz though, maybe probably better like 3 GHz to handle a bit of layout parasitics and process variation. Then clock buffer. Then a latch fast enough to accomplish a DIV2 off of this. Then a mux2 at least that would act as the final MUX in a C2 arrangement. Then draw at least a plain serializer MUX tree up to have a fallback to submit; the base clock buf cells should be sufficient speed. After, see how much time is left, and see how good an inductor would be needed to clock the input-multiplexed current-mode C4 MUX (the pseudo-nmos style architecture of it). If success, try to make an inductor that's good enough for pulling off a C4 architecture. If success, go and implement the C4 with FIR taps furnished at the CLK/2 level (i.e., C8). If inductor trials not success, instead go for some FIR taps at still CLK/2.

thanks past-me for making a plan so present-me doesn't wander off of the minimum-viable-submission route.

pair of latches be DIV2-ing

namibj

Click to see attachment 🖼️

16 half speed latches @ approx 100 mW each + 4 full-speed latches @ approx 400 mW each + 4 full-speed MUX2 @ somewhere_between_those each, so a "total" of 3.6 ~ 4.8 mW, not counting the clock feed (quadrature phases at both full clock and half clock), and not counting the output predriver limiting amplifier (edited)

namibj

Click to see attachment 🖼️

yeah I don't want to draw the rest by hand, real ugly to tune that way....

I designed some silicon lol. Maybe I will talk about it someday, this was more of an exercise than something I care about. A portion of the above was to understand the toolchain so I could make this docker based starter thing. Some people have asked me for it, so now it exist @carlfk https://github.com/evezor/wafer_space_docker_based_starter_kit If someone would mind giving it a quick overview, that would be lovely. Thanks and hope it's helpful!

GitHub - evezor/wafer_space_docker_based_starter_kit

Contribute to evezor/wafer_space_docker_based_starter_kit development by creating an account on GitHub.

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@needsadrink|woke Tim is asking me to look into getting the old Skywater masks from the google mpw run. Would you mind giving me a little assistance there? Please DM me. Thanks

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namibj

Click to see attachment 🖼️

How do you draw these diagrams? Just by hand in some tool or?

Tim 'mithro' Ansell

How do you draw these diagrams? Just by hand in some tool or?

looks like draw.io to me

Tim 'mithro' Ansell

How do you draw these diagrams? Just by hand in some tool or?

Hand in drawio.

11:34 a.m.

I'd prefer a less-hand way to get free verification out of it.

11:34 a.m.

I can send you the source this evening if you want.

namibj

I'd prefer a less-hand way to get free verification out of it.

Check out https://github.com/hneemann/digital !

GitHub - hneemann/Digital: A digital logic designer and circuit sim...

A digital logic designer and circuit simulator. Contribute to hneemann/Digital development by creating an account on GitHub.

Trevor Peyton

Check out https://github.com/hneemann/digital !

Cool! There's also Wokwi which you can use to create designs for Tiny Tapeout https://tinytapeout.com/digital_design/wokwi/

Getting started with our digital design tool - Tiny Tapeout

Learn the basics of Wokwi

For smallish things netlistsvg worked okay for a while

As a follow up, https://github.com/logisim-evolution/logisim-evolution this is an alternative program also. I used Digital when I was at uni and it was really nice.

GitHub - logisim-evolution/logisim-evolution: Digital logic design ...

Digital logic design tool and simulator. Contribute to logisim-evolution/logisim-evolution development by creating an account on GitHub.

I'm melting

But I do see hope for the 4:1 MUX (and required clocking feed) getting tested as part of Run2.

40 tomorrow, 39 sunday

10:01 a.m.

Gonna have a fun weekend

10:01 a.m.

But not gonna stop working

Tholin

But not gonna stop working

I'll ask and if I'm lucky I'll figure out how to remote into my workstation from the office

Would be awesome for the heatwave situation. Should just need a sufficiently effective codec to keep my sanity despite the inevitable lag.

For all the Visual Studio developers out there: I've released my best ever version of the Verilog Syntax Highlighter Extension. https://marketplace.visualstudio.com/items?itemName=gojimmypi.gojimmypi-verilog-language-extension

VerilogLanguage - Visual Studio Marketplace

Extension for Visual Studio - Verilog Extension for Visual Studio. (classifier extension). Implements the Verilog Language Extension allowing user-definable keyword colorization. Useful for FPGA, ASIC and other RTL development.

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Tholin

40 tomorrow, 39 sunday

hopefully low humidity!

not perfect, but pretty happy how this turned out

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BreakingTaps

not perfect, but pretty happy how this turned out

Looks great!!

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