wafer.space Community - 🤪-off-topic

Can i add custom chip art on the top and bottom right corner ( similar to the wafer space logo and qr in the left ) ? Or can i only add inside the pad ring ?

Deepak

Can i add custom chip art on the top and bottom right corner ( similar to the wafer space logo and qr in the left ) ? Or can i only add inside the pad ring ?

yep, you can! I have a little image on the bottom right of mine. I think the top right may be reserved for an arrow this time around (to help the wirebonding alignment) so I think we can't use that corner

BreakingTaps

yep, you can! I have a little image on the bottom right of mine. I think the top right may be reserved for an arrow this time around (to help the wirebonding alignment) so I think we can't use that corner

Hey sure got it thank you much Will use only the bottom right

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You are also free to replace the wafer.space logo on the top left. The precheck only checks the bottom left and the top right, if you have CoB enabled.

hah, I was skimming an old Adapteva parallela forum post looking for something and saw @tnt. Guess I shouldn't be surprised

@BreakingTaps Good old times

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Chinese open source 55nm PDK? https://github.com/openecos-projects/icsprout55-pdk (Found via https://mp.weixin.qq.com/s/hDV_g7wtZvxg2IIAZ1XvGA)

GitHub - openecos-projects/icsprout55-pdk: 55nm CMOS Open Source PD...

55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd. (ICS55 for short). - openecos-projects/icsprout55-pdk

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@BreakingTaps It was mentionned at FSiC last year but ... Not really open. If you look at it there is not much there. You get a standard cell library but only abstract view, no GDS. No DRC rules or any device simulation model. So you can "assemble" a chip with purely digital design but nothing more, nothing custom, ...

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5:02 a.m.

So you can do basically the same you can do with a FPGA.

ah, welp

5:04 a.m.

maybe some day we'll get a 50-65nm open PDK

I'll just leave this here.... -# Sometimes I feel I should not be allowed to use tools

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3:50 p.m.

It's DRC clean btw

haha that's amazing. i can't imagine making it DRC clean too

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Next week at FSiC 2026, we'll be introducing the latest updates on the ics55 pdk, eda tools, and design platform, etc. We have also upgraded the ics55 pdk from tier1 to tier 0. Moving forward, we're planning the roadmap, restructuring the repo based on sky130, gfmcu180, ihp130, and will be gradually releasing the remaining files over the next some months.

Andrew Wingate

I'll just leave this here.... -# Sometimes I feel I should not be allowed to use tools

Maybe we should indeed re-evaluate your permission to use tools

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Machine Kid myyerrol

Next week at FSiC 2026, we'll be introducing the latest updates on the ics55 pdk, eda tools, and design platform, etc. We have also upgraded the ics55 pdk from tier1 to tier 0. Moving forward, we're planning the roadmap, restructuring the repo based on sky130, gfmcu180, ihp130, and will be gradually releasing the remaining files over the next some months.

Are you connected to ics55 in some way?

Yes, we have integrated the ics55 pdk to ECOS Studio, but now it can only generate partial gds because of some key files haven't be released, so we need to do some works (like DRC/LVS/PEX) by ourselves.

4:58 a.m.

I read the IHP's slide at the FSiC 2026, their pdk and open mpw shuttle is fantastic, so we will learn from ihp sg13g2, to port more open-source eda tools to ics55, and release remaining data as soon as possilbe.

5:04 a.m.

And "EuroCDP Open-source PDKS and EDA tooling recommendations" book also give us great help-a good comparison table.

5:06 a.m.

There was an attempt at compression ...

-rw-r--r--  1 gp gp 754346 Jul 11 21:24 chip_top.oas
-rw-r--r--  1 gp gp 727632 Jul 11 21:24 chip_top.oas.gz

Has anyone figured out an easy way to do GDS art?

Essen

There was an attempt at compression ...

-rw-r--r--  1 gp gp 754346 Jul 11 21:24 chip_top.oas
-rw-r--r--  1 gp gp 727632 Jul 11 21:24 chip_top.oas.gz

at least the size went down and not up!

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A44

Has anyone figured out an easy way to do GDS art?

Pixel art in magic

... Okay there might be simpler ... (edited)

A44

Has anyone figured out an easy way to do GDS art?

Have a look at the FSiC talks from last year, there was one on how the pulp team do their art

The current diet: I am sure I can live off this for a few more days ... (edited)

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Essen

The current diet: I am sure I can live off this for a few more days ... (edited)

I miss HEB

6:45 p.m.

Sometimes I have dreams about HEB salsa, those are good dreams

Essen started a thread. 2026-07-14 7:03 p.m.

just cuz

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4

that's a great shot!

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Andrew Wingate

just cuz

Comes out so well !

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@Tim 'mithro' Ansell @Leo Moser (mole99) @Andrew Wingate https://bsky.app/profile/did:plc:ux7kshhvcz763o5eu7rzggig/post/3mqtzirifck2p

logic destroyer (@logicdestroyer.bsky.social)

-# ↩ logic destroyer (@logicdestroyer.bsky.social) It’s alive, and I could probably push the clock another 10 MHz, but I’m not interested in that right now. We’re running at 24 MHz for the time being.

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This is so cool to see!

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8:50 p.m.

7 hours uptime and still running linux

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@asic destroyer - That is in no way off-topic! That is #general content.

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very impressed you have a working DRAM controller! from the little I've dabbled it feels very non-negligible achievement!

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BreakingTaps

very impressed you have a working DRAM controller! from the little I've dabbled it feels very non-negligible achievement!

I got lucky that everything just fit. In the end it used the very last pin.

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How hot do your chips get? I'm measuring 35°C on the top surface of the chip. @Leo Moser (mole99) @Andrew Wingate @BreakingTaps @RebelMike @Tholin @Greg ...

What clock speed?

I hadn't even thought of that. Right now I'm still running at 24 MHz because I'm too lazy to hook up an external clock. But in theory, 35–40 MHz should be achievable.

35° is normal at 24MHz

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@Tholin Looking at how power scales with frequency, I figure the chip would end up at around 45°C at most. That should still be fine, right? (edited)

Yes

thanx

Tholin

35° is normal at 24MHz

I thought the chip might be running a bit hotter because of all the I/O activity.

Cross posting a message from @Tim Edwards

Calling on all analog designers. . . the Chipalooza Challenge is back! Looking for high-quality open source analog circuits that support system-on-chip. This is a 2-year-long project with five individual challenges covering the three major open source PDKs, with the goal of making SoC designs with analog components portable across all of the major open PDKs. It costs nothing but your (valuable) design time, and awards will be given for successful completed circuits. To participate, join the https://fossi-chat.org forum and go to hashtag#Chipalooza for details and updates!

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asic destroyer

@Tim 'mithro' Ansell @Leo Moser (mole99) @Andrew Wingate https://bsky.app/profile/did:plc:ux7kshhvcz763o5eu7rzggig/post/3mqtzirifck2p

@Tim 'mithro' Ansell @Leo Moser (mole99) @Andrew Wingate

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5

I haven't clocked mine faster than like 5hz so far

so not sure how hot it will get. need to carve out some more time to work on bringup

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Chipalooza Challenge is off-topic for now but there will be a GF180MCU/Wafer.Space version of it coming soon enough. @Andrew Wingate : Thanks for posting! @Tim 'mithro' Ansell : My proposed schedule assumes a Wafer.Space tapeout some time around Feb. 1 next year, so if that target is way off the mark, please let me know. I am also targeting a 2nd Wafer.Space tapeout Aug. 1 of next year, which is even more of a wild guess.

Tim Edwards

Chipalooza Challenge is off-topic for now but there will be a GF180MCU/Wafer.Space version of it coming soon enough. @Andrew Wingate : Thanks for posting! @Tim 'mithro' Ansell : My proposed schedule assumes a Wafer.Space tapeout some time around Feb. 1 next year, so if that target is way off the mark, please let me know. I am also targeting a 2nd Wafer.Space tapeout Aug. 1 of next year, which is even more of a wild guess.

Sure thing, sounds awesome. DM'd you a bit about super rough timing outlines.

asic destroyer

@Tim 'mithro' Ansell @Leo Moser (mole99) @Andrew Wingate

At 24 MHz, the board draws 80 mA under normal operation and 100 mA when accessing the SD card over SPI. (edited)

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asic destroyer

At 24 MHz, the board draws 80 mA under normal operation and 100 mA when accessing the SD card over SPI. (edited)

Dunno if that is good or bad?

Tim 'mithro' Ansell

Dunno if that is good or bad?

good! sdram, mcu, led, sd card, uart, regulator, flash , wires , pcb and asic (edited)

If there's a 28 nm process available, I'd love to build it. https://bsky.app/profile/logicdestroyer.bsky.social/post/3mravzo3xqk2r

Logic Destroyer — Proven in Silicon. (@logicdestroyer.bsky.social)

StealthV can now edit C programs under X11 at XGA+ resolution, compile them with TCC, and run them. Not bad.

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If any of you will be at Teardown 2026 I'd love to meet you! Come find me. I have also been asked to talk and will have the Sat 1:30 slot. My slides can be seen here: https://anfroholic.github.io/teardown2026_talk

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Essen started a thread. 2026-07-24 7:39 a.m.

https://bsky.app/profile/logicdestroyer.bsky.social/post/3mrfwa2dmjk2p

Logic Destroyer — Proven in Silicon. (@logicdestroyer.bsky.social)

My custom Linux RISC-V SoC just became an arcade game machine. I set out to build a Unix RISC-V workstation. Now it's running games on my custom Linux RISC-V StealthV SoC. The games run under Linux with virtual memory and render directly to the Linux framebuffer, not bare metal.

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https://bsky.app/profile/did:plc:ux7kshhvcz763o5eu7rzggig/post/3mrndnclrqk2x

Logic Destroyer — Proven in Silicon. (@logicdestroyer.bsky.social)

MP3 playback under Linux while running X11 Another milestone for my custom StealthV RISC-V SoC. The system now plays 48 kHz, 256 kbps CBR MP3 audio entirely in software while running Linux and X11. No dedicated MP3 decoder. Everything is handled by my own RISC-V CPU and hardware.

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