wafer.space Community - 🤪-off-topic

Interesting talk about some older (80s) architectures that never panned out. I'm excited to see new (potentially old) and novel architectures come online soon!! https://www.youtube.com/watch?v=7Cd4NQu1OG0

FUTO

The History of Forgotten Chips

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oooooh! queuing that up for a watch, love me some weird architectures!

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(RPI represent

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I have been reading though @LukeW's ws run1 submission codebase, and the comments are hilarious. Here is a random selection on setting a false path constraint on a sdff for building a pseudo dff with enable: The Machine Spirit is angry. Brother, get the holy oils (edited)

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8:17 p.m.

( Yes, I read codebases ... I am actually ancient ... This is but a mirage created by a wonderful moisturizer ... ) (edited)

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My dual-core keeps getting more and more mature. I’m already getting over 2 CoreMark/MHz out of it, and I’m going to turn it into a quad-core next. Then I think the project is basically done. The only thing that sucks is that I can’t turn it into an ASIC. I need a smaller process node. I really wanted to build an SMP Linux chip. <- @Tim 'mithro' Ansell

https://x.com/splinedrive/status/2095241420315795911 (edited)

Logic Destroyer (@splinedrive)

Bro, what the hell did I build? My KianV RISC-V Linux/NetBSD SoC is running Linux 7.2.2 now. I can run desktop apps with an analog clock whose second hand actually keeps perfect time, listen to 256 kbps MP3s, write and compile C/C++ natively with GCC/G++, and even play Doom while listening to MP3…

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Essen

I have been reading though @LukeW's ws run1 submission codebase, and the comments are hilarious. Here is a random selection on setting a false path constraint on a sdff for building a pseudo dff with enable: The Machine Spirit is angry. Brother, get the holy oils (edited)

Yeah, that saved my design. I knew nothing about ASICs. Luckily Luke taught me about reset. Pure luck. I really don’t want any shorts. https://github.com/splinedrive/gf180mcu-kianv-rv32ima-sv32/blob/2483ecb9cc00f52dbc2a226fda348d8c139e707c/src/chip_top.sv#L214

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boards arrived! hope they work

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Essen

Flex PCB have arrived

Oh in the future I'd probably not skip the back side coverlay over the die. And I'd probably prefer to keep the backside ground plane over the die just not over the pads like that; and in the future don't align the hatching lines or other lines orthogonal to the major bending; i.e., try to keep copper lines from being parallel to the cylinder axis around which the board will be bent. In this case, it'd better be 45° rotated from now.

Andrew Wingate

Yes, it ended up being one of those, "We can do both, it's the same for us" But then watching them when it was non linear it took a lot more setup and caused other problems that took a bunch of extra time.

Even if they're aligned with the bond wire's axis?

namibj

Even if they're aligned with the bond wire's axis?

Alignment with the bond wire has no correlation to anything with setup. Landing locations are just chosen more or less arbitrarily. When the landing locations are linear it seemed like it was easier for them to edit when problems came up, as they could sortof bulk edit. When all the landings were along some arc there was nothing to reference as they're all independent. I hope I'm explaining that right

Andrew Wingate

Alignment with the bond wire has no correlation to anything with setup. Landing locations are just chosen more or less arbitrarily. When the landing locations are linear it seemed like it was easier for them to edit when problems came up, as they could sortof bulk edit. When all the landings were along some arc there was nothing to reference as they're all independent. I hope I'm explaining that right

Ohhhh

5:28 p.m.

I'd assume then a 2/3 row staggered landing pad geometry with otherwise nice axis aligned grid spacing would not be substantially worse to program and would get much more density than the current single row non-staggered one? Like, the pads on the PCB are much coarser than PCB DRC minimums for copper width/spacing, and those are again coarser than the die side bond pad minimum spacing, and IIRC wedge bonds are a symmetric tool action to attach the wire to the substrate? Just that to end the wire it gets ripped off kinda horizontally in the same direction it came from after attaching to the surface; while ball bonding is very different between start and end action?

Basically the tool's UI has a thing where you can say I'm placing 10 bonds in a row and then you mark the first and last bond and it places them evenly spaced between them.

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ohhhhh. good/fair

The whole configuration is manual and entered via a keyboard on a computer.

4:27 a.m.

I'm still very interested in potentially purchasing a wire bonding machine and retrofitting the control system with a RPi that can do all this stuff automatically without having any human do setup.

4:27 a.m.

It could then collect photos of the bonds as they are done as well.

hmmmm, yeah, I'm surprised it's done all so manually still today, not even loaded from a floppy levels of pre-programming....

Tim 'mithro' Ansell

It could then collect photos of the bonds as they are done as well.

and presumably bespoke bonding configurations as long as they can get checked by some reasonable DRC gate that keeps the machine from choking /hitting anything in the porcess?