wafer.space Community - fpgas-online

This is a channel dedicated to the continued development of https://fpgas.online/ which has previously primarily been developed by @carlfk with the funding provided by @Tim 'mithro' Ansell The two current highest priority items for development are:

Getting all Tiny Tapeout boards onto the site in similar manner as existing Tiny Tapeout 6 board.

Getting @bunnie's NeTV2 boards into the site

Other lower priority items include:

Getting Tim's other FPGAs into the site, these include @Xobs's Fomu (Tim has pratically unlimited), @Greg's Butterstick (Tim has 8 devices) and @GoranMahovlic's ULX3S (Tim has ~12 devices), GreatScottGadget's Cythion (Tim has ~12 devices) hardware onto the site.

Actually using fpgas.online for testing open source FPGA projects.

If anyone has ideas on how to get more people to use the site, that is also something we are very interested in. (edited)

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Tim 'mithro' Ansell pinned a message to this channel. 2026-01-19 3:20 a.m.

FYI - @Tisham Dhar (CSIRO EASI) / @carlfk / @asic destroyer / @Greg

3:21 a.m.

@carlfk - @Tisham Dhar (CSIRO EASI) is looking at trying to get my NeTV2 hardware into https://fpgas.online

3:22 a.m.

@carlfk - IIRC I left a bunch of NiteFury with RPi Compute modules and Compute Cluster blades with you?

3:24 a.m.

@LukeW - @Tisham Dhar (CSIRO EASI) is having some issues with programming the NeTV2 using an RPi 5 because the GPIO have moved from the Broadcom device to the RP1 hardware. I believe the PIO hardware in the RP1 should allow us to do significantly better JTAG driver than what is currently in OpenOCD / openfpgaloader.

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3:32 a.m.

My stack looks like this now, since I am loading gateware using RPi 4 and accessing PCI-e from Rpi5

3:35 a.m.

The current pin assignments are here using the old driver : https://github.com/AlphamaxMedia/netv2mvp-scripts/blob/master/alphamax-rpi.cfg

netv2mvp-scripts/alphamax-rpi.cfg at master · AlphamaxMedia/netv2m...

Various scripts for NeTV2MVP. Contribute to AlphamaxMedia/netv2mvp-scripts development by creating an account on GitHub.

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This is awesome! Way to go @carlfk! I've been seeing a lot of work being done here on other channels. Looking forward to seeing more.

3:52 a.m.

I was having a thought the other day. I know that @asic destroyer ran a whole simulation of his new linux asic, and was curious what size FPGA you would need to do that same thing, and if that would even be applicable here. I assume that is something larger than you could load on to one of the ARTYboards?

Captured rpi4 working config here : https://github.com/AlphamaxMedia/netv2mvp-scripts/pull/1

Config working with upstream openocd and rpi4 by whatnick · Pull R...

Working version with upstream openocd and pcileech as sample gateware /opt/openocd/src/openocd -c &quot;set BSCAN_FILE /home/k8s/netv2mvp-scripts/bscan_spi_xc7a100t.bit&quot; -c &quot;s...

8:43 a.m.

May need a kernel module to make pcileech arrive as a device on the raspi5 pci bus, I will try an M2 Sata to make sure PCI is indeed connected. (edited)

8:50 a.m.

I think a NiteFury / 200T can run a Linux ASIC gateware, depends how complicated it is.

This looks useful for the NeTV2 to slot in : https://geekworm.com/en-au/products/x1010?srsltid=AfmBOopO2oOKLbdXuqHiQd1Poq-Cz4X5Bp7eHgrN7mOhQquOnVFMYTlX

Geekworm X1010 PCIe FFC to Standard PCIe x4 Slot Expansion Board for R

The X1010 PCIe FFC connector to standard PCIe x4 slot expansion board, designed for effortless integration of various PCIe add-on cards such as Graphics cards (GPUs), RAID cards, USB expansion cards, High-speed ethernet cards, Wi-Fi cards, and SSDs to enhance the capabilities of your Raspberry Pi 5. The X1010 features versatile power options, su...

Will need a ribbon to wire up the JTAG

What are you jtag-ing?

8:21 p.m.

I have a pi hat with a pico on it that does jtag things

8:22 p.m.

https://github.com/CarlFK/pj

GitHub - CarlFK/pj: Pi JTAG hat

Pi JTAG hat. Contribute to CarlFK/pj development by creating an account on GitHub.

I am jtaging the NeTV2

8:23 p.m.

The bitbang JTAG from old references no longer works on Raspi 5.

my pj project above was mean to debug pi boot - the pico PIO pins are routed to the Pi jgag. but I also added a header so they could be hooked to somethint else (like NeTV2)

8:36 p.m.

I have no idea if this is helpful, and now I am wondering if being hoked to both will be a problem (seems like it)

8:37 p.m.

oh right, the idea was don't plug the hat into the pi, then it isn't hooked to the pi jtag.

er.. looking at it in Kicad, there is no jtag header. I guess the idea is I can use the pi hat header holes for something else if it isn't on a pi

8:54 p.m.

I am ordering some other boards this week, $5 for boards, $20 shipping. I can tweek and add more PJ boards if you think there is some chance of being useful

8:55 p.m.

I am 1/2 thnking I need that jgag header I thought was there. but not if no one wants it.

We already have a mezzanine in the current stack that breaks out the PCI Express, ideally we need a board under like the sample PCI express above and a JTAG like yours wired from the top to the JTAG pins of the NeTV and perhaps RX / TX , power etc.

9:13 p.m.

9:14 p.m.

NeTV JTAG that wires itself to the Pi looks like this. This was a good idea for older pi's, since you could bitbang JTAG on those.

9:15 p.m.

And have RX/TX to debug or shell into it after gateware loads.

9:18 p.m.

Out of interest, what kind of cable does the RPi PIO JTAG look like to openOCD and openfpgaloader?

I am going to plead ignorance. consider me just the board manufacture that doesn't really know how it works

9:25 p.m.

the pico/pio -> pi was desinged by Clever who is makign an open source boot loder to replace broadcom's boot.bin

9:26 p.m.

hea had a tangle of wires on his work bench connecting pico to pi, and I made something nice

9:27 p.m.

do you have the netv2 schematic URL handy?

Hard to find : https://github.com/AlphamaxMedia/netv2-mainboard/blob/master/netv2mvp-pvt1.pdf

netv2-mainboard/netv2mvp-pvt1.pdf at master · AlphamaxMedia/netv2-...

Release directory for NeTV2 main PCBA files. Contribute to AlphamaxMedia/netv2-mainboard development by creating an account on GitHub.

Andrew Wingate

I was having a thought the other day. I know that @asic destroyer ran a whole simulation of his new linux asic, and was curious what size FPGA you would need to do that same thing, and if that would even be applicable here. I assume that is something larger than you could load on to one of the ARTYboards?

I believe you can use the ulx3s to simulate his design.

Tim 'mithro' Ansell

I believe you can use the ulx3s to simulate his design.

I guess, I was wondering if someone would be able to easily use your guy's internet facing FPGA's to validate designs somehow. Seems they aren't up to the task.

Andrew Wingate

I guess, I was wondering if someone would be able to easily use your guy's internet facing FPGA's to validate designs somehow. Seems they aren't up to the task.

Well, it's kind of complicated. The big issue is that the Arty has DDR3 memory but @asic destroyer's design only supports SDRAM (which is what is on the ULX3S).

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6:06 a.m.

The actually stuff he is putting on the ASIC should work fine on both FPGAs in theory

6:06 a.m.

But really you want something like https://fires.im/ -- that makes the FPGA be an ASIC simulation accelerator

FireSim is an open-source (https://github.com/firesim/firesim) FPGA-accelerated full-system hardware simulation platform that makes it easy to validate, profile, and debug RTL hardware implementations at 10s to 100s of MHz. FireSim simplifies co-simulating ASIC RTL with cycle-accurate hardware and software models for other system components (e.g...

6:09 a.m.

@Andrew Wingate - I have a bunch of the high end boards which people use for things like that. But as they are like $20k USD each I'm less happy to put them randomly on the internet for anyone to access.

6:10 a.m.

The NeTV2 and NiteFury cards that @Tisham Dhar (CSIRO EASI) is playing with might be a good option for doing small firesim like stuff with the PCIe connection.

Gotcha, thanks. I correctly assumed they weren't quite sized for the task, but figured I'd ask anyways. Cool to see the toolchain exists!

I mean, the designs you are doing on wafer.space probably are pretty reasonable to fit on the Arty / Netv2 / ULX3S sized FPGAs.

Oh! Amazing!!

I'm guessing the NiteFury II mentioned @ https://docs.fires.im/en/latest/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/RHS-Research-Nitefury-II-FPGAs.html is probably Ultrascale+ based rather than Series 7 like the original Nitefury?

Tim 'mithro' Ansell

I'm guessing the NiteFury II mentioned @ https://docs.fires.im/en/latest/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/RHS-Research-Nitefury-II-FPGAs.html is probably Ultrascale+ based rather than Series 7 like the original Nitefury?

Seems to work with FireSim

Tisham Dhar (CSIRO EASI)

Captured rpi4 working config here : https://github.com/AlphamaxMedia/netv2mvp-scripts/pull/1

Does this indicate the NeTV2 I have is a 100T ? 0x13631093 is the IDCODE for a Xilinx Artix-7 FPGA

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9:19 p.m.

I was going to frame it and hang it on the wall.

Tisham Dhar (CSIRO EASI)

Hard to find : https://github.com/AlphamaxMedia/netv2-mainboard/blob/master/netv2mvp-pvt1.pdf

https://github.com/AlphamaxMedia/netv2-mainboard/blob/master/hdmi_m2m_jumper-v2.PrjPcb#L92 DocumentPath=C:\Program Files (x86)\Altium\Altium Designer grumble :p

netv2-mainboard/hdmi_m2m_jumper-v2.PrjPcb at master · AlphamaxMedi...

Release directory for NeTV2 main PCBA files. Contribute to AlphamaxMedia/netv2-mainboard development by creating an account on GitHub.

carlfk

https://github.com/AlphamaxMedia/netv2-mainboard/blob/master/hdmi_m2m_jumper-v2.PrjPcb#L92 DocumentPath=C:\Program Files (x86)\Altium\Altium Designer grumble :p

@Tim 'mithro' Ansell can probably get sources fully uploaded by Bunny and we can get it all converted to KiCAD and make more , I have found the SQRL Acorn quite affordable due to crypto craze. Just need to reverse engineer and open it.

Tisham Dhar (CSIRO EASI)

Does this indicate the NeTV2 I have is a 100T ? 0x13631093 is the IDCODE for a Xilinx Artix-7 FPGA

According to AI - The JTAG IDCODE 0x13631093 decodes specifically to a Xilinx Artix-7 XC7A100T FPGA. I'm guessing you have one of the special "dev" NeTV2 which had the 100T rather than the 35T part?

Tisham Dhar (CSIRO EASI)

@Tim 'mithro' Ansell can probably get sources fully uploaded by Bunny and we can get it all converted to KiCAD and make more , I have found the SQRL Acorn quite affordable due to crypto craze. Just need to reverse engineer and open it.

I believe KiCAD can open Altium Designer files these days?

carlfk

Click to see attachment 🖼️

We should put it on fpgas.online instead

carlfk

https://github.com/AlphamaxMedia/netv2-mainboard/blob/master/hdmi_m2m_jumper-v2.PrjPcb#L92 DocumentPath=C:\Program Files (x86)\Altium\Altium Designer grumble :p

Where is the jtag header?

@carlfk

10:16 p.m.

We need an RPi hat that attaches a dirty JTAG to those pins, passes through power and Rx TX and may be interrupts , not sure what those do. And also has a PCIe ribbon cable M2 thingie or just an oculink connector at the edge.

10:17 p.m.

But it will be specific to the NETV2

10:17 p.m.

Not sure how many of those are out in the wild.

10:19 p.m.

I suspect the Pci-leech gateware I am loading is for a 35T precompiled and I am loading on a 100T so it is barfing. I have to setup litex and Vivado and all that jazz to compile gateware for the 100T and do a hello world and see.

10:20 p.m.

I wish OpenOCD had the cross-walk to tell me the FPGA type without giving me a hex.

10:20 p.m.

Would a 35T gateware run on a 100T ?

Tisham Dhar (CSIRO EASI)

But it will be specific to the NETV2

what is dirty JTAG ?

https://github.com/dirtyjtag/DirtyJTAG

GitHub - dirtyjtag/DirtyJTAG: JTAG probe firmware

JTAG probe firmware. Contribute to dirtyjtag/DirtyJTAG development by creating an account on GitHub.

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ah - runs on the pico https://github.com/phdussud/pico-dirtyJtag

GitHub - phdussud/pico-dirtyJtag

Contribute to phdussud/pico-dirtyJtag development by creating an account on GitHub.

10:49 p.m.

more on this tomorrow - I need to get to PS1 to tell them we have lots of money. (I'm the treasurer and we have lots of money)

Sketch of the mess to simplify or something. Feel like NeTV2 need a custom pi hat

Rebuilding NeTV2 gateware to target the 100T is hard, a lot of the submodules pointed to here are gone : https://github.com/AlphamaxMedia/netv2-fpga

GitHub - AlphamaxMedia/netv2-fpga: Quickstart for building FPGA cod...

Quickstart for building FPGA code for NeTV2. Contribute to AlphamaxMedia/netv2-fpga development by creating an account on GitHub.

5:29 a.m.

Wonder if I can get a pre-built stock gateware for 100T or get that repo maintained for 2026. Last commit from Bunnie points towards the shifting sands of sourcing toolchains at the bleeding edge

Bunnie's on Discord, in the baochip Discord (his current project -- https://www.crowdsupply.com/baochip/dabao) and a few others. (edited)

6:17 a.m.

I'd guess he still has a checkout of the dependencies, and probably could rebuild it for the 100T variant.

6:19 a.m.

This post from Bunnie has an invite link for the baochip Discord if you're interested -- https://social.treehouse.systems/@bunnie/115716761132172776

bunnie (@bunnie@treehouse.systems)

I'll be presenting some of my latest work on Xous & Baochip with @Xobs at #39C3 on Day two, 11PM room One: fahrplan.events.ccc.de/congres… Hope to see you there! For more on Baochip, checkout bluesky: bsky.app/profile/baochip.com or read the source at github: github.com/baochip/baochip-1x The TL;DR is that Baochip is a "mostly-open" RTL SoC in 22nm TSMC, purpose-built for Xous and expressly packaged for IRIS inspection. It packs in five RISC-V CPU cores (one Vexriscv CPU at 350MHz, and four PicoRV's at 700MHz), 2MiB on-chip SRAM and 4MiB on-chip RRAM (basically FLASH). I'm aiming to have the chip broadly available by early 2026. Right now I have first silicon. You can follow development & ask questions on the Baochip discord at discord.gg/yesbcPF9Xy Sorry, no website yet - I suck at marketing - but hey, at least the source code is up!

Not sure I can ask for things

@bunnie is right here too....

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7:46 a.m.

@Tisham Dhar (CSIRO EASI) - I probably have 35T versions of the NeTV2 too....

@bunnie would it be possible to update the netv-fpga repo compile the gateware fixing the sub module linkage etc.

this is a good question. unfortunately litex has been a moving target and i haven't been able to keep up with it on NeTV

4:10 p.m.

the best bet is...i need to get back from traveling (currently not at home) and then I have to access my archive machine and dig up the virtual machine I used to build the NeTv2 firmwares

4:10 p.m.

i stopped schlepping that around years ago since the project had been pretty dormant and it took like 40 gigs on my hard drive

4:11 p.m.

if i can resurrect the VM it' should have a snapshot of everything as it was back then and may be able to build some things modulo the fact that i've totally forgotten how to use it and hopefully i even remember the password to log into it

4:13 p.m.

might be a few days before i can try this...i'm kind of compressed until chinese new year. how urgent is it to get a 100T firmware

@Tisham Dhar (CSIRO EASI) - It should be pretty trivial to get the latest LitePCIe going on the NeTV2 once you have a working Vivado environment.

I will get the Vivado going , then come back here. Last time AMD site would not let me register and download Vivado.

@Tisham Dhar (CSIRO EASI) - Yeah, know that feeling. It would be nice if f4pga was able to do LitePCIe -- https://github.com/openxc7 might be able to do it -- but I wouldn't start with that.

openXC7

Free and open source FPGA toolchain for AMD/Xilinx Series 7 chips, including Kintex-7. Supports Kintex7 (including 325/420/480t), Artix7, Spartan7 and Zynq7. - openXC7

Overall though it points to a distribution challenge with FPGA / Litex toolchains. I am sure you are working on a solution.

10:20 p.m.

I remember I proposed docker instead of VM's long time ago, but at that time they were not hardware exposure friendly and images would be too big. Which is what we are trying to solve with FPGAs online, instead of distribution of toolchains we can let users come to a pre-installed stack.

10:21 p.m.

Which for context is what I do in my day job, maintain science coding environments for astronomers and earth observation people.

@Tisham Dhar (CSIRO EASI) - https://bit.ly/edda-conda-eda-spec

EDDA - Conda based system for FPGA and ASIC Dev

EDDA - "Conda for EDA tools"Conda based system for FPGA and ASIC Dev bit.ly/edda-conda-eda-spec Packaging status can be found at j.mp/edda-status Tasks Split apart the litex-hub/litex-conda-packages repository into compilers, eda, etc. Defork litex-hub/litex-conda-packages, SymbiFlow/conda-pac...

11:10 p.m.

@Tisham Dhar (CSIRO EASI) - https://docs.google.com/document/d/10_MqFjTIYVVuOJlusJydsp4KOcmrrHk03__7ME5thOI/edit?tab=t.0

Open Source EDA: building, packaging, installing

PARENT: http://bit.ly/unai-eda-megadoc Building, packaging and installingOpen Source EDA toolingfor mixed HDL designs Packaging + Distribution Systems 1 Overall Goals 2 Distribution: Canonical package managers (apk, apt, dnf, pacman, etc.) 2 Alpine Linux 3 Android 3 Arch Linux 3 Debian/Ubunt...

11:11 p.m.

@Tisham Dhar (CSIRO EASI) - https://docs.google.com/document/d/1fWV259IbgnenwjRswE9dqCMBfyg8NC2Ily3pGQcw5ck/edit?tab=t.0#heading=h.pocyih7al6a4

SymbiFlow, LiteX & TimVideos Conda Packages

SymbiFlow, LiteX & TimVideos Conda Packages High priority items Cross platform support - IE adding Windows and Mac Cross device support - IE adding non-x86 Linux like Raspberry Pi Improving the documentation Improving the CI and build process Turning conda environment files into a single install ...

11:12 p.m.

I think packaging and distribution is still one of the unsolved problems in computer science

11:12 p.m.

https://github.com/YosysHQ/oss-cad-suite-build

GitHub - YosysHQ/oss-cad-suite-build: Multi-platform nightly builds...

Multi-platform nightly builds of open source digital design and verification tools - YosysHQ/oss-cad-suite-build

@Tisham Dhar (CSIRO EASI) - I just randomly found a PicoEVB in one of my boxes - https://www.crowdsupply.com/rhs-research/picoevb

PicoEVB

The Xilinx Artix dev kits that fit in your laptop. A convenient, affordable way to explore Xilinx PCIe IP.

Why does it have so many ufl ?

6:24 a.m.

I have been trawling Ali and found these : https://a.aliexpress.com/_mrgWC0h

6:24 a.m.

https://a.aliexpress.com/_m0qC88D

I don't think you want an ECP3 board

Tisham Dhar (CSIRO EASI)

Sketch of the mess to simplify or something. Feel like NeTV2 need a custom pi hat

https://kicanvas.org/?repo=https%3A%2F%2Fgithub.com%2FCarlFK%2Fpj%2Fblob%2Fmain%2Fproject%2Fpj.kicad_pro

6:40 a.m.

I suspect I can hack my design to do what you sketched

6:40 a.m.

https://github.com/CarlFK/pj

GitHub - CarlFK/pj: Pi JTAG hat

Pi JTAG hat. Contribute to CarlFK/pj development by creating an account on GitHub.

The Xilinix one is interesting, it is for cheating at games

6:47 a.m.

https://www.reddit.com/r/FPGA/comments/1im47cm/are_the_captain_dma_75t_boards_only_for_cheating/

From the FPGA community on Reddit

Explore this post and more from the FPGA community

bunnie

might be a few days before i can try this...i'm kind of compressed until chinese new year. how urgent is it to get a 100T firmware

Not in a rush if the netv-fpga repo is updated such that it points to the right submodules I can take it from there. Hopefully that doesn't require dusting off your Vivado VM.

Tisham Dhar (CSIRO EASI)

I will get the Vivado going , then come back here. Last time AMD site would not let me register and download Vivado.

I can't even register and get it now. I think they might just be blocking everything now....

Tisham Dhar (CSIRO EASI)

Not in a rush if the netv-fpga repo is updated such that it points to the right submodules I can take it from there. Hopefully that doesn't require dusting off your Vivado VM.

I think what happened is Litex restructured its repos in a fundamental way so the submodules are dangling due to that. what I might be able to do is just vendor in a copy of the stuff "detaching" it from the history, since it sort of doesn't matter because they broke the chain of commits by restructuring the repo

11:06 a.m.

like i think they actually deleted some repos and paths so there's nothing to even refer to

Repo rot and Tool chain rot

@carlfk - Did we ever explore things like this -> https://52pi.com/collections/sales/products/52pi-19-inch-2u-rack-mount-for-raspberry-pi5-4b-with-10-pcie-nvme-expansion-board-supports-m-2-nvme-ssds ?

52Pi 19 Inch 2U Rack Mount for Raspberry Pi5 with 10 PCIE NVME Expa...

Good news! This product can be shipped from the US overseas warehouse, and the shipping fee for US orders will be reduced. If you have any questions, please contact us. [Description] The 2U Raspberry Pi Rack is a versatile and efficient solution for housing up to ten Raspberry Pi units, compatible with the Raspberry Pi

11:09 p.m.

@Tisham Dhar (CSIRO EASI) - Was this the board you were showing me? https://52pi.com/collections/sales/products/deskpi-super6c-raspberry-pi-cm4-cluster-mini-itx-board-kit-6-rpi-cm4-supported ?

DeskPi Super6C Raspberry Pi CM4 Cluster Mini-ITX board Kit 6 RPI CM...

Good news! This product can be shipped from the US overseas warehouse, and the shipping fee for US orders will be reduced. If you have any questions, please contact us. [Description] DeskPi Super6C is the Raspberry Pi cluster board a standard size mini-ITX board to be put in a case with up to 6 RPI CM4 Compute Modules.

11:10 p.m.

They also have https://52pi.com/collections/sales/products/rs01-1u-rack-mount-for-raspberry-pi5-4b-with-four-rs-p11-expansion-board-for-rs-p22-raspberry-pi5

RS01 1U Rack Mount for Raspberry Pi5 with four RS-P11 Expansion Boa...

Good news! This product can be shipped from the US overseas warehouse, and the shipping fee for US orders will be reduced. If you have any questions, please contact us. Description The new Raspberry Pi Expansion Board RS-P11 for RS-P22 RPi5 is designed to enhance the functionality of your Raspberry Pi devices with addi

No, I have a Turing Pi, same idea, shared power and ethernet backplane and custom BMC

11:12 p.m.

https://turingpi.com/product/turing-pi-2-5/

Paula Nsky

Get Turing Pi 2, mini ITX cluster board

The Turing Pi 2.5 is a 4-node mini ITX cluster board with a built-in Ethernet switch that runs Turing RK1, Raspberry Pi CM4 or Nvidia Jetson compute modules

11:14 p.m.

Either way the M2 is great for adding our FPGA's on

11:15 p.m.

I have ordered one of the game hacking 75T's with preloaded firmware (Pci-leech) , will see if it shows up on lspci off the bat.

@Tisham Dhar (CSIRO EASI) - I was pondering https://www.amazon.com/erounder-Raspberry-Female-Computer-Accessories/dp/B08H26LY71/ref=sr_1_51

S erounder 5Pcs GPIO Ribbon Cable for Male to Female 40pin Breadboa...

Specification: Item Type: GPIO cable Length: Approx. 20cm / 7.9in Application: For Features: 40pin Package List: 5 x GPIO Cable

Hmm they are not super useful since Pi-5 GPIO drive for FPGA access is stunted we are better served with cheap dirtyJTAG's, they will be useful for stacking pi4's and more flexible layout, but without the PCI-e , do we really want pi-4's.

@everyone

Tim 'mithro' Ansell

@carlfk - Did we ever explore things like this -> https://52pi.com/collections/sales/products/52pi-19-inch-2u-rack-mount-for-raspberry-pi5-4b-with-10-pcie-nvme-expansion-board-supports-m-2-nvme-ssds ?

no - but I don't think it helps, and might be worse than the current thing

12:34 a.m.

the FPGA board and camera need to be mounted somewhere - adding onto that pi holder seems harder than the little bundle of pi+camera+fpga board

12:36 a.m.

never mind harder - routing the usb and eathernet is impracticable - they would have to go over the top, and the dongle cables aren't long enough

Now I am down the game hacking with FPGA rabbit hole and the whole ecosystem there : https://captaindma.com/product/captain-dma-100t-7th/

Tomok

Captain DMA 100T-7th(Buy DMA, get Makcu) - Captain DMA

Experience the pinnacle of DMA technology with Captain DMA 7th. Unleash blazing-fast data transfer rates, enjoy customized firmware options

1:08 a.m.

Should release the NeTV2 to that crowd

(just dropping a note here that someone should @bunnie me if i don't get back to this thread by middle/late next week, my head's L1 cache is full so this might get written to swap shortly and I'll need a tickle to bring this back into my working set)

2

So turns out I have to be outside the CSIRO network to download Vivado from AMD, I have it downloaded installed and now synthing 100T bitstream, turns out the pre-built one I was loading was indeed for 35T and failed to launch. OpenOCD performed the board-scan and did not stop me from loading the wrong bitstream

2:11 p.m.

Receipts : Vivado% source vivado_build.tcl -notrace ------------------------------------------------------- STARTING SYNTHESIS STEP. ------------------------------------------------------- INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'pcie_7x_0'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'bram_pcie_cfgspace'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_66_66'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_41_41_clk2_tlptapcfgspace'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_55_55_clk2_tlptapcfgspace'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_68_34'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_32_32_clk2'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_64_64'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_64_64_clk1_fifocmd'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_34_34'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_256_32_clk2_comtx'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_32_32_clk1_comtx'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_64_64_clk2_comrx'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz'... INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz'...

2:12 p.m.

There are warnings like this, which I assume are a bad thing, will see if synth results work : INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/xilinix/2025.2/data/ip'. WARNING: [IP_Flow 19-2162] IP 'bram_pcie_cfgspace' is locked:

IP definition 'Block Memory Generator (8.4)' for IP 'bram_pcie_cfgspace' (customized with software release 2020.2) has a different revision in the IP Catalog. * Current project part 'xc7a100tfgg484-2' and the part 'xc7a35tfgg484-2' used to customize the IP 'bram_pcie_cfgspace' do not match.

WARNING: [IP_Flow 19-2162] IP 'fifo_41_41_clk2_tlptapcfgspace' is locked:

IP definition 'FIFO Generator (13.2)' for IP 'fifo_41_41_clk2_tlptapcfgspace' (customized with software release 2020.2) has a different revision in the IP Catalog. * Current project part 'xc7a100tfgg484-2' and the part 'xc7a35tfgg484-2' used to customize the IP 'fifo_41_41_clk2_tlptapcfgspace' do not match.

WARNING: [IP_Flow 19-2162] IP 'fifo_55_55_clk2_tlptapcfgspace' is locked:

AND DONE !! k8s@node10:~ $ lspci 0001:00:00.0 PCI bridge: Broadcom Inc. and subsidiaries BCM2712 PCIe Bridge (rev 21) 0001:01:00.0 Ethernet controller: Xilinx Corporation Device 0666 (rev 02)<- Devil Device ? 0002:00:00.0 PCI bridge: Broadcom Inc. and subsidiaries BCM2712 PCIe Bridge (rev 21) 0002:01:00.0 Ethernet controller: Raspberry Pi Ltd RP1 PCIe 2.0 South Bridge

2:31 p.m.

Time to give it a crack with litepcie

@Tisham Dhar (CSIRO EASI) - Great progress!

This weekend I am playing with the Blackhole from Tenstorrent and recovering from the heat and COVID. Remind me next weekend where the goal posts are.

How is the BlackHole connected to your computers?

PCIe over thunderbolt

I have discovered and used this file with installed Litex toolchain. I am going to try the synthesised bitstream and see what I get : https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/kosagi_netv2.py it also produces a driver. Need to read up on what it exactly does in the kernel. Because JTAG loader and synthesis toolchains are on different machines , I have to create a bin file and copy it over. I will also add the working 100T pci-leech bin file to the wiki where I got the pre-built 35T one from. Stuck on my tenstorrent card , so I have dropped that from my working set while I rustle up some help (edited)

litex-boards/litex_boards/targets/kosagi_netv2.py at master · lite...

LiteX boards files. Contribute to litex-hub/litex-boards development by creating an account on GitHub.

@Tim 'mithro' Ansell @bunnie you can leave off the VM dusting Litex has kept the NeTV2 support maintained, at least upto 2 years ago and I can build from their end with this command python3 -m litex_boards.targets.kosagi_netv2 --build --with-pcie --variant a7-100 --with-ethernet --driver --with-sdcard

1

5:50 a.m.

Bitstream when loaded shows up with this Xilinix device on PCI-e Bus of Raspberry pi 5: 0001:00:00.0 PCI bridge: Broadcom Inc. and subsidiaries BCM2712 PCIe Bridge (rev 21) 0001:01:00.0 Memory controller: Xilinx Corporation Device 7024 0002:00:00.0 PCI bridge: Broadcom Inc. and subsidiaries BCM2712 PCIe Bridge (rev 21) 0002:01:00.0 Ethernet controller: Raspberry Pi Ltd RP1 PCIe 2.0 South Bridge (edited)

oh wow. what? I had no idea that Litex was maintaining a port. That's pretty awesome.

1

6:00 a.m.

Thank you florent

@carlfk - So I have the tweed gateway box plugged in now and can access it's BMC. The only problem is that I currently have a single IPv4 IP address.

@carlfk - Looks like I can connect to the machine using the IPv6 address

@carlfk - I was hoping to get tweed up and running but I ended up fighting with vlans and stuff

it might be a good time to rebuild the box - there is a new version of Debian and RaspiOS and figure out how to support more than just Arty which I think is all the ansible stuff sets up

@carlfk - How are the two sites handled again?

both dns point to the same IP, nginx did a reditect

I got a one of the DMA game hacking cards off Amazon (a 75T) it comes with a built in CH347 UART + JTAG interface. So can upload things to it via newer openOCD , did upload Pci-leech and that works. Will see if I can register it as a board under Litex and make it do something. Next weekend will document the NeTV2 status in Litex Wiki. CH347 seems to be the easiest / cheapest UART + JTAG in the current setup. Dirty JTAG's work too I guess. I have some Raspi's Pico's floating around looking for a purpose in life.

@Tisham Dhar (CSIRO EASI) - Do you have a link to the DMA game hacking cards?

8:34 p.m.

I also have a box of about 30 x CH347 UARTs here.

Tim 'mithro' Ansell

@Tisham Dhar (CSIRO EASI) - Do you have a link to the DMA game hacking cards?

guessing https://captaindma.com/product/captain-dma-75t/

Tomok

Captain DMA 75T-6th(Buy DMA, get Makcu) - Captain DMA

Experience the pinnacle of DMA technology with Captain DMA 4th. Unleash blazing-fast data transfer rates, enjoy customized firmware options

1

I bought an unbranded hardware on Amazon

9:01 p.m.

https://www.amazon.com.au/Synpinya-Blender-High-Performance-Direct-Memory/dp/B0FQJ92MX1/

Synpinya DMA Borad 75t for Kmbox Video Blender High-Performance DMA...

Synpinya DMA Borad 75t for Kmbox Video Blender High-Performance DMA Card Direct Memory Access

9:02 p.m.

Available on AliExpress as well

Tim 'mithro' Ansell

I also have a box of about 30 x CH347 UARTs here.

I will take a few and develop a recipe with Raspberry Pi 5 and NeTV2 then you can use that stack to wire up all the boards.

carlfk

guessing https://captaindma.com/product/captain-dma-75t/

No DDR memory on that board?

9:16 p.m.

Guess if you have a decent PCIe link going, you can just use the host's memory....

It is a super simple card ch347, FPGA, spi flash and ftdi for output if things back to host. It captures game frames and does stuff automatically (target lock for FPS(.

Tim 'mithro' Ansell

No DDR memory on that board?

For what they're meant for x4 is already pretty good

9:56 p.m.

Though I think they generally use USB / Eth to exfiltrate the data

9:57 p.m.

Anticheats will prematurely blacklist drivers and prevent the pages from getting mmio mapped if it looks off (edited)

@carlfk - Did you end up writing up instructions on how to use the stuff in the Pici supplies to mount RPis?

4:13 a.m.

I think I should be using these

Tim 'mithro' Ansell

@carlfk - Did you end up writing up instructions on how to use the stuff in the Pici supplies to mount RPis?

https://github.com/CarlFK/pici/wiki/Card-Assembly-Procedure

Card Assembly Procedure

Contribute to CarlFK/pici development by creating an account on GitHub.

5:00 p.m.

that bag of holes is "secure with 4 donuts"

5:03 p.m.

There should be 4 assembled ... cards? sets? bundles.

5:04 p.m.

get those on line, and figue out if you want to add more Arty or add new stuf like NeTV2 or fomu

also: Pi5 will need a heat sink and fan - the cpu based video encoding heats it up enough to trip some shutdown thing

@carlfk - Thanks past Carl for writing that up!

Tim 'mithro' Ansell

@carlfk - Thanks past Carl for writing that up!

well... I'm curious if someone can make sense of it.

4:33 a.m.

it's good once you have done it a few times and can't remember what order to do things in

@carlfk - I think I've almost got tweed reconfigured, going to get you a pull request with the changes needed

1

I'm just circling back to this thread - it looks like the NeTV2 bitrot issue was resolved, so I don't need to dust off the old VM and try to figure that out any more, correct?

bunnie

I'm just circling back to this thread - it looks like the NeTV2 bitrot issue was resolved, so I don't need to dust off the old VM and try to figure that out any more, correct?

Yep Litex works fine and you can make a post somewhere to that effect. I will be testing the 35T this week.

1

11:50 a.m.

This CH347 in mode 3 does UART + jtag

I'll try to catch up on some PRs etc on the repo then, thanks for working through this!

@Tim 'mithro' Ansell you changed "hardcoded 10.21.0.1" which looks like it should work fine, but I am wondering why?

@carlfk - The AI decided it wanted to

that makes things harder to keep track of, so no.

11:40 p.m.

please don't make me spend time on AI stuff you have't scrutinized

1

Tim 'mithro' Ansell

@carlfk - The AI decided it wanted to

I hate to ask.. and it bothers me that we are having this conversation - is any of your PR needed?

carlfk

I hate to ask.. and it bothers me that we are having this conversation - is any of your PR needed?

The description seems reasonable to me: cmdline.txt and fstab had hardcoded 10.21.0.1 NFS server IPs. Convert to Jinja2 templates using {{ eth_local_address }} and {{ nfs_root }} so they work across sites with different IPs (e.g. welland at 10.31.0.3, PS1 at 10.21.0.1). The IP address range 10.31.X.X is what I'm using for the fpgas.online in my network.

@carlfk - Can you ssh -6 root@tweed.welland.mithis.com ?

Tim 'mithro' Ansell

@carlfk - Can you ssh -6 root@tweed.welland.mithis.com ?

ssh: connect to host tweed.welland.mithis.com port 22: Network is unreachable

10:05 p.m.

carl@x1:~$ host tweed.welland.mithis.com tweed.welland.mithis.com has address 87.121.95.37 tweed.welland.mithis.com has IPv6 address 2404:e80:a137:3100::2

@carlfk - Did you use the -6 ?

yup

@carlfk - Can you ping6 that address then?

carl@x1:~$ ping6 2404:e80:a137:3100::2 ping6: connect: Network is unreachable

@carlfk - Can you try a ping6 www.google.com ?

I have no idea and I would be surprised if I have v6 here on my home lan

10:07 p.m.

carl@x1:~$ ping6 www.google.com ping6: connect: Network is unreachable

10:07 p.m.

my router is long overdue for an overhaul - maybe this is the bump I need to do something

Does PS1 have IPv6 setup?

I think so. cchecking...