wafer.space Community

I am interested in designing a metering ASIC for energy. Design block suggestions and toolchains welcome. Looking to use Tiny Tapeout or Wafer Space given space required. (edited)

world's least optimized pixel array

BreakingTaps

world's least optimized pixel array

Are you doing photoelectronics for Run2/3?

11:27 p.m.

(also that's why back illumination and what microlenses are for)

If I can get a bit more of it done in the next week or two, yep! Would love to tape this out for Run2. it's an "event pixel" design, where each pixel fires asynchronously when its threshold is breached. They register changes in a scene rather than a clocked frame

BreakingTaps

If I can get a bit more of it done in the next week or two, yep! Would love to tape this out for Run2. it's an "event pixel" design, where each pixel fires asynchronously when its threshold is breached. They register changes in a scene rather than a clocked frame

ahhhhh. I was about to say, at that lack of density, might almost go for SPAD (but the DRCs likely prevent the necessary field-smoothing rounding).

I should be able to get density higher, ALIGN freaked out once I added the photodiode into the circuit. Either needs some tweaks, or just pull the diode out and hand-place them. but otoh 32x32 is plenty for demonstration and it'll probably make the rest of the project easier so

‍♂️

(edited)

1:33 a.m.

SPADs would be neat though!

1:34 a.m.

think I saw a paper somewhere with a SPAD done in skywater 130? or maybe even GF 180? will try to find it

I'm just a little sad that silicon's indirect bandgap means you can't just use a photodiode for bidirectional communications like you can with e.g. a 405nm-pumped COTS blue LED (load modulation in photovoltaic biasing severely varies how much shunt current in the diode produces electroluminescence; this is fairly easy to separate at the end with the 405nm source and can be used as a back-channel there). Unless you happen to know some clever trick that'd allow one to do vertical surface emitting data back channel from on top of a gf180mcuD die to some "beefier" system. I mean I guess tbf things like osram/ams's PLPVYL1 940A_E 20~60ct/each (depending on quantity) VCSEL do exist... (wish there was a SPICE for it, or even just capacitance information, but oh well....)

2:41 a.m.

ohhh, it even hits nicely into peak Si photodiode A/W efficiency.... (edited)

could abuse resistive elements or even just big gates and emit IR

I think porous silicon can be used to make an LED without any other materials, but it's a pretty crapp LED iirc (and far red)

BreakingTaps

could abuse resistive elements or even just big gates and emit IR

I think porous silicon can be used to make an LED without any other materials, but it's a pretty crapp LED iirc (and far red)

tho apparently you can just buy VCSEL for so cheap if you buy ones marketed to lower power IR illumination; I should get one next time and try to measure capacitance.

AnalogCoder: Analog Circuit Design via Training-Free Code Generation https://arxiv.org/pdf/2405.14918 LADAC: Large Language Model-driven Auto-Designer for Analog Circuits https://www.techrxiv.org/doi/full/10.36227/techrxiv.170473941.10097233/v1 Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System https://par.nsf.gov/servlets/purl/10356326

8:09 p.m.

@BreakingTaps ^

8:09 p.m.

ever come across them?

I've seen MAGICAL before! MAGICAL and ALIGN were both funded by the same DARPA program and were sort of sibling projects. After looking over them, it seemed that MAGICAL is abandoned/not-very-active and looked harder to extend to other PDKs (the paper or project had a note about how it was difficult to port). Dunno about the other two, will take a look!

BreakingTaps

could abuse resistive elements or even just big gates and emit IR

I think porous silicon can be used to make an LED without any other materials, but it's a pretty crapp LED iirc (and far red)

Stupid idea, but could the metal layers be used as reflectors and/or diffraction gratings/etc ?

sure, kinda static tho

6:48 p.m.

and I at least don't know how good the absolute scale tolerance of the litho is

Tim 'mithro' Ansell

Stupid idea, but could the metal layers be used as reflectors and/or diffraction gratings/etc ?

I was actually looking into using the metal lines as gratings / structural color recently. Unfortunately the min pitch is pretty large. M1 could get you some mid-visible color, but M2+ is all pretty far red.

I wonder if you could throw a resistive element under a metal reflector layer and use the thermal expansion though? be sort of like a deformable mirror but fully monolithic

BreakingTaps

I was actually looking into using the metal lines as gratings / structural color recently. Unfortunately the min pitch is pretty large. M1 could get you some mid-visible color, but M2+ is all pretty far red.

I wonder if you could throw a resistive element under a metal reflector layer and use the thermal expansion though? be sort of like a deformable mirror but fully monolithic

Just don't do what tholin seems to have accidentally done (crack dies after first power cycle)

1

namibj

Just don't do what tholin seems to have accidentally done (crack dies after first power cycle)

That is why you get 1,000 of them

BreakingTaps

I was actually looking into using the metal lines as gratings / structural color recently. Unfortunately the min pitch is pretty large. M1 could get you some mid-visible color, but M2+ is all pretty far red.

I wonder if you could throw a resistive element under a metal reflector layer and use the thermal expansion though? be sort of like a deformable mirror but fully monolithic

Could you use some type of pattern between the layers or something?

I'd guess the silicon could be modulated in transparency via presence of minority carriers, for some wavelength at least?

quite possibly! afraid that's approaching the end of my photonics knowledge. probably easy enough to simulate though (edited)

BreakingTaps

quite possibly! afraid that's approaching the end of my photonics knowledge. probably easy enough to simulate though (edited)

The simulation itself might be an interesting video?

ahhh yeah internet says Free-Carrier Plasma Dispersion Effect

7:24 p.m.

modulate refractive index usable on 1310/1550 nm light in silicon photonics waveguides.

7:25 p.m.

just have a pn/pin junction and either reverse bias the former to desired width of depletion zone or forward bias the latter to desired minority carrier density

as silicon should be pretty transparent there normally, it might work having it be in the resonator and to use it to minutely shift the resonance peak to doa little FM modulation

BreakingTaps

I was actually looking into using the metal lines as gratings / structural color recently. Unfortunately the min pitch is pretty large. M1 could get you some mid-visible color, but M2+ is all pretty far red.

I wonder if you could throw a resistive element under a metal reflector layer and use the thermal expansion though? be sort of like a deformable mirror but fully monolithic

heh ran some numbers on this, very roughly you could get 5-10nm of vertical displacement so 10-20nm of reflected displacement. Not nothing!

consider comparing to carrier density effects in vertical transmission perhaps for the iirc fairly accessible 1310nm

BreakingTaps

I was actually looking into using the metal lines as gratings / structural color recently. Unfortunately the min pitch is pretty large. M1 could get you some mid-visible color, but M2+ is all pretty far red.

I wonder if you could throw a resistive element under a metal reflector layer and use the thermal expansion though? be sort of like a deformable mirror but fully monolithic

or use multiple metal layers with offsets?

Muuuuch better!

12:04 p.m.

And can still drive a 1K load

12:05 p.m.

Yes, I could still make it use less current by optimizing it to drive smaller loads, but this is a nice tradeoff

12:05 p.m.

My next chip is only going to have 2 of these anyways

@Tholin - Invest in power gating anyway

1

Welp, defeated by DRC again

working on a 1T pixel design based off of this paper (https://www.mdpi.com/1424-8220/9/1/131). Needs a floating P body which I figured you could build with DNWell -> LVPWell -> NPlus. Got everything dialed into minimum size that would make DRC happy, then arrayed it and discovered another DRC rule: LVPWell to LVPWell must be >1.4um. There goes my pixel density!

Should still work, but I was hoping for <2-3um pitch so I could play with sub-diffraction limit oversampling stuff. But with that DRC limitation might as well make the active area larger and run it as a normal detector. (edited)

10:07 p.m.

better screenshot (edited)

BreakingTaps

Welp, defeated by DRC again

working on a 1T pixel design based off of this paper (https://www.mdpi.com/1424-8220/9/1/131). Needs a floating P body which I figured you could build with DNWell -> LVPWell -> NPlus. Got everything dialed into minimum size that would make DRC happy, then arrayed it and discovered another DRC rule: LVPWell to LVPWell must be >1.4um. There goes my pixel density!

Should still work, but I was hoping for <2-3um pitch so I could play with sub-diffraction limit oversampling stuff. But with that DRC limitation might as well make the active area larger and run it as a normal detector. (edited)

Can't you use pmos devices instead and not need the dnwell? Also I still don't quite get where and how STI is litho'd. Like, what patterns/shapes even do that? Also, https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_04.html says:

Equi potential min space 0.86V

1:56 a.m.

Also maybe look at https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_10_07.html it feels like you may be doing things similar to those restrictions depending on biasing conditions?

1

Hmm I'll need to double check, but I don't think a normal pmos device would give the floating p-body that's needed. It'd be an nwell in the psub, and then p+ contacts

2:52 p.m.

need to look into that equipotential thing, not sure how it's calculated. Would be great to use that spacing! I think because all the floating p-body sections are isolated, they are considered at different potentials by the DRC? not sure

BreakingTaps

Hmm I'll need to double check, but I don't think a normal pmos device would give the floating p-body that's needed. It'd be an nwell in the psub, and then p+ contacts

No I mean like, the photodiode works regardless of whether it's illuminated from the P-side or the N-side, right? Voltages flip, sure, but I'd not think you'd need particularly high performance transistor channels in those pixels so that's not on it's own at least reason to go for N-channel device.

BreakingTaps

need to look into that equipotential thing, not sure how it's calculated. Would be great to use that spacing! I think because all the floating p-body sections are isolated, they are considered at different potentials by the DRC? not sure

Well I'm pretty sure it's (only) a latchup concern; I'd guess this might cause charge-spillover to adjacent cells similar in visual effect to what we remember from old CCD digital cameras. Xyce has 2D TCAD on hand you could use to model the latchup behavior. I guess the biggest hurdle would be that it's potentially gonna blow the 4-electrode limit in their code.

1

Ah I misunderstood. Yes, N or P is fine, although P is preferred because hole accumulation is (apparently) better for imaging. less noisy I think? But the main thing is that it needs a floating/isolated body of the diode. Light passes through the poly gate, creates electron/hole pairs, the electrons are swept away to drain and the holes remain which then alters the IV curve of the transistor when it is read out. That's how they get a "3T" pixel with one transistor, it acts as integration, readout and reset all in one. But needs the floating/isolated body to do it

1 source, 2 gate, 3 drain, 4 substrate, (maybe 5 next_drain), 5 next_gate, 6 next_source

namibj

Well I'm pretty sure it's (only) a latchup concern; I'd guess this might cause charge-spillover to adjacent cells similar in visual effect to what we remember from old CCD digital cameras. Xyce has 2D TCAD on hand you could use to model the latchup behavior. I guess the biggest hurdle would be that it's potentially gonna blow the 4-electrode limit in their code.

I was a little confused why it was codified in DRC, it seems like a functional problem but not really a design rule / layout issue

One should notice that in readout mode, some stored holes are displaced under the source due to shrink of charge storage region under the gate and source potential lowering. This shift of the charge storage region to the source and toward the pixel edge should be stopped to avoid electrical crosstalk. One solution to the problem is to employ STI (shallow trench isolation), as shown in Figure 2. It was adopted in our first design configuration.

Yeah I for one don't quite get where the electrodes are in Fig.2

Have you considered asking those researchers?

BreakingTaps

I was a little confused why it was codified in DRC, it seems like a functional problem but not really a design rule / layout issue

Me when I look at one too many sky130 DRC's again and go huh....

1

3:59 p.m.

[insert villager sound effect]

might give them a ping! can't hurt

worst case they don't answer

4:00 p.m.

well, worst worst case they snipe your slot on Run2

BreakingTaps

I was a little confused why it was codified in DRC, it seems like a functional problem but not really a design rule / layout issue

At work we definitely have some DRs that are just for electrical "dummyproofing", and since my team draws mechanical and litho designs, we often get waivers for some of those rules

12:08 a.m.

However we also can ask the process integration owners and ask questions like "how does the STI actually get patterned" if we're confused or just curious

BreakingTaps

better screenshot (edited)

I need that GDS3D isometric view

12:09 a.m.

After 5 years drawing OASIS/GDS... I still get confused over all these layers on top of layers

nmz787

I need that GDS3D isometric view

same sadly KLayout PDK only has that for sky130A (and maybe ihp I don't know), not gf180mcuD

It's easy (ish) to make a layerstack

12:12 a.m.

I should really publish my layerstack generator helper... basically just a CLI that takes the list of layers, already arranged in order in a text file, and asks you what Z and how thick you want it... And accumulates your overall height to the next Z default entry (in case you have two layers at the same Z, like the diffusions)

12:13 a.m.

Although I'm sure pointing AI at the existing gds3d layerstacks as examples and asking it to generate the helper I just said, would do it in one or two prompts

12:14 a.m.

I believe I already have a gf180 prop file for gds3d, but am not on my PC right now

nmz787

Although I'm sure pointing AI at the existing gds3d layerstacks as examples and asking it to generate the helper I just said, would do it in one or two prompts

feed it the https://gf180mcu-pdk.readthedocs.io/en/latest/analog/layout/inter_specs/inter_specs_3_30.html and https://gf180mcu-pdk.readthedocs.io/en/latest/analog/layout/inter_specs/inter_specs_3_30.html

namibj

feed it the https://gf180mcu-pdk.readthedocs.io/en/latest/analog/layout/inter_specs/inter_specs_3_30.html and https://gf180mcu-pdk.readthedocs.io/en/latest/analog/layout/inter_specs/inter_specs_3_30.html

Need the dl;dt too, I think there's a layermap for klayout that I'd start with, but those images would be good to finish the details!

nmz787

Need the dl;dt too, I think there's a layermap for klayout that I'd start with, but those images would be good to finish the details!

Sure

https://discord.com/channels/1009193568256135208/1015911926053740544/1508755468275814470

9:47 a.m.

TT will be running an experimental slot in run2 for analog designs. See above for details.

namibj

feed it the https://gf180mcu-pdk.readthedocs.io/en/latest/analog/layout/inter_specs/inter_specs_3_30.html and https://gf180mcu-pdk.readthedocs.io/en/latest/analog/layout/inter_specs/inter_specs_3_30.html

KLayout has some type of cross-sectioning mode - https://klayoutmatthias.github.io/xsection/

XSection Project Home Page

Former xsection@klayout project

https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_10_05.html I think I'm doing everything right, taking a nmos_06v6_nvt PCell that I confirm next to the DUT extracts just fine through magic, and deleting just the dualgate layer rectangle on the DUT copy of the (all flattened) PCell structure, but magic doesn't spell complaints and the DUT just won't spawn in the extracted SPICE? I also have a tiny nmos_03v3 and I just confirmed that deleting also the NAT box on the DUT makes it extract as the plain nmos_03v3 it's then expected to extract as. Do we or do we not have those available at the GDS level? I can understand (with much unhappyness) if there's no design support (LVS, other extraction, spice, xschem, etc.), but otherwise I'd quite very like to know where I would have been supposed to read about us explicitly not having nmos_03v3_nvt.

namibj

https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_10_05.html I think I'm doing everything right, taking a nmos_06v6_nvt PCell that I confirm next to the DUT extracts just fine through magic, and deleting just the dualgate layer rectangle on the DUT copy of the (all flattened) PCell structure, but magic doesn't spell complaints and the DUT just won't spawn in the extracted SPICE? I also have a tiny nmos_03v3 and I just confirmed that deleting also the NAT box on the DUT makes it extract as the plain nmos_03v3 it's then expected to extract as. Do we or do we not have those available at the GDS level? I can understand (with much unhappyness) if there's no design support (LVS, other extraction, spice, xschem, etc.), but otherwise I'd quite very like to know where I would have been supposed to read about us explicitly not having nmos_03v3_nvt.

Maybe grep _nvt $PDK_ROOT/gf180mcu/libs.tech/ngspice/*

I guess you can tape one out and measure it and see if it actually works.

tnt

I guess you can tape one out and measure it and see if it actually works.

That's my fallback.

tnt

I guess you can tape one out and measure it and see if it actually works.

I believe the GDSFactory people are hoping to do some test circuits to do some verification circuits.

@Thomas Pluck 2.1 nfet_03v3_nvt misses models and currently even extraction; it's only implied from some DRCs to exist. Etest if any of that happens would be awesome to capture.

namibj

@Thomas Pluck 2.1 nfet_03v3_nvt misses models and currently even extraction; it's only implied from some DRCs to exist. Etest if any of that happens would be awesome to capture.

Oh and if anyone etests that one, don't only do L=1.8, go down towards the L=0.28.

Leo Moser (mole99) started a thread. 2026-05-27 2:32 p.m.

Tim 'mithro' Ansell

I believe the GDSFactory people are hoping to do some test circuits to do some verification circuits.

Plan was that we can generate test structures on a left over Run 2 half slot right? (edited)

4:17 p.m.

No sense wasting a creative TT slot on device characterization.

Thomas Pluck 2.1

Plan was that we can generate test structures on a left over Run 2 half slot right? (edited)

Correct!

@BreakingTaps - You might find https://docs.google.com/presentation/d/e/2PACX-1vS2jJzvahcR7M6YPl6omPSDk7ZW6sFhqpsh4mxRzwc5JhHkUPudI62qpevA1WWu2g/pub?start=false&loop=false&delayms=3000 interesting. (edited)

[Chipathon 2026 4th Weekly - 29 May 2026] - Track D.pptx

IEEE-SSCS Chipathon 2026 Track D: AI/LLM-assisted circuits gLayout Design Walkthrough Presented by: Anhang Li (anhangli@umich.edu) Track Leads: Mehdi Saligane, Saptarshi Ghosh, Osama Khan, Trio Adiono/Nur, Mauricio Montanares, Muhammed Luqman Jukaku, Luighi Viton 1

Tim 'mithro' Ansell

@BreakingTaps - You might find https://docs.google.com/presentation/d/e/2PACX-1vS2jJzvahcR7M6YPl6omPSDk7ZW6sFhqpsh4mxRzwc5JhHkUPudI62qpevA1WWu2g/pub?start=false&loop=false&delayms=3000 interesting. (edited)

That's a private repo

Andrew Wingate

That's a private repo

I think that fixes it?

Tim 'mithro' Ansell

I think that fixes it?

Yes, fixed

ooh neat, thanks for the ping!

Oh yes thanks for the link. If anyone has a link to how that LLM assitance there happens to be practically usable, I'd appreciate to see if it appers to be effective for my MCML efforts that way.

I need a quick&dirty current reference. Nominal would be 30 uA at 3.3V but should be usable at 5V and acceptable range would be 20~60 uA. Anyone got something easy to propose ?

10:06 p.m.

ive used this circuit before and on a punch it's good enough

10:06 p.m.

otherwise, a high enough voltage and a high enough resistor should work

I meant an on-chip reference ... you can't make zener in gf180mcu

Thomas Dexter started a thread. 2026-05-31 11:05 p.m.