wafer.space Community

ah I have not been paying attention here

Another option could be mezzanine connectors (similar to the Raspberry pi compute module) The connectors are sub $0.10 each.

We're planning to use those in Tiny Tapeout

@Andrew Wingate - My understanding was those connectors tend to be hugely expensive in anything but 100k units (which is why everyone ends up using PCIe or other similar connectors) but maybe things have changed?

Tim 'mithro' Ansell

@Andrew Wingate - My understanding was those connectors tend to be hugely expensive in anything but 100k units (which is why everyone ends up using PCIe or other similar connectors) but maybe things have changed?

https://www.lcsc.com/product-detail/C2763968.html Nah, they seem to be available and cheap

YXT-BB10-40S-02 | YXT | Price | In Stock | LCSC Electronics

YXT-BB10-40S-02 by YXT - In-stock components at LCSC. Price from $0.0571. Free access YXT-BB10-40S-02 datasheet, Package, pinout diagrams, and BOM tools.

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Cool! Maybe we should offer that as a COB optoin then?

7:19 p.m.

@urish - You going to annoy @carlfk by making the board size/shape change again? So he has to redo the mounting for tt.fpgas.online ?

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What exactly are you referring to with "that"?

7:20 p.m.

yes, we figured out the current 2x2x20 DIP headers is pretty bad UX

Tim 'mithro' Ansell

@urish - You going to annoy @carlfk by making the board size/shape change again? So he has to redo the mounting for tt.fpgas.online ?

So he has to [tell @Andrew Wingate] to redo the mounting for tt.fpgas.online

ftfy

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urish

What exactly are you referring to with "that"?

Carl has a rack of tiny tapeout boards connected to raspberry pis and cameras that are accessible to play with remotely. Every version of TTO boards you all have released has a different layout for the mounting holes

I was asking about

Cool! Maybe we should offer that as a COB optoin then?

urish

I was asking about

Cool! Maybe we should offer that as a COB optoin then?

To have the dies mounted to a PCB and have a mezzanine connector on the back opposed to castellated or dip options. What form factor works best for people to use? What would they like (and at what scale?)

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7:29 p.m.

These mezzanine connectors can be hand soldered as well, they're available and inexpensive, so think it sounds viable

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@Andrew Wingate - I think we just need to create some options and give them a go

Example of a mezzanine connected COB This would probably be the one I'd choose. Example has 40 pins, but there's room for a lot more.

Looks nice - though, having the connector exactly in the middle means that you have better chances of inserting it in the wrong orientation (edited)

urish

Looks nice - though, having the connector exactly in the middle means that you have better chances of inserting it in the wrong orientation (edited)

That's why I put the pin1 designator

But good call. Not sure how the best way to do that would be. Even if it's offset still doesn't help.

yes, pin1 helps but it requires you to pay extra attension

10:09 a.m.

I imagine most carrier boards will have some rect marked where you insert the daugtherboard.

10:09 a.m.

So if you tried to insert it wrong orientation, the offset would cause these not to match (and in some cases, the daugther board might get of of the host board boundaries)

10:10 a.m.

so it's not full-proof either, but it gives you another cue that you did something wrong.

10:10 a.m.

If this wasn't BOM sensitive, I'd suggest just using two smaller connectors (20+30?), then this would be pretty much foolproof

I was thinking that. I could also make a footprint that already contains all that so people don't need to reinvent. I also thought maybe knocking a corner off, or a hole

Yep, corner could also help here

10:12 a.m.

I think there are also keyed connnectors, but they are probably more expensive

If we do put it way over to the side there could be a warning message that says something DANGER

10:13 a.m.

only shows when it's reversed

do it like Intel Edison corner/side connector placement and maybe throw a single M2 hole on the opposite corner or something

Something like this maybe?

I would definitely like to see such a connector for the default pad frame of the example project and that would include the decoupling caps and separate io/core voltage on the power pins. And yes, if it's in the middle it can be inserted backward but then same for a QFN that can be soldered at wrong orientation or a DIP inserted backward ... when it's on the edge the routing of sigcal can become a pain. You could actually just notch the PCB (or put a couple of hole) and put a pin header on the main board to prevent wrong orientation while keeping it in the center.

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tnt

I would definitely like to see such a connector for the default pad frame of the example project and that would include the decoupling caps and separate io/core voltage on the power pins. And yes, if it's in the middle it can be inserted backward but then same for a QFN that can be soldered at wrong orientation or a DIP inserted backward ... when it's on the edge the routing of sigcal can become a pain. You could actually just notch the PCB (or put a couple of hole) and put a pin header on the main board to prevent wrong orientation while keeping it in the center.

I think we can find something much more elegant, but I love the idea!!

I should maybe prepare a padring config template that's designed to work with my 40-pin COB footprint

Also does anyone have a suggestion for the number of pins? 50p would fit fine. There's not really any extra cost for extra even if they're unused.

Tholin

I should maybe prepare a padring config template that's designed to work with my 40-pin COB footprint

I guess maybe wait?? Tim was saying there may be a couple version of padrings?

@Andrew Wingate Default pad frame needs more than 50 pins

tnt

@Andrew Wingate Default pad frame needs more than 50 pins

There's a fairly significant jump going to 60 pins. Is that adequate?

Significant jump of what ?

tnt

Significant jump of what ?

price and availability

2x30 ?

or 2x40 ... (edited)

So, 60 is the target?

or 30 + 40 will also prevent wrong way insertion ...

2:24 p.m.

Actually ideally it'd be like 70 ( well don't think there is anything between 60 and 70 ) so you can put a couple more ground pins in there and double up the power ... (edited)

The price and availability is pretty flat up to 50 pins, so if there are 2, 90 is also probably fine?

Sure more is never an issue

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Then depending on what Tim wants to do he has some high pin count for some of the less complex COB if desired

tnt

@Andrew Wingate Default pad frame needs more than 50 pins

Can you point me to where I can find the default pad frame?

https://docs.google.com/spreadsheets/d/1sZCpz6yy-bHGaV2BVG4IZOLBWn--WIddM9pkCQm_Vyc/edit?usp=sharing

TT GF180 padframe

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2:32 p.m.

That's the TT padframe that was picked as the default pad frame for the user project ( except all the "names" are irrelevant, just that signal pins are signal pins and power/ground pins are power/ground pins ). (edited)

@tnt Something more like this then?

Yup.

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Do I create a COB footprint based on this padring from a DIP-64 ceramic carrier?

2:58 p.m.

Pro: would be compatible with real DIP carriers Con: requires awkward padring setup on the die

I thought it was generally not advisable to use multiple of those kinds of connectors because then SMT alignment becomes an issue, and the tolerance for alignment gets very tight.

That is a valid concern

I don't think you should underestimate SMT alignment issues with multiple connectors.

Andrew Wingate

The price and availability is pretty flat up to 50 pins, so if there are 2, 90 is also probably fine?

Well, it is 1c per wire bond and you need one wire bond per pad at least. So 80 pins doubles the cost from 40 pins.

7:31 p.m.

Frequently people seem to double bond power stuff.

Supporting customers at Efabless, 64 pins on Caravel and even OpenFrame was always a bit limiting. That’s why I was excited when 74 was described for the TT default padframe

@algofoogle (Anton Maurovic) - I've pondered a bit about how people are using all these pins

@Tim 'mithro' Ansell When you want to test things, you often try to export internal signals to have some visibility and you can quickly run out that way.

9:22 a.m.

In the pad frame above, only 56 are actual user IO, rest is power/ground ( multiple rails, multiple bond per rail ). (edited)

tnt

@Tim 'mithro' Ansell When you want to test things, you often try to export internal signals to have some visibility and you can quickly run out that way.

I think that is why we need to create a decent internal logic analyser / oscilloscope

Both of these need memory ... which is huge on-chip ... (edited)

tnt

Both of these need memory ... which is huge on-chip ... (edited)

Yeah, having better memory options/solutions would help with that.

9:31 a.m.

And better connectivity like high speed USB and such

9:33 a.m.

However, we are not there yet with such things.

@tnt I've been playing in my mind with the number of pins you're looking for and how to best accomplish that. On one hand we just have the sheer number of pins and I am not sure how many wire bonds @Tim 'mithro' Ansell is wanting to let people have. That said, the picture here has 78pins and there is some room for some other things as well--and/or instead. Instead could also just be testpoints. They don't need to be brought down to the main PCB board and can remain on the COB Another idea, is to have some solderable jumpers or 0R resistors that can bridge a pin from the COB to the pcb. And finally if something like the solderable jumper is a viable option, is there some way to have the same effect on the die itself with a MUX or the like. I am trying to wrap my head around the actual utility here. There are user_pins and power_pins I can understand the desire for more pins, but don't know what that means in practice and if it could/should be more shared_pins Thanks

I asked in the discord of another product (tinyclunx) that uses two of these connectors about alignment issues, this was the reply FWIW: "As in the 2 DF40 Hirose connectors being misaligned/slightly rotated? So far, have not seen anything liek this. Have got fabrication done at the local SMT, Elecrow and JLCPCB. All have been perfect over more than 100 units. These connectors seem to self align with solder surface tension. I could see them moving to the right spot when hand placing them and reflowing. PS: these connectors are used in very high volume products so am sure they've been optimized for self alignment. Must have ENIG plating for this pitch to help."

@Andrew Wingate Of those 74 bond pads it's important to note only 56 are "user io". The other being power and if you include decaps on board that means you could probably get by with only say 1 power pin per rail on the breakout and maybe 4 gnd pads. So that's "only" 63 external castellated pins.

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5:12 p.m.

The chips needs several bond pads for power because the rings inside the chip are not that good of a conductor, a PCB trace is much better to move power around and feed it at several place around the die. But to connect to the "mother board" you don't necessarely need multiple castellated pins. (edited)

tnt

The chips needs several bond pads for power because the rings inside the chip are not that good of a conductor, a PCB trace is much better to move power around and feed it at several place around the die. But to connect to the "mother board" you don't necessarely need multiple castellated pins. (edited)

I see, thank you. I think I am understanding a bit better now. Any ideas on how many decoupling caps? I am assuming a few .1uF?

I'd go with a couple of 1uf for each rail.

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I put together a few numbers so we can get a feel for the cost to put dies on COB to present to you all and @Tim 'mithro' Ansell COB Cost Breakdown

| Item              | Price (1k COB) | Each     | Notes / Link |
|-------------------|----------------|----------|---------------|
| **PCB**           | $45.00         | $0.0450  | PCB cost is always needed — assumed 6×6 grid @ qty 30 panels |
| **Wire Bond**     | $500.00        | $0.5000  | For 50 wirebonds |
| **Castellated**   | $100.00        | $0.1000  | Extra cost on top of other PCB cost |
| **70p Mezzanine** | $291.20        | $0.2912  | [LCSC C19089236](https://www.lcsc.com/product-detail/C19089236.html) |
| **60p Mezzanine** | $247.40        | $0.2474  | [LCSC C294544](https://www.lcsc.com/product-detail/C294544.html) |
| **50p Mezzanine** | $83.20         | $0.0832  | [LCSC C2763977](https://www.lcsc.com/product-detail/C2763977.html) |
| **1µF Decap**     | $11.60         | $0.0116  | Assume 4 per COB |
| **Assembly Fees** | $50.00         | $0.0500  | 1¢ per component |

The general idea is that COB will be panelized in ~100mmx100mm panels. Some components can be put on the pcb before (or after) the die like connectors--mezzanine most likely--and decoupling caps reducing the number of pins that may need to connect to the motherboard like TinyTapeout and @tnt with high pinout demands would like. Please let me know if there are any other variations anyone would be looking for and/or interested. DIP like @Tholin has been working on are still available too, but didn't really have a place on this sheet I don't think link to spreadsheet https://docs.google.com/spreadsheets/d/17oUlsN1SRM1lt5fsIiS17jE1C9ZgoKSnC5zECYs8Bc4/edit?gid=0#gid=0

COB pricing guide

Hi, nice to meet you all. My name is Andrew and my team and I are very excited to start work on porting the MOSbius chip (mosbius.org) to GF180 with the wafer.space project. I have just now started working on this project so please forgive my ignorance in the following questions. 1) I recall from a previous email chain that @Tim 'mithro' Ansell had kindly let us know that we can use our own padframe. Is that still true for the COB option ($8500), or is there a default padframe we would need to follow? 2) If we can use our own padframe, I’m assuming we would also need to design the wire bond as well? 3) For the default padframe that @tnt mentioned above with the 56 “user io” bond pads, can that be generated with the following template? https://github.com/wafer-space/gf180mcu-project-template 4) Would the template also generate a seal ring? We had an issue with the 2025 Chipathon where a seal ring was not generated with the padframe. I believe GF will end up adding the seal ring for us. Apologies for the many questions. I would greatly appreciate your time and help clearing these questions up for us. Thank you.

GitHub - wafer-space/gf180mcu-project-template: Project template fo...

Project template for wafer.space MPW runs using the gf180mcu PDK - wafer-space/gf180mcu-project-template

@asc for (3), yes, the default padframe in that template is the one I was talking about.

1

@tnt are all the "user" type pads a single type of pad (Analog, digital, bidirectional, etc) ? I noticed that the pads have different "TT Function"s but I'm assuming that is specific only to the TT padframe?

The "TT" function is just for TT. In the template above they have some type defined, but you can pick/change to whichever you need for your needs.

1

I see, thank you

@asc 1) Yes, the CoB option for $8500 uses the default padring. You can change the I/O pad types, put you shouldn't change the number of pads, as this would change the position of the bondpads.

1

Hi all, is the config.yaml file the only file I would need to alter to generate a custom padframe? Also, of the 74 pads, are all of them fair game to customize?

Hi Everyone, We just got into the wafer.space design, so excuse me if I ask questions that have been answered. Looked around a bit but I am left with the following question. I was talking to @asc and he mentioned that you are developing a template with 74 pads; ( 20 + 17 ) x 2 The reticle is sqrt(20) so about 4.5mm on the side (although maybe the reticle is rectangular). In any case 20 pads on 4 mm would mean 200um center-to-center pitch. That sounds large. Obviously we do not need to push is to 50um which likely might not work for COB, but what is the guideline for the COB? What is the center-to-center pitch on the PCB pads? 74 pads would work for out MOSbius chip (https://mosbius.org) , but more pins can always be put to very good use for our application ... Finally, we would like a version which is dual in line style so we can put it in a breadboard. You can see our current PCB (with a chip in a package) attached. @Tim 'mithro' Ansell So how would we go about this? Do all the designs in the run use the same # pins and positions for the COB at 8,500. Or if we do the designwork of the PCB, can we make our own, or does that come at a higher cost? Many thanks! Looking forward to be part of this exciting opportunity for cheap 'packaged' silicon. For those that have paid for chip packaging they probably realize that silicon cost is one thing, packaging is a whole other painful expense ... -- Peter Kinget (edited)

Hi Peter, Yes, there is the default template which has 74 pads, 54 of which are used for signals. The $8,500 USD option with CoB packaging can only be used with this exact padframe, since the setup cost is shared across all designs. While you should not change the position of any pads, you can change the pad types. For example, all of the 54 pads could be used for analog. The remaining 20 pads are used for power and ground and should not be changed, since they will be connected to the power/ground rings of the CoB footprint on the PCB. If you do your own packaging, you could fit more pads into the padframe, or remove the padframe completely - this is up to you. I believe there are different daughter boards in development in the #cob channel.

Leo

@Tim 'mithro' Ansell would it be possible for someone to design their own padframe and choose the CoB option? What would the additional cost be?

1

I'm open to potentially having more options around pad frames / PCBs if we can make them come in within the required budget.

1

@Leo Moser (mole99) The padframe template seems to have 56 user pads and 18 power/ground pads instead of the 20power/ground you mentioned. Can you confirm the correct number? Is there some sort of guide I can follow to switch out the different IO types? I am getting lost in what needs to be done in the system verilog and yaml files to generate a custom padframe. Looking at the system verilog files, it seens that the BIDIR pads are actaully digital pin cells "gf180mcu_fd_iobi_24t". Is it possible to use the analog pin cells "gf180mcu_fd_ioasig_5p0" instead? Thank you, Andrew

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asc

@Leo Moser (mole99) The padframe template seems to have 56 user pads and 18 power/ground pads instead of the 20power/ground you mentioned. Can you confirm the correct number? Is there some sort of guide I can follow to switch out the different IO types? I am getting lost in what needs to be done in the system verilog and yaml files to generate a custom padframe. Looking at the system verilog files, it seens that the BIDIR pads are actaully digital pin cells "gf180mcu_fd_iobi_24t". Is it possible to use the analog pin cells "gf180mcu_fd_ioasig_5p0" instead? Thank you, Andrew

You're absolutely right! I only counted the INPUT and BIDIR pads in the template, but we also have a clock and reset. So, 56 user pads and 18 power/grounds pads is right.

5:36 p.m.

Basically, you just instantiate a different pad type in the Verilog and swap out the instance name in the LibreLane config.yaml Let me know if you encounter any issues.

5:37 p.m.

Yes, the bidir pads are digital input/output pads. You can swap them against the analog pad you mentioned.

Sounds good, thank you

1

Tim 'mithro' Ansell

I'm open to potentially having more options around pad frames / PCBs if we can make them come in within the required budget.

How do we go about this. Given the time constrains we will start with the standard for now, but for MOSbius we need pins, pins, pins ... So it would be great if you could take a stab at trying to increase the # of pins. Also we need analog pads, i.e. only ESD and no buffers or other active components in the pads. Finally our need for VDD/VSS pads is less since we are operating at lower frequencies so we can worry a bit less about bondwire inductance.

Leo Moser (mole99)

Basically, you just instantiate a different pad type in the Verilog and swap out the instance name in the LibreLane config.yaml Let me know if you encounter any issues.

What is the pad type for a basic analog pad: only ESD and no active components like buffers etc.

Leo Moser (mole99)

Hi Peter, Yes, there is the default template which has 74 pads, 54 of which are used for signals. The $8,500 USD option with CoB packaging can only be used with this exact padframe, since the setup cost is shared across all designs. While you should not change the position of any pads, you can change the pad types. For example, all of the 54 pads could be used for analog. The remaining 20 pads are used for power and ground and should not be changed, since they will be connected to the power/ground rings of the CoB footprint on the PCB. If you do your own packaging, you could fit more pads into the padframe, or remove the padframe completely - this is up to you. I believe there are different daughter boards in development in the #cob channel.

Leo

@Tim 'mithro' Ansell would it be possible for someone to design their own padframe and choose the CoB option? What would the additional cost be?

Thank you, Leo. There are 74 pads. Fully understood that location should not change, so that the bonding setup is the same for all. I can assign the type of the pads as I see fit. But I have to assign 20 to VDD/VSS. Can I change the location of those 20 pads or they are fixed?

They're fixed.

6:02 p.m.

The idea is those power pads will get bonded to the various power rails in the "common" bonding setup. (edited)

1

6:04 p.m.

The analog pads don't have buffer no. Just ESD diodes to both the DVDD and DVSS ( which are IO voltages ) (edited)

@peterkinget I will try to use the template to generate the analog pads from the Chipathon for the design. (https://gf180mcu-pdk.readthedocs.io/en/latest/IPs/IO/gf180mcu_fd_io/datasheet.html) They only have double diode protection. No buffers.

Of course if you have your own packaging provider, you can do whatever you want and just get dies

I guess you had to have the other mosbius chips packaged somehow

@tnt we cant say no to 1.5$ per chip for packaging

1

@asc / @peterkinget - I'm hoping that the stuff behind the $1.5 per chip packaging will be available generally in the future for any bare die packaging through the PCBA houses, then you can choose how much you want to pay, like $0.10 for 6 wire bonds and a $0.04 PCB or $5.00 for 400 wire bonds and $1.00 PCB.

9:28 p.m.

And then wafer.space can ignore packaging stuff

9:29 p.m.

The general costs are the PCB and ~$0.01 per bond.

9:31 p.m.

If you can create a PCB design + padframe which is open source and under the budget amount and the PCBA house is happy with, then I'm willing to try and make it happen and publish as an example/template for others to reuse. (edited)

9:32 p.m.

The people in this channel are probably the best people to help you figure out if you can make it work l.

Sounds good. We may give that a try. Given the time constraint, this might be a project for a future run. (edited)

Are the bare dies really that resilient to feed into pick-and-place ? I always understood that they were very sensitive and needed special tools for handling the dies without damaging them

11:48 p.m.

(If we are talking about places like JLC doing mounting in the future)

dshadoff

(If we are talking about places like JLC doing mounting in the future)

While they're talking about having a company like JLC do the wire bonding, I wouldn't call it pick and place. It's wire bonding and is just being performed by JLC

2:46 p.m.

So I have been going around and around about this. 70pin Mezzanine: I really think that version would be great, but I am concerned about users being able to get their own components for the mating side. Availability seems very low for this size Castellated: This is another viable option, but this means that users must either supply the COB to a PCBA at the time of assembly, or try to solder this chip on their motherboard themselves. This is doable but ~70 pin castellated solders gets old fast. 2row 1.27 headers: This is my latest iteration. This option has all the pins broken out (76) so users can do whatever they like. The picture on the right can probably be wave soldered, reducing the cost as much as possible because things add up fast when there's a lot of pins. Personally, I would like to see the 50pin mezzanine connector version stay on the smallest footprint version for anyone wanting to use these in application (not sure if there are any) but that option allows a PCBA to assemble an entire board and user does not need to supply anything, then can just plug in themselves easily. This decision is based on price and availability as well. @asc, I don't know what where you'd land on desires here, but an option as well for you would be the 50pin mezzanine and a bunch of testpad/breakout type areas where you could attach a probe for any pin that is not part of the 50 on the connector. We don't know the variability granted by the wirebonders. Ideally the PCB portion could be anything and as long as the pads are all in the same positions, granting @asc and others more pins taken from the power rails needed for @tnt Opinions/ suggestions anyone? @Tim 'mithro' Ansell (edited)

I'd definitely avoid 1.27 headers, they're a pain.

3:08 p.m.

I prefer mezzanine, HCTL seems to have quite a few 70~100 pin options if using 2 conectors is not acceptable. Also instead of castellated, you can do just plain LGA with just 0.5 mm pitch pads on the bottom to be reflowed on a host PCB.

1

Andrew Wingate

While they're talking about having a company like JLC do the wire bonding, I wouldn't call it pick and place. It's wire bonding and is just being performed by JLC

Thanks. I asked because there was a point in the CrowdSupply talk where Mithro said it might be possible to supply the chips (as wafer slices) as tape spools, which made me wonder about how fragile (or robust) they might be.

1

tnt

I prefer mezzanine, HCTL seems to have quite a few 70~100 pin options if using 2 conectors is not acceptable. Also instead of castellated, you can do just plain LGA with just 0.5 mm pitch pads on the bottom to be reflowed on a host PCB.

Thanks. While they're available from a couple suppliers availability seems low. Wafer.space will be able to purchase whatever because the qty is there given this will be spread across multiple projects, it does not seem places like lcsc stock very many. Ill try drawing up an lga later tonight hopefully. There seems fo be a fair amount of pushback on the 2 connectors regarding tolerances. But like I said above, hopefully the wire bonders will allow different pcbs as long as the pads stay the same, Ill draw you whatever you want if you're willing to risk it!

@tnt, I think we may have a winner here. Originally, I dismissed LGA as something that's hard to work with, but everything is pretty relative here and this actually seems like a really viable option. Depending on how the sizes of everything work out someone could even put this on some other daughterboard that does whatever they want. As shown there's 100 pins (not including the large pads in the middle) I figure sprinkling grounds all over for the analog and differential pins is a huge bonus. Let me know what you think and I think I can start to harden this design. @Tim 'mithro' Ansell thoughts?

1:11 a.m.

also of note, the way this is layed out gives an effective pin pitch of 1.13mm so it's not even that super small.

@Andrew Wingate - I think we probably want these options uploaded and listed somewhere.

Tim 'mithro' Ansell

@Andrew Wingate - I think we probably want these options uploaded and listed somewhere.

Agreed, but nothing is even real at the moment. There isn't even a schematic. I've just been dropping footprints in the editor. The pictures have been the only real thing.

Well, I created https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs

GitHub - wafer-space/chip-on-board-wire-bonded-pcbs: Wire bonded ch...

Wire bonded chip on board PCB designs. Contribute to wafer-space/chip-on-board-wire-bonded-pcbs development by creating an account on GitHub.

1

Tim 'mithro' Ansell

Well, I created https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs

I have uploaded my working files, But more importantly probably, I have compiled all the different designs and notes here: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/tree/main/scratch

chip-on-board-wire-bonded-pcbs/scratch at main · wafer-space/chip-...

Wire bonded chip on board PCB designs. Contribute to wafer-space/chip-on-board-wire-bonded-pcbs development by creating an account on GitHub.

Probably should add a "Work in progress" warning?

1

@Andrew Wingate thank you for working on this. Just to confirm, with the new 100 pin LGA design, which of the 74 pads would we be able to customize? Is it still the same where we cannot touch the location of the 18 power/ground pads?

@Andrew Wingate Looks good. I would definitely do a test solder ( make some empty board and carrier and actually test reflow ) before making thousands, but it looks nice.

6:23 a.m.

Maybe just notch a corner

@asc I would like to defer to @tnt a bit here and ask what/where do you need nets tied in the COB I am referring to https://docs.google.com/spreadsheets/d/1sZCpz6yy-bHGaV2BVG4IZOLBWn--WIddM9pkCQm_Vyc/edit?gid=0#gid=0 I would assume that we want GND IO to be the ground pour and have these all tied together on the COB. I am assuming that the rest were tied mostly because you were shooting for a QFN 64 so just tied them all to EPAD. Does this need to remain the case? I am counting 6 wirebonds to GND IO can the rest of the pads be on their own nets? @asc this would leave you (74-6) 68 pins to do with as you wish.

TT GF180 padframe

tnt

Maybe just notch a corner

Yeah I was hoping as soon as possible to just get some made and do some testing. I will see what I can come up with for pin1 marking. I am planning on V-scoring all these and that makes notches more interesting. maybe a plated through hole with a sizable annular ring? That should stand out. or now that I'm thinking about it, just a plated shape with no mask over it. It will be a bright gold spot

I kinda like this

4

I am imagining GND_IO to be laid out like this? Is that too many? Should I try reducing the pitch some?

1

Andrew Wingate

@asc I would like to defer to @tnt a bit here and ask what/where do you need nets tied in the COB I am referring to https://docs.google.com/spreadsheets/d/1sZCpz6yy-bHGaV2BVG4IZOLBWn--WIddM9pkCQm_Vyc/edit?gid=0#gid=0 I would assume that we want GND IO to be the ground pour and have these all tied together on the COB. I am assuming that the rest were tied mostly because you were shooting for a QFN 64 so just tied them all to EPAD. Does this need to remain the case? I am counting 6 wirebonds to GND IO can the rest of the pads be on their own nets? @asc this would leave you (74-6) 68 pins to do with as you wish.

68 pins would be great.

1

@Andrew Wingate Anything marked GND should be wired together with as big traces/planes as possible

The power pins I was originally thinking of wiring them together on the breakout and bypass them there, but in the case of the LGA, if we can put the bottom pads of power close enough to where they get bonded on the top, it's probably fine to not treat them differently. I maybe would use 0.8 mm PCB too. Not sure if JLC offers ViP plated over ?

tnt

@Andrew Wingate Anything marked GND should be wired together with as big traces/planes as possible

The power pins I was originally thinking of wiring them together on the breakout and bypass them there, but in the case of the LGA, if we can put the bottom pads of power close enough to where they get bonded on the top, it's probably fine to not treat them differently. I maybe would use 0.8 mm PCB too. Not sure if JLC offers ViP plated over ?

Looks like JLC can do POFV (Plated Over Filled Via), and on 6+ layer boards it looks like they'll do it at no extra cost since 2024 -- https://jlcpcb.com/blog/Free-Via-in-Pad-on-6-20-Layer-PCBs-with-POFV (and https://jlcpcb.com/blog/jlcpcb-free-via-in-pad)

Free Via-in-Pad on 6-20 Layer PCBs with POFV

JLCPCB via-in-pad on 6- 20 layer PCBs are upgraded to POFV (Plated Over Filled Via) for free and will continue to be the free default for all upcoming high layer count boards.

tnt

@Andrew Wingate Anything marked GND should be wired together with as big traces/planes as possible

The power pins I was originally thinking of wiring them together on the breakout and bypass them there, but in the case of the LGA, if we can put the bottom pads of power close enough to where they get bonded on the top, it's probably fine to not treat them differently. I maybe would use 0.8 mm PCB too. Not sure if JLC offers ViP plated over ?

I've been planning to use .8mm this whole time. @asc it looks like 10 pins will be used for GND this will leave (74-10) 64 pins to use as you see fit. Thank you @tnt , I will try to get something drawn today sometime maybe and hopefully get something off to manufacture in the next few days.

@tnt Does this look ok for a bonding ring layout? It looks like you wanted to keep the power inputs in the corner pads so I kept that. The power pins will be broken out individualy and you can link/bypass them on the motherboard. I will try to get those pads as close to--if not directly under--the vias for power. Is there anything else you'd like to see The pin spacing (21 on each side and 16 on top/bottom) have been preserved -# the bondwire layout has obviously not been updated

7:18 p.m.

@Tim 'mithro' Ansell would you like to add anything in here. Previous discussions have revolved around keeping as many pins available for project specific needs over tying some nets together such as VDD.

@Andrew Wingate The pwr aux are actually in the middle of the left/right side, not at the corners.

tnt

@Andrew Wingate The pwr aux are actually in the middle of the left/right side, not at the corners.

Dangit, I had it there for previous revisions.

I'd check if it was possible to bring the pads in closer without violating the 45 degree limit. I feel like this could be smaller.

Tholin

I'd check if it was possible to bring the pads in closer without violating the 45 degree limit. I feel like this could be smaller.

Thanks @Tholin I thought about that, but decided against hoping I could squeeze half the vias under the bond wires for the inner ring io's Is there a huge reason to try to shrink it down much further?

7:35 p.m.

*this is still the old padring shown

7:36 p.m.

although I guess it would anyways. Sure, I can shrink it a bit

If the wires are too long they can have too much slack and end up touching.

Alright, I think I got it. Whatever is going on in that top left corner threw me for a loop every time. @tnt and @Tholin do you see any problems if I start moving forward with this?

1

I'd do what I did and check your work by using a comment layer to map out the bond wires. (edited)

Tholin

I'd do what I did and check your work by using a comment layer to map out the bond wires. (edited)

Yeah, just wanted to check overall layout before going that far. the two bottom left wires have been placed and are within 45deg Thank you again

8:27 p.m.

@tnt Is there somewhere I can find the pitch for the bond pads?

@Leo Moser (mole99) do you have a GDS handy ?

8:30 p.m.

In theory they're equally spaced, so just dividing the die size by number of pins should be close enough.

8:31 p.m.

Note that the 45 deg rule is also not strictly required for the corner ones.

1

tnt

In theory they're equally spaced, so just dividing the die size by number of pins should be close enough.

Ok, I'll go with that. Afterall, I think this is more of a map for manually placing the bond points. Thank you

@tnt @Tholin Thanks again. I think this is the final rev

How big is it?

Tholin

How big is it?

That is pretty small!

too small?

No

1

We're well within JLC's capabilities as far as PCBs go

9:31 p.m.

New vs old. I think this will look really nice

2

This might fit onto a DIP-40 compatible carrier.

1

not quite. I checked that already...

9:36 p.m.

LGA is 16mm and space in DIP is only 12mm

9:37 p.m.

I don't think trying to squeeze lga by that much is worth it. Things become very small

Tholin

This might fit onto a DIP-40 compatible carrier.

oh, you probably thought just the padring. it might

Would require some intense routing on a 4-layer PCB, but doable

9:46 p.m.

Assuming supporting components are required

You wouldn't be using all the pins then either, so that would save a bunch of space for traces. Still not sure how things will land on different formats. Is the pattern more important? or what makes one something new that they consider it different

9:47 p.m.

There are 32 pins that go out the top and bottom. That's close to satisfying the 40

@Andrew Wingate final is 64 customizable pins and 10 unchanged ground pins? I’m assuming the ground pin locations are identical to the 10 ground pins locations already in the template (from the TT padframe spreadsheet)?

asc

@Andrew Wingate final is 64 customizable pins and 10 unchanged ground pins? I’m assuming the ground pin locations are identical to the 10 ground pins locations already in the template (from the TT padframe spreadsheet)?

That is correct.

10:45 p.m.

Hope that works for you all

10:46 p.m.

We can get a final sign-off from @Tim 'mithro' Ansell, but I feel pretty confident.

This is a nice step up from the original Caravel and OpenFrame, which offered 38 (technically 40) and 44 signal pins respectively... so now we'd get at least 54 signal pins, and each of them as customisable pads.

10:58 p.m.

Great work @Andrew Wingate and team

2

Great work. I would still like to suggest to have more signal pins. I am not sure why you are using so many VSS pins. Now I might be missing something in terms of the limitations w.r.t. COB bonding, but 10 GNDs out of 74 is a lot, in particular for those of us who are not going after high speed or RF designs (which are going to be challenging in GF180MCU anyway). We need 68 pins (and preferrably more) for MOSbius. But I do not think we are unique in the "need for pins". I did a quick area estimate planning exercise yesterday -- see below -- and we have tons and tons of spare area and could put in a lot of functions, but just need more pins ... That is in part due the nature of our MOSbius design, but is true for many designs by starting designers where you want a good number of pins for debug. We saw the same in the chipathon. Can we set up a zoom call to discuss. I am on pacific time but can accommodate times the work for US or EU. Many thanks.

Tholin

Assuming supporting components are required

Have you considered putting the chip footprint on the PCB under a 45 deg angle (see e.g. the arduino nano board), that often simplifies the routing. If it is allowed by the COB packaging process.

peterkinget

Have you considered putting the chip footprint on the PCB under a 45 deg angle (see e.g. the arduino nano board), that often simplifies the routing. If it is allowed by the COB packaging process.

I thought about that as well. The main argument that came to mind was what the wirebonders would think of it. I think there are still a lot of negotiations happening, so I'm not sure what they feel a new design would consist of, whether it be changing orientation, number of pins while still sharing locations from default, different spacing on a panelized PCB.

11:14 p.m.

Another option for those like @Tholin would be to create a board that can just accept the LGA and do whatever you like there. This particular design kinda makes me feel yucky, but not entirely sure why, but figured I'd share

peterkinget

Great work. I would still like to suggest to have more signal pins. I am not sure why you are using so many VSS pins. Now I might be missing something in terms of the limitations w.r.t. COB bonding, but 10 GNDs out of 74 is a lot, in particular for those of us who are not going after high speed or RF designs (which are going to be challenging in GF180MCU anyway). We need 68 pins (and preferrably more) for MOSbius. But I do not think we are unique in the "need for pins". I did a quick area estimate planning exercise yesterday -- see below -- and we have tons and tons of spare area and could put in a lot of functions, but just need more pins ... That is in part due the nature of our MOSbius design, but is true for many designs by starting designers where you want a good number of pins for debug. We saw the same in the chipathon. Can we set up a zoom call to discuss. I am on pacific time but can accommodate times the work for US or EU. Many thanks.

Can we set up a zoom call to discuss. I am on pacific time but can accommodate times the work for US or EU.

I'm not sure who outside @tnt wants to speak for the default padframe. I personally don't have any opinions but would offer to be present if you all think I would add anything.

Also I've been following the recommendations laid out by STMicro on LGA patterns and am opting for non solder mask defined (NSMD) pads for reliability and feel there shouldn't be a lot of rework done on these chips (you're getting 1000 anyways) https://www.st.com/resource/en/application_note/an5886-guidelines-for-design-and-board-assembly-of-land-grid-array-packages-stmicroelectronics.pdf

@Andrew Wingate / @peterkinget / @tnt / @asc / @Tholin I have a couple of random thoughts (not in any particular order):

Ultimately my thoughts don't really matter, the only ones who really do are the PCBA house & the customers. If the result is under budget, actually can be manufactured and makes people happy then it is perfectly fine by me.

In terms of PCBA negotiation, PCB Way is the furthest along, then Seeed and JLCPCB the furthest behind. We should make sure the PCBs are manufacturable at PCB Way as P0.

I'm happy to have multiple PCBs and pad frame designs -- 4-6 is fine, >10 is probably too many.

I really want to have at least one option which is DIP for breadboard compatible usage.

I have square & symmetrical designs, just gives one another way to screw things up.

The only silicon we have today uses either Mehdi/OpenFASoC or the caravel padframe. Hence to test the cob wire bonding before we get back Run 1 silicon we need some designs which are compatible with that. I think we do really need to test this whole process before Run 1 gets back.

I believe @stuart is the only person who has actually done cob wire bonding before (as part of the Tiny Tapeout test) we should ask him for advice and thoughts.

12:05 a.m.

There are also design rules from one house found @ https://drive.google.com/file/d/1touEQHWAOTon_98TdiVLKKqsQ8RJJ1tP/view?usp=sharing

Tim 'mithro' Ansell

There are also design rules from one house found @ https://drive.google.com/file/d/1touEQHWAOTon_98TdiVLKKqsQ8RJJ1tP/view?usp=sharing

design rules from one house found

Awesome, thanks. Giving that a read. Seems I'm out of spec in a couple areas

I'm happy to have multiple PCBs and pad frame designs -- 4-6 is fine, >10 is probably too many.

@peterkinget Personally I would like to keep my just one LGA pattern but would be happy to create a bond pad version for you all. Let me know what you have in mind and I can try.
In this case I can connect some nets back up if you'd like @tnt?
[...] We should make sure the PCBs are manufacturable at PCB Way as P0.

I just glossed over capabilities. I tried to keep everything very loose. Seems we're still on point

The only silicon we have today uses either Mehdi/OpenFASoC or the caravel padframe [...] we need some designs which are compatible with that.

Is the TT frame compatible? (edited)

@Andrew Wingate - Afraid I have no idea, would have to ask @tnt on the frame compatibility.

1

Fiducials added and ground landings moved to adhere to design constraints edit: I also changed pin #s to harmonize with TT pin #s (edited)

Andrew Wingate

design rules from one house found

Awesome, thanks. Giving that a read. Seems I'm out of spec in a couple areas

I'm happy to have multiple PCBs and pad frame designs -- 4-6 is fine, >10 is probably too many.

@peterkinget Personally I would like to keep my just one LGA pattern but would be happy to create a bond pad version for you all. Let me know what you have in mind and I can try.
In this case I can connect some nets back up if you'd like @tnt?
[...] We should make sure the PCBs are manufacturable at PCB Way as P0.

I just glossed over capabilities. I tried to keep everything very loose. Seems we're still on point

The only silicon we have today uses either Mehdi/OpenFASoC or the caravel padframe [...] we need some designs which are compatible with that.

Is the TT frame compatible? (edited)

Thanks, @Andrew Wingate, what timezone are you in? It would be great to connect in a webmeeting. Your design looks nice. Where do you think you are out of spec? How big are your bondpads on the chip? They seem bigger than my 100um pads at a 200um pitch. I left a 1.5mm spacing around the die to statisfy the 1.5 x die thickness clearance (die are typically way thinner than 1 mm, don't know if the dies are backlapped in GF180); then I placed a row of 200x100 bondfingers (PCB side) at a 200um pitch on top. Not sure if the PCB house can support that, but it seemed to satisfy the requirements in the doc that @Tim 'mithro' Ansell shared above. If the PCB can support, then we can have straight wires, or am I missing something? Why are some of your bondfingers bigger? What CAD are you using for the PCB design? I attach a PDF export of an Altium webpage https://resources.altium.com/p/pcb-design-rules-chip-board-layout?utm_source=chatgpt.com. That tool seems to have a nice COB built in tool. In any case, notice how they rotate the pads to be aligned with the bondwire. This is also clearly visible on the picture that is on the wafer.space front page. Have you considered doing that or are there reasons why you can not? (edited)

PCB_Design_Rules_for_Chip-on-Board_Layout.pdf

3.98 MB

PCB Design Rules for Chip-on-Board Layout

There is one simple type of packaging that is not really packaging in the conventional sense: chip-on-board.

peterkinget

Thanks, @Andrew Wingate, what timezone are you in? It would be great to connect in a webmeeting. Your design looks nice. Where do you think you are out of spec? How big are your bondpads on the chip? They seem bigger than my 100um pads at a 200um pitch. I left a 1.5mm spacing around the die to statisfy the 1.5 x die thickness clearance (die are typically way thinner than 1 mm, don't know if the dies are backlapped in GF180); then I placed a row of 200x100 bondfingers (PCB side) at a 200um pitch on top. Not sure if the PCB house can support that, but it seemed to satisfy the requirements in the doc that @Tim 'mithro' Ansell shared above. If the PCB can support, then we can have straight wires, or am I missing something? Why are some of your bondfingers bigger? What CAD are you using for the PCB design? I attach a PDF export of an Altium webpage https://resources.altium.com/p/pcb-design-rules-chip-board-layout?utm_source=chatgpt.com. That tool seems to have a nice COB built in tool. In any case, notice how they rotate the pads to be aligned with the bondwire. This is also clearly visible on the picture that is on the wafer.space front page. Have you considered doing that or are there reasons why you can not? (edited)

what timezone are you in?

I'm in Chicago - UTC-6. And you?

Your design looks nice. Where do you think you are out of spec?

The minimum distance to a pad based on the height of the die. (just a couple of the ground wires.)

How big are your bondpads on the chip? They seem bigger than my 100um pads at a 200um pitch.

If you're talking about what you see above, those are not the real pad sizes. they're just drawings for reference. I also am not well versed enough to answer some of the other questions, you'll have to ask someone else.

Why are some of your bondfingers bigger?

In an effort to get some more pads broken out for you all, I talked to tnt about breaking some nets up so you could use them for your purposes. In that we wanted to keep the traces as short as possible so there is a via directly in those. I feel I will be going back and changing that portion as it's less necessary now. We'll see. Long story short is they don't have to be.

What CAD are you using for the PCB design?

I'm using KiCad

Altium webpage [...] seems to have a nice COB built in tool. In any case, notice how they rotate the pads to be aligned with the bondwire. Have you considered doing that or are there reasons why you can not?

This would be kindof a pain in Kicad and I don't think this is necessary. You're welcome to design your own. It seems like you have the same layout as the TT layout with 74 bonds. https://docs.google.com/spreadsheets/d/1sZCpz6yy-bHGaV2BVG4IZOLBWn--WIddM9pkCQm_Vyc/edit?gid=0#gid=0 If you want to make your own pin map, I will make a version for you. (edited)

chip_top.gds.gz

4.77 MB

tnt

@Leo Moser (mole99) do you have a GDS handy ?

This is generated using the project template. The pad positions are fixed, the signal pad types can be changed.

Not sure how realistic this timing is but I'm going to be in Shenzhen next month (7-20th) and will be visiting my friend's cob factory for some TT projects and tests, would be happy to take other boards and dies too. They only do aluminium bonding, not gold wires - and can do either black or colourless transparent glob top

6:33 p.m.

https://youtu.be/XJmWoBJjvlI?si=Bj2e63CKN8ztEQ2d Here's a video with more about what we did last year

Zero To ASIC Course

Chip on Board! Wirebonding ASICs

6:35 p.m.

One thing to consider is making sure there's nothing too big / tall near the bonding area so the machine head has enough clearance. The cob process has to be done after smta afaik as the bonds wouldn't survive the reflow oven temps - they had to do some creative programming to get around the headers on the boards we took last time

"The cob process has to be done after smta afaik as the bonds wouldn't survive the reflow oven temps" Oh well that would kind of kill the LGA or castellated pad idea and only leave mezzanine connects as the only option if you can't reflow after wire bonding ....

tnt

"The cob process has to be done after smta afaik as the bonds wouldn't survive the reflow oven temps" Oh well that would kind of kill the LGA or castellated pad idea and only leave mezzanine connects as the only option if you can't reflow after wire bonding ....

Yeah, that would really be a problem lol.

stuart

One thing to consider is making sure there's nothing too big / tall near the bonding area so the machine head has enough clearance. The cob process has to be done after smta afaik as the bonds wouldn't survive the reflow oven temps - they had to do some creative programming to get around the headers on the boards we took last time

I thought that the wire bonds were pretty protected after the covering blob was done?

I've been trying to track that down as well. My google-foo has been poor.

This is also why I think we need to try and do some experiments / runs ASAP.

It's covered in epoxy which should hold up to the heat just fine

Andrew Wingate

what timezone are you in?

I'm in Chicago - UTC-6. And you?

Your design looks nice. Where do you think you are out of spec?

The minimum distance to a pad based on the height of the die. (just a couple of the ground wires.)

How big are your bondpads on the chip? They seem bigger than my 100um pads at a 200um pitch.

If you're talking about what you see above, those are not the real pad sizes. they're just drawings for reference. I also am not well versed enough to answer some of the other questions, you'll have to ask someone else.

Why are some of your bondfingers bigger?

In an effort to get some more pads broken out for you all, I talked to tnt about breaking some nets up so you could use them for your purposes. In that we wanted to keep the traces as short as possible so there is a via directly in those. I feel I will be going back and changing that portion as it's less necessary now. We'll see. Long story short is they don't have to be.

What CAD are you using for the PCB design?

I'm using KiCad

Altium webpage [...] seems to have a nice COB built in tool. In any case, notice how they rotate the pads to be aligned with the bondwire. Have you considered doing that or are there reasons why you can not?

This would be kindof a pain in Kicad and I don't think this is necessary. You're welcome to design your own. It seems like you have the same layout as the TT layout with 74 bonds. https://docs.google.com/spreadsheets/d/1sZCpz6yy-bHGaV2BVG4IZOLBWn--WIddM9pkCQm_Vyc/edit?gid=0#gid=0 If you want to make your own pin map, I will make a version for you. (edited)

I am on Pacific time, feel free to suggest some times and I will try to accommodate.

peterkinget

I am on Pacific time, feel free to suggest some times and I will try to accommodate.

Typically later in my evenings work the best. Some time around now some other day would be fine. If you're up for it, I would like to leave this semi-public and let others here join in if they'd like to join in. Tonight does not work for me. Tomorrow I will be out of town. I think I'm pretty free for the rest of the week, so let me know what works for you with that. Others please let us know if these times work for you.

Rest of week should work for me; wednesday best.

peterkinget

Rest of week should work for me; wednesday best.

Ok, let's tentatively shoot for Wed evening!

How about 8:15pm Pacific 10/15 -- here is a meeting room: https://columbiauniversity.zoom.us/j/98265793354?pwd=sXsJvzRF9rmJt1YTb6MCpkd0PXew7E.1

Join our Cloud HD Video Meeting

Zoom is the leader in modern enterprise cloud communications.

3

stuart

One thing to consider is making sure there's nothing too big / tall near the bonding area so the machine head has enough clearance. The cob process has to be done after smta afaik as the bonds wouldn't survive the reflow oven temps - they had to do some creative programming to get around the headers on the boards we took last time

I asked the reddit and got a response that you could reflow. There are wire bonds in many (most) regular packages. Their response in the post https://www.reddit.com/r/AskElectronics/comments/1o61zzx/boards_with_wire_bonded_die_and_epoxy_coating_can/

es, it can. This is a pretty common setup for cheap products where all the high integration stuff is located on a module. A lot of the handheld NES games do that. This is also not that different from the ICs. It is also epoxy coated wire bonded die.

From the AskElectronics community on Reddit

Explore this post and more from the AskElectronics community

Looked into it a bit. Found this, but doesn't seem like it's reflowed after..

While I have not been able to find anything specifically, There are a ton of BGA that seem to follow the pattern we're looking for. Found these people and if somewhere did have something suitable, these guys would probably know https://dm.henkel-dam.com/is/content/henkel/COST_EFFECTIVE_AND_RELIABLE_MATERIALS_FOR_WIREBOND_PACKAGING

Also, are all epoxies equal? For example, does the clear epoxy have the same qualities as the “usual” black COB epoxy?

algofoogle (Anton Maurovic)

Also, are all epoxies equal? For example, does the clear epoxy have the same qualities as the “usual” black COB epoxy?

There are a ton of varieties in the pdf I just posted. Page 22 has a bunch of COB style encapsulants. BGA is also listed so I would assume it's suitable for LGA as well

1

I did a bit more looking and seems like gold wire bonds may be more resilient than aluminium - I don't have experience with gold wire bonds but have seen alu bonds fail after glob top then going through the reflow oven

The plastic encapsulation of "normal" packages ( like QFN and such ) might also provide a lot more protection than whatever the COB process uses, so that could be a difference too

Shall we try to find some packaging expert to consult?

urish

Shall we try to find some packaging expert to consult?

If you know someone, I'm sure we'd love to hear what they have to say

I don't know, but we can try to find (LinkedIn is a good starting point)

1

I want to say that we'll be fine here And the reason this is not seen much in industry has more to do with the fact that low pressure molding has an extremely lower cycle time that is more in line with what packagers are used to and are willing to put up with. They also don't need additional processes like baking or UV treating. Like, if we weren't in the situation we're in and the packagers were willing to work with our quantities we would have a QFN or similar package.

another example https://www.qptechnologies.com/services/ic-assembly/encapsulation-options/

Encapsulation Options - IC Assembly | Services QP Technologies

QP Technologies offers several encapsulation options of your devices, providing the level of protection and/or accessibility that you need.

Semi-related is I wonder how pick and place machine deal with glob top parts ... like would those LGA module work fine or would the top not be flat enough for vacuum pickup and proper placement ...

The biggest tip i have i think would be alright

It also needs to sit flatish in it or it would screw up when it places it I think.

All the encapsulations I've come across seem to self level pretty well. I think it should be alright

Hi all, here's a few pieces of information on COB mfg in case it's useful to the recent discussions going on. It took us over a year to establish a flow that didn't break most of our assemblies :( This was a combination of company negotiation time and lots of surprise temperature incompatibilities.

You will likely find wirebond/COB houses and SMT assembly houses who will each want to do their process first on a bare PCB. I have set up prototyping runs in both situations, and only once found a company that could do both (at higher cost than the two phases individually, unfortunately). I have not gone back to that company because initial project setup took months and over 150 emails. Then that sales engineer retired and I loathed the idea of explaining our assembly to another person. I think they contracted out the COB portion but at least they were responsible for ensuring order of operations.
Advantages to SMT going first: get the high temperature steps out of the way. We were using transparent epoxy that swelled in high temperature, ripping off bondwires. As others have already mentioned, opaque epoxies can generally withstand high solder temperatures.
Advantages to COB going first: wirebond heads work easiest when the bonding surface is flat and there's nothing for the bond head to crash in to. Also they are often attached via vacuum chuck which cannot seal if there are parts on the backside of the board. Custom chucks can be fabricated to enable vacuum seal, at increased NRE cost.
We had some designs packaged QFN but the hassle and cost wasn't ultimately worth it. Packages were not bonded correctly in some cases, with no way to inspect the bonds' correctness via microscope.
COB houses will often require PCBs with ENEPIG or soft bondable gold surface finishes which increase PCB cost and mfg time significantly. Some COB houses are fine with more widely available ENIG but with more risk to yield.

(edited)

1

db

Hi all, here's a few pieces of information on COB mfg in case it's useful to the recent discussions going on. It took us over a year to establish a flow that didn't break most of our assemblies :( This was a combination of company negotiation time and lots of surprise temperature incompatibilities.

You will likely find wirebond/COB houses and SMT assembly houses who will each want to do their process first on a bare PCB. I have set up prototyping runs in both situations, and only once found a company that could do both (at higher cost than the two phases individually, unfortunately). I have not gone back to that company because initial project setup took months and over 150 emails. Then that sales engineer retired and I loathed the idea of explaining our assembly to another person. I think they contracted out the COB portion but at least they were responsible for ensuring order of operations.
Advantages to SMT going first: get the high temperature steps out of the way. We were using transparent epoxy that swelled in high temperature, ripping off bondwires. As others have already mentioned, opaque epoxies can generally withstand high solder temperatures.
Advantages to COB going first: wirebond heads work easiest when the bonding surface is flat and there's nothing for the bond head to crash in to. Also they are often attached via vacuum chuck which cannot seal if there are parts on the backside of the board. Custom chucks can be fabricated to enable vacuum seal, at increased NRE cost.
We had some designs packaged QFN but the hassle and cost wasn't ultimately worth it. Packages were not bonded correctly in some cases, with no way to inspect the bonds' correctness via microscope.
COB houses will often require PCBs with ENEPIG or soft bondable gold surface finishes which increase PCB cost and mfg time significantly. Some COB houses are fine with more widely available ENIG but with more risk to yield.

(edited)

The current plan is that the PCBA house is also doing the wire bonding.

2

Tim 'mithro' Ansell

The current plan is that the PCBA house is also doing the wire bonding.

That would likely solve the availability problems if we end up going with some kind of connector. They would likely offer to stock them hopefully.

But the 150 email nightmare problem is what I'm hoping we can solve

4:10 a.m.

But also why I want to get something actually bonded and such

4:12 a.m.

But I would also guess we are okay with a higher failure rate than industry as well

Probably good to set a numerical target on that

To clarify, the yield risk of ENIG is number of parts successfully assembled --in contrast to flip chip bumps, it's pretty obvious under a microscope if a wirebond doesn't want to stick to its pad. As long as the assembly house notices the failed bond before covering it in epoxy, "low yield" should mean some wasted dice and otherwise a very high percentage of functional assemblies that are shipped back (assuming anything else on the board is assembled perfectly).

@dshadoff - I would say somewhere between 1% and 10% of whole parts.

10:09 p.m.

@dshadoff - Like you if you want 1,000 pieces and I send the board house 1,100 and then you get 100 failures, that seems fine to me.

1

fair enough. Just wanted people thinking about the number.

Hey @tnt I just had a meeting with @peterkinget and @asc and they were telling me about their needs. I have changed the padframe layout a bit and wanted to run it past you. The intent here is for anyone using the 74 pad layout can customize it to their needs, but the actual wirebond layout will remain unchanged between versions. The example here I have your GND pins all tied together and we can also tie together VDD and other nets too if you'd like. @peterkinget I have uploaded the latest versions. The newest padframe footprint is also here. https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/tree/main/scratch/footprints

GitHub - wafer-space/chip-on-board-wire-bonded-pcbs: Wire bonded ch...

Wire bonded chip on board PCB designs. Contribute to wafer-space/chip-on-board-wire-bonded-pcbs development by creating an account on GitHub.

chip-on-board-wire-bonded-pcbs/scratch/footprints at main · wafer-...

Wire bonded chip on board PCB designs. Contribute to wafer-space/chip-on-board-wire-bonded-pcbs development by creating an account on GitHub.

Thanks! We make a pcb rough design and share in the coming days.

2

This is nice @Andrew Wingate

1

@Andrew Wingate Sure looks fine. It's a bit confusing to have the waferspace logo not in the pad 1 corner though no ? (edited)

tnt

@Andrew Wingate Sure looks fine. It's a bit confusing to have the waferspace logo not in the pad 1 corner though no ? (edited)

You are correct. It's an artifact from before I was following your pinout. I had never made a design that didn't have pin 1 at the top before.

Fee free to rotate the die footprint if you want the pin 1 on the top

Haha, sounds good thanks

I think we just used that pin numbering / orientation because the original IHP script in ORFS was using it and so this is what we ended up with.

I understand

@Tim 'mithro' Ansell I figured CS was about to be bugging you for an update so I made this. Then I checked my email. Let me know if there's some other kind of content I can drum up. -# this is meant to look pretty and is not real, but is very close to what the real one could look like. (edited)

Hi @Andrew Wingate, @Tim 'mithro' Ansell , we made a quick design of the DIL version. (Thanks to @asc and Xianglin Pun) Not routed but we wanted to figure out the size. There are 37 pins across now, but we will likely reduce to 34. The vertical dimension might grow a bit in steps of 100mil if we face routing contention at the bottom and top. Let us know what you think. This would be great for our purpose since we can plug it right in the breadboard or custom PCB with headers without needing a motherboard and reflow solder oven. We are happy to share the design once it is done.

peterkinget

Hi @Andrew Wingate, @Tim 'mithro' Ansell , we made a quick design of the DIL version. (Thanks to @asc and Xianglin Pun) Not routed but we wanted to figure out the size. There are 37 pins across now, but we will likely reduce to 34. The vertical dimension might grow a bit in steps of 100mil if we face routing contention at the bottom and top. Let us know what you think. This would be great for our purpose since we can plug it right in the breadboard or custom PCB with headers without needing a motherboard and reflow solder oven. We are happy to share the design once it is done.

Thanks! I know that Tim is wanting a breadboard version so it's good to see one mocked up!

70 pin Mezzanine COB I have a pretty strong feeling this will be one that makes it to the end. If you want a motherboard stick it on there If you want a DIP package stick it on there If you want a breadboardable stick it on there If you want a test board stick it on there If you need revisions stick it on there, revise, then stick it on there If you want other people to design motherboards for you, send them one so they can stick it on there If you're worried about wirebond failures stick it on there and test without worries Side benefits, PCBA house does not need to stock these for you and/or you do not need to ship them to them when you need more motherboards The extra cost will probably be < $0.30 but may be washed out if the wirebond house only has to deal with a single format. If half a run wants COB that's 20k. Setup costs trend towards zero, and 1k chips almost perfectly fit on a 7" reel making a PCB changeout also low/no cost. @db mentioned above that some of the wirebonders use a vacuum chuck to hold the parts. If we think we want to move the bottom traces into an inner layer and accommodate some decoupling we may want to consider that now before tooling is made (even if we never do) Is there anything I missed? @tnt @Tim 'mithro' Ansell @peterkinget @Tholin @asc

Andrew Wingate

70 pin Mezzanine COB I have a pretty strong feeling this will be one that makes it to the end. If you want a motherboard stick it on there If you want a DIP package stick it on there If you want a breadboardable stick it on there If you want a test board stick it on there If you need revisions stick it on there, revise, then stick it on there If you want other people to design motherboards for you, send them one so they can stick it on there If you're worried about wirebond failures stick it on there and test without worries Side benefits, PCBA house does not need to stock these for you and/or you do not need to ship them to them when you need more motherboards The extra cost will probably be < $0.30 but may be washed out if the wirebond house only has to deal with a single format. If half a run wants COB that's 20k. Setup costs trend towards zero, and 1k chips almost perfectly fit on a 7" reel making a PCB changeout also low/no cost. @db mentioned above that some of the wirebonders use a vacuum chuck to hold the parts. If we think we want to move the bottom traces into an inner layer and accommodate some decoupling we may want to consider that now before tooling is made (even if we never do) Is there anything I missed? @tnt @Tim 'mithro' Ansell @peterkinget @Tholin @asc

Nice, is the mezzanine connector polarized? It appears symmetric and could be connected both ways?

12:50 p.m.

If there are retention strength concerns maybe we can design a 3D printed bracket for it.

Jianxun Zhu

Nice, is the mezzanine connector polarized? It appears symmetric and could be connected both ways?

It is symmetric, but there are multiple pin 1 markers. These connectors are quite strong it's the same ones that hold on the Raspberry Pi compute modules. Also these COB are fairly small. I don't think I would worry. But thank you for your input, I plan to create some tests to be sure.

@Andrew Wingate Looks good. One comment (both for LGA and mezzanine), the tracks could probably be thicker for the power pins, there does looks like there is space. I think there should also be space for decoupling in the corners on the top to put a few 1u 0201 there.

tnt

@Andrew Wingate Looks good. One comment (both for LGA and mezzanine), the tracks could probably be thicker for the power pins, there does looks like there is space. I think there should also be space for decoupling in the corners on the top to put a few 1u 0201 there.

Ah, I hadn't considered putting them further out. That could work. Also yes, power pins could be widened. Thank you

12:59 p.m.

@tnt Do you have an idea on how many? I see 8 pins that have power

Andrew Wingate

It is symmetric, but there are multiple pin 1 markers. These connectors are quite strong it's the same ones that hold on the Raspberry Pi compute modules. Also these COB are fairly small. I don't think I would worry. But thank you for your input, I plan to create some tests to be sure.

Could you share the part number of the connector? Thanks

Jianxun Zhu

Could you share the part number of the connector? Thanks

https://www.lcsc.com/product-detail/C19089236.html

HC-PBB40C-70DP-0.4V-02 | HCTL | Price | In Stock | LCSC Electronics

HC-PBB40C-70DP-0.4V-02 by HCTL - In-stock components at LCSC. Price from $0.2912. Free access HC-PBB40C-70DP-0.4V-02 datasheet, Package, pinout diagrams, and BOM tools.

@tnt power traces thickened and 8 decaps added. I also wrote some notes for others if they want to add some kind of components. If bonders want some kind of vacuum chuck, they can provision for components to sit here.

2

1

No notch?

The plan is to have these all v-cut. That makes notches a little more tricky. There are qty(2) pin 1 markers

1

urish started a thread. 2025-10-18 2:09 p.m.

What if you just drill at the edge?

2:10 p.m.

As in adding a large via

We could... I kinda like the golden rocket

You can have both

2:12 p.m.

I was thinking about drilling out just the part that doesn't have the solder mask

The window in the rocket? It's too small.

2:13 p.m.

This entire thing is itty bitty

2:14 p.m.

The vias are the smallest drill without being charged more

The following is my opinion alone Based on notes like above about 150 emails between @db and their wirebonder, this is something we want to avoid. And given the most I’ve seen for passing bond layouts has been glorified napkin sketches. We don’t want to be doing this all the time. The overall layout here has 74 bondpads and 70 pins that can be brought through the mezzanine connector. Again, it’s my suspicion, but keeping things the same will pay in dividends. I think the process looks something like this.

COB PCB

PCB houses already deal with variety, I don’t see why this would be different. The current layout is a 7x6 grid (42) dies per panel. 25 panels is 1050 COB. We will likely share a few basic designs and all most would do is change the silkscreen to their liking. From @Tim 'mithro' Ansell side, he is looking at purchasing 10s of thousands of these connectors making for happy conversations with suppliers. With Crowd Supply’s connections with Mouser, there may be a way to get them to stock the mating components.

Glue and Die Placement

All the die are the same size. If there is a mechanical solution for adding the glue (I believe there is) having the same layout for everything will make them very happy. Cost is inversely proportional to happy. Furthermore, from my estimation, roughly 1k die fit on a 7” reel and the die can likely be placed by standard pick and place machinery, further increasing happiness.

12:30 a.m.

Wirebonding itself

Wirebonding: Like I said above, it seems like wirebonds are identified by napkin sketches. Even moving 1 pad creates 74 unhappys. I am going to go out and and say that in the beginning at least it’s going to be cheaper for someone who only wants 50pins and a 50pin mezzanine ($0.20 cheaper per connector) to actually get all 74 wirebonds even if they remain unused. Vacuum Chuck @db had mentioned above they may—likely—use a vacuum chuck. For our needs they will likely need to create a custom harness, decreasing hundreds of happy every time there is something new. In the design I have allocated a space we can keep clear for any number of components that can fit that area. Stack height can be changed on motherboard side if needed

Goober

Once the wirebonding is completed, the dies need to be protected. There are machines that can place the epoxy. Again, if all the panels are the same, there is no setup cost, increasing happiness. @Matt Venn shared a table in one of his recent videos about where all the cost is compared across different quantities. If there is an LGA version, I suggest it still use the same layout. If @Tim 'mithro' Ansell can get the throughput enough that he’s making runs every week—which would be super cool!!—I bet the cost for this would drop below $0.50 or even less for some variations. Enough happiness to go around.

Just to keep the creative juices flowing, I made a couple examples of motherboards. While I think it would be a squeeze to fit this on a dip with all the pins, if there were less I see no problem working with the .3" space. 70pin DIP does not seem like anything anyone would want anyways. Both have 35 pins on each side. Since we cannot know what the pinout will be from the die, we can't really pour grounds, but would be simple enough for someone to change if they did want it. (I also feel like someone would want to label pins as well?) One is castellated, one is meant to plug into a breadboard and has .5" spacing between .1" headers

@Andrew Wingate looks great! "Since we cannot know what the pinout will be from the die, we can't really pour grounds" Does that mean the current plan is to give each pad a separate pin? I thought, the ring in the image above was a ground ring? Sorry if this has already been answered :)

1

Leo Moser (mole99)

@Andrew Wingate looks great! "Since we cannot know what the pinout will be from the die, we can't really pour grounds" Does that mean the current plan is to give each pad a separate pin? I thought, the ring in the image above was a ground ring? Sorry if this has already been answered :)

No worries. Judging only from the TT layout and the MOSbius layouts they're both using the standard 74 pads on the die. MOSbius wants access to as many pins as possible, while TT wants many more ground pads--and some decoupling. Correct me if I'm wrong, but users can choose to use any pad in any way they wish on the die? Finally, personally. I think that using a mezzanine connector will be a good choice for us all going forward. That leaves 70pins that can make it down to a motherboard. The two projects I've listed here are incompatible and don't necessarily even share the same GND pins on the die let alone what makes it down to the motherboard. I imagine, eventually there will be some conventions which will allow for some standards, but does not seem that we're there

6:55 a.m.

Does that mean the current plan is to give each pad a separate pin?

I think the disconnect may be: Yes, there are 74pads on the COB. But some COB will be unique--but hopefully only on pin/pad signal and routing

ATM the only way to accomodate both is to have different "breakout" ( bonding -> connector ) PCBs. The dimensions of the PCB, connector position and wirebonding plan will be the same but actual traces on the PCB will be different.

1

Thanks for the explanation. So I understand that MOSbius will use a separate "breakout" PCB compared to the default one (TT). This means that they will have to modify any of the motherboards they want to use anyway, in order to pour grounds. But then, why don't develop the motherboards for the default "breakout" PCB in mind?

Leo Moser (mole99)

Thanks for the explanation. So I understand that MOSbius will use a separate "breakout" PCB compared to the default one (TT). This means that they will have to modify any of the motherboards they want to use anyway, in order to pour grounds. But then, why don't develop the motherboards for the default "breakout" PCB in mind?

Correct. I posted the current TT version here https://discord.com/channels/1361349522684510449/1408134567491145728/1429108195506257983 And @xianglin_pu created a derivative version here https://discord.com/channels/1361349522684510449/1429068742108909638/1429520076536811622

1

7:05 a.m.

Also the TT version has 8 1uF decoupling caps

7:06 a.m.

With the intent to future-proof I have outlined an area people can put components and hopefully not interfere with the wirebonders.

Andrew Wingate

Correct. I posted the current TT version here https://discord.com/channels/1361349522684510449/1408134567491145728/1429108195506257983 And @xianglin_pu created a derivative version here https://discord.com/channels/1361349522684510449/1429068742108909638/1429520076536811622

Right! But what I meant, in the example motherboards you posted above, why don't you just pour the grounds for the default breakout PCB? For any non-default breakout PCBs, the ground pours will have to be modified anyways? This way it would be just a bit easier to go the default route, but it shouldn't make any difference for any non-default projects.

Leo Moser (mole99)

Right! But what I meant, in the example motherboards you posted above, why don't you just pour the grounds for the default breakout PCB? For any non-default breakout PCBs, the ground pours will have to be modified anyways? This way it would be just a bit easier to go the default route, but it shouldn't make any difference for any non-default projects.

I guess, there just is no default breakout yet. I may be naive, but I don't think that either are exactly generic. MOSbius is probably closer, choosing to break out more pins instead of ground, but this isn't necessarily true for someone wanting super highspeed differential signals? So I just don't know, and in my not knowing I decided not to make a choice

If anyone wants to suggest a default, I am more than willing to listen. Even if it's allocating certain specific pins to GND? These questions are also why I've been rapid firing different examples and configurations.

7:19 a.m.

In the end, these are pretty generic, and I see people wanting to customize them at least a little bit anyways. Even if it's just to put the project name and version on it.

MOSBius doesn't care about separating IO GND and Core GND because they use neither ... all their pins are analog logic so there is no IO current, they use none of the digital pad at all afaiu.

1

Andrew Wingate

I guess, there just is no default breakout yet. I may be naive, but I don't think that either are exactly generic. MOSbius is probably closer, choosing to break out more pins instead of ground, but this isn't necessarily true for someone wanting super highspeed differential signals? So I just don't know, and in my not knowing I decided not to make a choice

If anyone wants to suggest a default, I am more than willing to listen. Even if it's allocating certain specific pins to GND? These questions are also why I've been rapid firing different examples and configurations.

Well, the choice we had made was the TT padring, since TT has to be fabricated anyway and is reasonably generic as a default padring. It will not be possible to find a pinout that matches every application. (edited)

It's true that TT has probably more than strictly necessary, but I'd rather err on the side of caution. It's also because of the way TT work, our "in-chip" PDN has more resistance than a "normal" chip would have, so one way of compensating for that is to feed it externally at more points.

So when it comes to digital designs, the TT padring is a good default.

I am probably getting a little lost with language. When you say "padring" you're only referring to the pads on the die itself? Or how/where/what signal/power goes to each pad?

7:27 a.m.

-# forgive my ignorance (edited)

7:29 a.m.

The padring is really the ring around your design, which defines the type and placement of the pads.

7:29 a.m.

We've chosen the TT padring as a reasonable default padring.

Leo Moser (mole99)

The padring is really the ring around your design, which defines the type and placement of the pads.

Ok, yes. I am also suggesting that all projects use this padring as default. Anything not this is not default

Therefore, it would be great if the default "breakout" PCB and motherboards could be optimized for that. (edited)

Leo Moser (mole99)

Therefore, it would be great if the default "breakout" PCB and motherboards could be optimized for that. (edited)

I'm all for that too, but am not skilled enough to understand these choices fully

Some numbers I got was 500 mA per bond wire ( for 25u Al wedge bonded) fusing current, so you'd want to stay way away from that, say half. I don't know the short circuit current of the IO but on IHP for instance it's 32 mA, so you'd want like 1 power wire for like ... 8 IOs or so to survive the user shorting all. So for the default frame that has 54 user IO, you'd want at least 6 GND IOs.

2

Andrew Wingate

Ok, yes. I am also suggesting that all projects use this padring as default. Anything not this is not default

Well, yes, they should use the same pad positions and power/ground pads if they want to use the default bonding setup :) The signal pad types can actually be changed and it is still compatible.

1

Andrew Wingate

I'm all for that too, but am not skilled enough to understand these choices fully

That's why I suggested to pour the ground planes for the default "breakout" board, as this is what most people will be using. If you use a non-default "breakout" board, you need to change the ground pours anyway.

2

7:35 a.m.

Great work on the PCBs by the way. I'm really looking forward to seeing all of this coming together!

1

Thanks, please don't hesitate to make suggestions. I often share things before they're pretty to get feedback

1

7:42 a.m.

@tnt and @Leo Moser (mole99) I would like to document this somehow. In the TT layout there is VDD IO PWR Aux and VDD Core These are not tied together on the COB PCB how should they be labeled?

7:42 a.m.

https://docs.google.com/spreadsheets/d/1pI2BAEWEexXcXN3vah3SR85zPIV6eAXPGXc2bcvoSGU/edit?gid=0#gid=0

7:43 a.m.

I made a copy of your document to figure some stuff out when I was trying to make the first PCB

7:44 a.m.

sorry, wasn't shared, it is now

@Andrew Wingate They should not be wired together, they might be at different voltages.

7:48 a.m.

VDD IO / VDD Aux / VDD Core. ( The IO and Core one directly map to the main rings. The "Aux" is meant as bias voltage / aux power for analog stuff ... )

rings

I do not have those rings on the current COB PCB. Should they be added (or at least tie them together on an inner layer?)

As for the naming: At the moment there are no separate IO and Core domain since we don't have the pads for that yet (actually we have them, but they are untested). So for the default wafer.space pinout, all GNDs should be "GND IO/Core" and VDD should be "VDD IO/Core" (even for Aux). This will change in the future once we have separate domains.

they being only VDD IO to the other VDD IO pins?

Oh, if we already do power rings for IO/Core then we can think about keeping the naming

I guess what I'm asking is do we tie them together on the COB, if not, then maybe find different words?

1

Leo Moser (mole99)

Oh, if we already do power rings for IO/Core then we can think about keeping the naming

they currently are not tied

@tnt should there be power rings on the breakout for TT?

I don't think that's really necessary. Traces to the pins are thick, and short decoupling is near. (edited)

1

Just call them out as VDD{i}

They should be tied together on any mother board since you don't want to feed different voltages to them.

8:03 a.m.

Like feeding different voltage to VDD IO and VDD Core is fine, but feeding different voltage to different VDD IO pin is a sure way to obliterate the chip.

I am imagining the default layout also comes with decaps as well. But trying to be forward-looking do you have a suggestion for naming convention?

8:05 a.m.

I'm also content to not change anything and if someone cares enough they can look closer

Well what I said above GND/VDD IO/Core/Aux. (edited)

1

8:07 a.m.

It's true that for the current pads, some are technically tied internally ATM, but in the future they should be split so might as well start with that naming now IMHO.

2

@Tim 'mithro' Ansell There has been significant discussion on what the defaults should be. I have tried to compile the latest/best information I have here https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs Please let me know if there's anything you think should be added.

GitHub - wafer-space/chip-on-board-wire-bonded-pcbs: Wire bonded ch...

Wire bonded chip on board PCB designs. Contribute to wafer-space/chip-on-board-wire-bonded-pcbs development by creating an account on GitHub.

What's the thinking behind the mezzanine connectors rather then bonding directly?

8:52 a.m.

I'm also not seeing info on the connectors in that repo?

8:52 a.m.

@Andrew Wingate -^

Tim 'mithro' Ansell

What's the thinking behind the mezzanine connectors rather then bonding directly?

I have laid out some of the case here: https://discord.com/channels/1361349522684510449/1408134567491145728/1429068742108909638 and here: https://discord.com/channels/1361349522684510449/1408134567491145728/1429265501145534516 A lot of it is logistical. The LGA package can ride along with this as well with no changes. Some back of the envelope math expecting 1000 pcs is: panelized mezzanine cob pcbs would need 25 panels (a stack <20mm high) panelized castellated board from here would need 70 pcbs (a stack ~60mm high) And the last breadboard version would be 170 pcb panels (a stack ~275mm high) We still should see what the wirebonders have to say, but logistically, if we can keep the panels small we get a lot of gains and think they'd be more willing to work with us. Also having a standard that's easily customizable and approachable has some benefits of themselves. Also, good call on the links. I am/was still unsure to lock this in, but sounds good.

@Andrew Wingate - No reason not to put as much information there even if we remove it later.

Are you going to want all that in the CS update?

Say I want the DIP packaging, it seems like I now have to pay for 2 * connectors which adds ~$0.60 to the cost of packaging?

Tim 'mithro' Ansell

Say I want the DIP packaging, it seems like I now have to pay for 2 * connectors which adds ~$0.60 to the cost of packaging?

That sounds true on the surface, but may be washed out by wirebonders pricing. If they have a standard setup and they just crank through these, I bet we can get a significant reduction in the $0.01/wire cost

9:12 a.m.

connector links added to git repo

Tim 'mithro' Ansell

Say I want the DIP packaging, it seems like I now have to pay for 2 * connectors which adds ~$0.60 to the cost of packaging?

Also I don't know where $0.60 is coming from? Any reasonable qty is <$0.35 for the mating connector. The first connector is included in your COB cost. https://www.lcsc.com/product-image/C19089262.html

HCTL HC-PBB40C-70DS-0.4V-2.0-02 Pinout Diagram & Footprint Diagram ...

View HCTL HC-PBB40C-70DS-0.4V-2.0-02 Pinout Diagram and Footprint Diagram at LCSC Electronics. Access precise pin configurations and footprint designs for your electronic components.

$0.30 for connector on the COB side and $0.30 for the mating connector on the DIP package side?

Tim 'mithro' Ansell

$0.30 for connector on the COB side and $0.30 for the mating connector on the DIP package side?

But you have a fixed cost ($1,500) for bonding. The one already fits into that equation.

9:29 a.m.

Furthermore, if there is a true standard, I believe the wirebonders could be more willing to support the people who only want some minimum like (5 panels/ ~250 COB) making it actually cheaper for them

Each 1,000 unit run is pretty much a seperate run as far as the wire bonders are concerned.

9:31 a.m.

It's $1.50 USD per part - with $0.60 going to connectors?

I thought the idea was just to ship the modules to customer, so the mating connectors and the board to put them on would be their responsability so to speak.

That as well

I'm thinking of the person who wants DIP ICs

Tim 'mithro' Ansell

I'm thinking of the person who wants DIP ICs

Furthermore, if someone didn't need as many pins, they could drop down to the 50pin mezzanine connectors dropping the overall cost of connectors by $0.50. I feel very confident in saying that the cost in the end would be comparable (if not less) adding the mezzanine connectors.

9:47 a.m.

hell, you could even just add the dip pcbs with opposing connectors for the same cost giving the benefit of all worlds

Ultimately, I'll do whatever people ask for / want

Of course

@Tim 'mithro' Ansell You can use these when talking to the wirebonders

There might be a min distance for vscoring between edge of connector and edge of board for the blade to go through.

tnt

There might be a min distance for vscoring between edge of connector and edge of board for the blade to go through.

It's .4mm and is already added in

1

Oh wow, they're much better than I though.

Oh you said connector. The v-score is done before PNP at any rate. All clearances have been accounted for though

1

https://www.youtube.com/watch?v=JzdelpyRW9E Wirebonding machine working

Minder-Hightech Guangzhou

Automatic gold wire bonder / Gold wire bonding mahcine

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@tnt and @Leo Moser (mole99) I'm designing all the symbols in kicad I have the COB Wirebond pads -> Mezzanine And then will be making a default Mezzanine -> Motherboard My question is regarding naming conventions for the user pins. Ideally whatever the pins are called in HDL or wherever the original name comes from would be used or whatever label they contain as generic from the default template . I assume this has the 74pad default? Can I get a convention please -# I also understand there will be a TT specific version but would like to make the generic first (edited)

GitHub - wafer-space/gf180mcu-project-template: Project template fo...

Project template for wafer.space MPW runs using the gf180mcu PDK - wafer-space/gf180mcu-project-template

9:00 a.m.

I see the convention starts at index 0 here https://github.com/wafer-space/gf180mcu-project-template/blob/main/librelane/config.yaml

gf180mcu-project-template/librelane/config.yaml at main · wafer-sp...

Project template for wafer.space MPW runs using the gf180mcu PDK - wafer-space/gf180mcu-project-template

Yes it starts at 0 and is usually called pad not pin and 0 is bottom left to match gds orientation

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tnt

Yes it starts at 0 and is usually called pad not pin and 0 is bottom left to match gds orientation

Cool, thanks. So this is what will eventually filter down to the motherboard connector

Looks good to me, the power/ground pads all match up. The naming is different in the template with pad_0 is clk_PAD, pad_1 rst_n_PAD and pad_3 bidir_PAD[0] ... But it wouldn't make sense to use that naming as you are free to change the signal pads in any way you like, and this way is more generic

Leo Moser (mole99)

Looks good to me, the power/ground pads all match up. The naming is different in the template with pad_0 is clk_PAD, pad_1 rst_n_PAD and pad_3 bidir_PAD[0] ... But it wouldn't make sense to use that naming as you are free to change the signal pads in any way you like, and this way is more generic

Thanks, I guess I'm having trouble separating TT specific pin specifiers and what anyone else will do with them. I'll make a TT version that has

ctrl_ena
ctrl_sel_inc
ctrl_sel_rst_n
analog[0]
analog[1]
analog[2]
ui[7]
u_rst_n
u_clk

and so on. But to keep them generic, this is appropriate?

Andrew Wingate

Thanks, I guess I'm having trouble separating TT specific pin specifiers and what anyone else will do with them. I'll make a TT version that has

ctrl_ena
ctrl_sel_inc
ctrl_sel_rst_n
analog[0]
analog[1]
analog[2]
ui[7]
u_rst_n
u_clk

and so on. But to keep them generic, this is appropriate?

To keep them generic for the project template, your previous symbol with pad_0 to pad_69 is fine.

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Ok, made some much more pretty symbols for the COB components. That was not fun trying to unwind the pin numbers and nets.

I don't like that the ground pins are not spaced well. I am going to do some pin shuffling. I plan to move one of the grounds from the pink pin to the green location. @Leo Moser (mole99) or @tnt Are there any changes you'd like to see? Also KiCad allows to have aliased pin names. So I'm going to do that for the TT pins and it all can remain the same symbol. It also allows you to have different electrical properties so I'll fill those in for the people who want to do ERC

Not sure if people know about this other project @Tim 'mithro' Ansell helped to bring us. He helped bring Kicanvas. I have created a link to see these designs in your browser here Thanks Tim, I've used this on a number of occasions!

Andrew Wingate

I don't like that the ground pins are not spaced well. I am going to do some pin shuffling. I plan to move one of the grounds from the pink pin to the green location. @Leo Moser (mole99) or @tnt Are there any changes you'd like to see? Also KiCad allows to have aliased pin names. So I'm going to do that for the TT pins and it all can remain the same symbol. It also allows you to have different electrical properties so I'll fill those in for the people who want to do ERC

I would prefer the symbol on the right, as it resembles the actual positions of the pads in the padring. What is the reason or benefit of the symbol on the left? Too many options might also be confusing. Pin aliases sound great for the TT symbol!

Leo Moser (mole99)

I would prefer the symbol on the right, as it resembles the actual positions of the pads in the padring. What is the reason or benefit of the symbol on the left? Too many options might also be confusing. Pin aliases sound great for the TT symbol!

The one on the left is the mezzanine connector, these are how the signals make it down to the motherboard. I will likely change it a bit then when I get the pin mapping sorted and we can see what we like.

Andrew Wingate

The one on the left is the mezzanine connector, these are how the signals make it down to the motherboard. I will likely change it a bit then when I get the pin mapping sorted and we can see what we like.

Thanks for the clarification, that makes sense :)

@Leo Moser (mole99) The one on the far left would be for someone that wants to design a motherboard for TT COB The one on the right is wild west and the one in the middle is the exact same as the one on the right, but is using pin alias names. Let me know if you want a different arrangement of the one on the left, but all 3 are electrically identical.

I've also updated the example motherboards with the new footprints/pin mappings.

1:42 p.m.

There are some open questions regarding what pins we decide to break out like if we only keep 2 grounds and combine all the power pins on their respective nets we save like 10 pins. Keeping it on the COB itself there are some tight spots (I can do much better, just wanted something now) or we can move to 4layer boards.

For me the power rails could be shorted on the mother board.

1:49 p.m.

Actually it would even be better they are

VDD_IO, VDD_VORE and PWR_AUX?

1:50 p.m.

in the example above each respective is shorted, but all are broken out as well adding to 70pins current schematic

1:51 p.m.

I feel like people will want to make neat boards for TT, but don't know what the demand is, or if these are what anyone would even be looking at.

1:53 p.m.

coincidentally LCSC has just added another even cheaper connector of the same size https://www.lcsc.com/product-detail/C49451471.html

GY972P070 | CHIN-BAN | Price | In Stock | LCSC Electronics

GY972P070 by CHIN-BAN - In-stock components at LCSC. Price from $0.1681. Free access GY972P070 datasheet, Package, pinout diagrams, and BOM tools.

@tnt and @Leo Moser (mole99) I'm working to get some padframe/ cob/ wirebonding standards that will be offered compiled for an upcomming update. Obviously there is the 74pad version with the 70pin mezzanine. I think that's been pretty solidified. I am looking for anything else, and what we think people would want. @Tholin you seem to be the only other one who has expressed interest in another--that being a dip version. Is this what you want? Would you be opposed to having a dip version that looks like these versions above, where the actual dip layout is in fact a carrier? https://discord.com/channels/1361349522684510449/1408134567491145728/1431637886314352834 If we're looking for some other version that would be lower cost, what would you all think of a 50pin mezzanine, this could have 55pads or so? The cost difference from 40pin to 50pin is basically 0, so real difference is offers from wirebonder. Sharing the source and production files will already be done. But also have a relationship to Mouser through CS so if we wanted them to stock panels of DIP carrier boards that fit our to be determined standard I'm sure this is something that can happen if we think there will be some kind of demand. @Leo Moser (mole99) I'm pretty sure there are some other files somewhere that map the config to the actual pad locations. Having another padframe obviously has some overhead, do you want to speak for a second standard? @Tim 'mithro' Ansell your opinions as well?

gf180mcu-project-template/librelane/config.yaml at main · wafer-sp...

Project template for wafer.space MPW runs using the gf180mcu PDK - wafer-space/gf180mcu-project-template

Still a little curious about wirebonder capabilities/ input medium. I found this one by yamaha work area: Width: 20– 95 mm (20–93 mm when carrier type) Length: 95～300mm https://www.youtube.com/watch?v=-43dpkL5N7w

UTC-5000Super | Product Information | Yamaha Robotics Co., Ltd.

The UTC-5000Super is the culmination of a series of high-speed wire bonders. Yamaha Robotics is a turn key provider in the field of semiconductor back-end processing and electronic component mounting.

ヤマハロボティクス公式チャンネル

【Shinkawa】UTC-5000Super（Wire Bonder）

Leo Moser (mole99) started a thread. 2025-10-27 7:30 a.m.

Poor Man's Intro to Bonding: https://youtu.be/_xRH6R4bn-4?si=Rb_vWIx_BTgcD5vM

KiCad

Poor Man's Intro to Bonding | Stephan Bökelmann @ Kicon 2025

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