wafer.space Community

Tim 'mithro' Ansell

@BreakingTaps - That is super cool! Can you publish that somewhere publically?

I'll tidy and throw it up on github this weekend!

5:11 p.m.

(should also note that they failed DRC with a ton of violations, so probably not super reliable results)

BreakingTaps

(should also note that they failed DRC with a ton of violations, so probably not super reliable results)

Will have to figure out how to clean them up.

I'm working on an I/O pad library for 1.8V - 3.6V LVCMOS with adjustable slew and LVDS/CML options. For LVCMOS 3.3V, seeing half-nanosecond edges with 15pF of load; good for >500Mhz using GF's 3.3V FETs. (edited)

5:52 a.m.

Any padrings so far that supported 3.3V I/O?

EmbeddedKen

Any padrings so far that supported 3.3V I/O?

as I understand it, the default padring works fine with 3.3V I/O as long as you're also doing 3.3V Vcore

That's correct, there are even liberty views for ~3.3V.

EmbeddedKen

I'm working on an I/O pad library for 1.8V - 3.6V LVCMOS with adjustable slew and LVDS/CML options. For LVCMOS 3.3V, seeing half-nanosecond edges with 15pF of load; good for >500Mhz using GF's 3.3V FETs. (edited)

What are you working on? LVDS/CML is something that is very interesting to me

- I would to get us to PCIe eventually.

Tim 'mithro' Ansell

What are you working on? LVDS/CML is something that is very interesting to me

- I would to get us to PCIe eventually.

An FPGA with 5V core and 1.8V-3.3V I/O; maybe a test gigabit transceiver for proving out SGMII or PCIe x1 Gen1 physical-layer capability. I think 2.5 Gbps may be almost within the realm of reach for half-rate architecture; solid PLL and CDR would be the limiting factors.

EmbeddedKen

An FPGA with 5V core and 1.8V-3.3V I/O; maybe a test gigabit transceiver for proving out SGMII or PCIe x1 Gen1 physical-layer capability. I think 2.5 Gbps may be almost within the realm of reach for half-rate architecture; solid PLL and CDR would be the limiting factors.

Have you seen https://bit.ly/open-pipe-talk ?

[External Access] SERDES, PIPE and protocols - Pathway to fully ope...

SERDES, PIPE and protocols Pathway to fully open source implementations... Presenters Tim ‘mithro’ Ansell <tansell@google.com> bit.ly/open-pipe-talk

The associated PIPE interface and Hard IP would be quite a technical challenge; possible greater than PMA development

Also have you seen @Leo Moser (mole99)'s FPGA?

6:35 a.m.

@EmbeddedKen - If you get me the SERDES, I can get you the PIPE and reset of the stack

1

I do have a PCIe serial logic analyzer for decoding DLLPs and TLPs; which could help with silicon bring-up and have extensive experience debugging PCIe for FPGAs.

Tim 'mithro' Ansell

@EmbeddedKen - If you get me the SERDES, I can get you the PIPE and reset of the stack

I'll see what I can do- I'm not an analog wizard; I think PLL/CDR will be the most challenging

@EmbeddedKen - @Mehdi and the openfasoc project where working on high quality PLL and CDR structures for SERDES in the past, I have no idea were they ended up getting too. There is some very out of date stuff in https://bit.ly/goog-analog

Google + Analog Handout - Non-confidential -- https://bit.ly/goog-a...

Analog bit.ly/goog-analog

6:38 a.m.

Their general approach was to write generators so they could eventually tape out like 50 variants to find the best solution.

6:38 a.m.

@EmbeddedKen - If we could do the slowest USB3 speed, that would be pretty epic.

One of the first PCIe Gen1 devices was on 180nm- which provides some additional hope. 2.5Gbps is definitely pushing the limits of the process node.

This group is one I know attempting to do some stuff -> https://github.com/chili-chips-ba/openPCIE

GitHub - chili-chips-ba/openPCIE: Peripheral Component Interconnect...

Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource on the Host side too. Our project roots for the Root Port i...

6:40 a.m.

@EmbeddedKen - https://github.com/mithro/open-pcie-status

GitHub - mithro/open-pcie-status: Repo containing an AI generated r...

Repo containing an AI generated report on the status of open source PCIe implementations (for FPGAs). - mithro/open-pcie-status

Tim 'mithro' Ansell

@EmbeddedKen - If we could do the slowest USB3 speed, that would be pretty epic.

I thought SuperSpeed started at 5Gbps... that is probably well out of reach.

6:41 a.m.

Awesome info- I'll dive into these

6:41 a.m.

Amazing to think there's others out there working on PIPE

@EmbeddedKen - But yeah, high performance IO would be a great step, even if initially it starts at like 250MHz and then we slowly improve until we can get the 1.5GHz (or is it just 1 GHz, I've forgotten?) needed.

480Mbps for USB2 HS (UTMI) 1.25Gbps for 1000BASE-X/SGMII (GMII) 2.5Gbps for PCIe Gen1 (PIPE) 5.0Gbps for PCIe Gen2 / USB3 SS (PIPE)

EmbeddedKen

An FPGA with 5V core and 1.8V-3.3V I/O; maybe a test gigabit transceiver for proving out SGMII or PCIe x1 Gen1 physical-layer capability. I think 2.5 Gbps may be almost within the realm of reach for half-rate architecture; solid PLL and CDR would be the limiting factors.

Cool! Which tools are you targeting for synthesis and PnR? FABulous uses Yosys and nextpnr.

@EmbeddedKen But the first PCIe was on a true 180nm right ? Here we only have "IO" device, no real 180nm transistors.

https://docs.google.com/document/d/1ItFfVkK6SQFjOv5kzzwCAq5x_xVZee9zKB7v0VDrYKk/edit?tab=t.0#heading=h.dz6yjd8i5d0

PCIe 2.0 Support Process Nodes

PCIe 2.0 Support From Wikipedia; Intel's first PCIe 2.0 capable chipset was the X38 and boards began to ship from various vendors (Abit, Asus, Gigabyte) as of October 21, 2007. AMD started supporting PCIe 2.0 with its AMD 700 chipset series and nVidia started with the MCP72. All of Intel's prior...

EmbeddedKen

480Mbps for USB2 HS (UTMI) 1.25Gbps for 1000BASE-X/SGMII (GMII) 2.5Gbps for PCIe Gen1 (PIPE) 5.0Gbps for PCIe Gen2 / USB3 SS (PIPE)

Ahh - I always get confused because SATA is 1.5gbit/s which is the first of these "real" LVDS 8b10b protocols if I understand correctly... https://docs.google.com/document/d/1krIVSZw_FwjG7sroVZ3IIVIHmBZ76r8e4mBtlCwJy6k/edit?tab=t.0#heading=h.cec2048bak8g

SERDES Protocol Table

SERDES Protocol Table Protocol Encoding Voltages Serial Interface PPM 8-bit Slow Speed Interface 10-bit High Speed Interface 1 DP AUX 1.0 Manchester 1.0 Mbit/s ±500 1 USB1.1 - Low Speed NRZI ±3.3V 1.5 Mbit/s ±0.25% 6 MHz - 1 USB1.1 - Full Speed NRZI ±3.3V...

11:18 p.m.

Some very old stuff from 2020 around the time released SKY130 - https://drive.google.com/drive/folders/1A6K2b9VFvGC5VRVsnGBQJYwM-L2GsjAI?usp=drive_link

1000BASE-X/SGMII are LVDS 8b/10b at 1.25Gbps. Are SATA III devices able to negotiate down to 1.5Gbps? I've heard there's an additional physical-layer feature called "beaconing" that some transceivers have to support SATA.