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Having an inverter at the output of a logic cell (buffering the internal node) is almost a given, right? So any custom gates in any static logic family I have to draw I should expect to use an inverter as an output buffer after the actual gate itself, right?

Sometimes you'll find _0 variants of gates where it's directly the internal output but yeah that's rate and not that useful for general P&R where you'd almost always have an inverter at the output ... except if the cell in question is an inverter or a delay cell .

1

namibj

Having an inverter at the output of a logic cell (buffering the internal node) is almost a given, right? So any custom gates in any static logic family I have to draw I should expect to use an inverter as an output buffer after the actual gate itself, right?

No. CMOS standard cells have NAND2 and AOI amd OAI cells that don't have inverter at the end and these cells will be used quite a lot in the synthesized netlist.

I just noticed the SRAM behavioral model has timing constraints (55.6 ns, ~18MHz). Do we know if this is a real limit of the SRAM, or just a quirk of the fab's sram model?

BreakingTaps

I just noticed the SRAM behavioral model has timing constraints (55.6 ns, ~18MHz). Do we know if this is a real limit of the SRAM, or just a quirk of the fab's sram model?

That seems close to the 1.8V figures on https://gf180mcu-pdk.readthedocs.io/en/latest/IPs/SRAM/gf180mcu_fd_ip_sram/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/gf180mcu_fd_ip_sram__sram512x8m8wm1.html

8:24 p.m.

So I assume you can safely ignore at 5V or 3v3

aha good catch! Didnt realize the docs had those tables for the sram

8:39 p.m.

thanks!

Does anyone have t_FO4 on hand by chance?

@RebelMike @Leo Moser (mole99) Overdue update to my SCL: non-inverting latches. So you can use those now and drop any inverters you had to place in your design. Always remember to gate-level simulate, there should be no more missing cell models now.

2

Tholin

@RebelMike @Leo Moser (mole99) Overdue update to my SCL: non-inverting latches. So you can use those now and drop any inverters you had to place in your design. Always remember to gate-level simulate, there should be no more missing cell models now.

Awesome, thank you!

Tholin

@RebelMike @Leo Moser (mole99) Overdue update to my SCL: non-inverting latches. So you can use those now and drop any inverters you had to place in your design. Always remember to gate-level simulate, there should be no more missing cell models now.

Opened an open_pdks PR to update the hash: https://github.com/RTimothyEdwards/open_pdks/pull/525