wafer.space Community - [0.5x0.5 changes] 🧵

4:05 p.m.

@RebelMike in regards to the 6 through hold mezzanine gnd pins: does this apply for the quarter slot ? Since I have 2 additional layers I can add to make this a 4 layer PCB, I am thinking I can make these extra layers entirely GND, which would likely give us plenty of ground connection.

but use 6 through holes to provide a good ground connection to each mezzanine ground pin

Do you guys think this would be a bad idea ? Not just asking Mike, anyone else fell free to speak up.

@Essen thank you for working on the 0.5x0.5 design! My first change request is to rotate the whole PCB 180 degrees, so that the pin1 indicator would be in bottom left corner.

I think @RebelMike has already changed the other designs as well to match this. https://discord.com/channels/1361349522684510449/1408134567491145728/1552431619565031635

Lauri

@Essen thank you for working on the 0.5x0.5 design! My first change request is to rotate the whole PCB 180 degrees, so that the pin1 indicator would be in bottom left corner.

I think @RebelMike has already changed the other designs as well to match this. https://discord.com/channels/1361349522684510449/1408134567491145728/1552431619565031635

Thanks, added to the list.

@Andrew Wingate last confirmation: do you still want the 60 pin mezzanine connector ? Because that is going to be by far the biggest change by far and we will be losing some pwr and gnd connections. (edited)

4:32 p.m.

Current list is https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/issues/11#issuecomment-5835719739

RUN-2 Change Requests · Issue #11 · wafer-space/chip-on-board-wir...

There are a number of changes we may or may not be making for the run-2 versions. Current List: All boards 4 layers Location of the pin1 fiducial Globtop bubble fixes No vias/holes/etc. under globt...

@Lauri re: 60pin connector. Last time I looked the 60pin was significantly cheaper This cost must be balanced against different testing boards and would not allow p5p5 cob to be used on the standard motherboards. @Tim 'mithro' Ansell @stuart you guys want to chime in here on an opinion?

RUN-2 Change Requests · Issue #11 · wafer-space/chip-on-board-wir...

There are a number of changes we may or may not be making for the run-2 versions. Current List: All boards 4 layers Location of the pin1 fiducial Globtop bubble fixes No vias/holes/etc. under globt...

1

I don't have a strong opinion tbh

1

Essen

@RebelMike in regards to the 6 through hold mezzanine gnd pins: does this apply for the quarter slot ? Since I have 2 additional layers I can add to make this a 4 layer PCB, I am thinking I can make these extra layers entirely GND, which would likely give us plenty of ground connection.

but use 6 through holes to provide a good ground connection to each mezzanine ground pin

Do you guys think this would be a bad idea ? Not just asking Mike, anyone else fell free to speak up.

I don't know - my feeling is it's not ideal but it's probably fine. If you look at the 1x1 and 0p5x1 you can see the ground through holes are generally close to both a mezzanine ground pin and a ground pad, providing a bunch of really good connections. The 1x0p5 is a lot worse though - I'll definitely be improving that one. The flip side of course is that putting holes in this region is also not ideal but probably fine - so I'll leave it to you and the others on this thread!

1

should have posted here and not in the main channel but for sanity - I've requested a quotation from the supplier for the 60pin connectors

1

HC-PBB40C-60DP-0.4V-02 ：5k Price 0.3277 USD Compared to the 70 pin: 5k pcs: 0.33 USD So no significant difference

1

stuart

HC-PBB40C-60DP-0.4V-02 ：5k Price 0.3277 USD Compared to the 70 pin: 5k pcs: 0.33 USD So no significant difference

Yup, looks like there is no incentive to change the connector. I will assume we are sticking with the 70 pin one.

I'm finding them for $0.10 at low qty https://www.lcsc.com/product-detail/C55111651.html

LXWBB0009P60A | Arrays, Edge Type, Mezzanine (Board to Board) | LXW...

LXWBB0009P60A Arrays, Edge Type, Mezzanine (Board to Board) by LXWCONN. Features 30V and -40℃~+85℃. From $0.1064, 980 in stock. Datasheet available.

Andrew Wingate

I'm finding them for $0.10 at low qty https://www.lcsc.com/product-detail/C55111651.html

Looks like a different manufacturer to me

3:55 p.m.

Interestingly Claude said: On price, the LXW part costs about $0.11 in volume, while the HCTL is about $0.36. The genuine Hirose DF40C-60DP-0.4V(51) is only about $0.38 on LCSC with around 15.8k in stock. So the HCTL clone saves you almost nothing over the real Hirose part.

3:57 p.m.

I'd be hesitant to go for a much cheaper connector without getting some, doing a test batch and inspecting. Seems as though cheaper connectors often have a thinner gold plating but not sure how much of an issue this is

1

@stuart - Maybe we can try some of the cheaper connectors on the designs people are getting free silicon?

Tim 'mithro' Ansell

@stuart - Maybe we can try some of the cheaper connectors on the designs people are getting free silicon?

We can do but keep in mind while using cheaper connectors is easy, changing the board from 70 to 60 pin is some work: board redesign, adaptor for testing, fw for testing, probably other things too. Interested to hear others' opinions about this too

1

Well AIUI everyone with a quarter slot on run 2 is free silicon, so doing something a bit experimental with it is presumably ok. One issue with quarter slot on run 3 is the price of the CoB is almost as much as the silicon, so if that could actually be reduced in some way that would be a good thing. My understanding the way testing is setup is it would just be a different carrier board in the test board, and due to the low number of mating cycles, that board is consumable anyway. (As an aside, if the Hirose part has more mating cycles then for the other boards you might save money using that!) On the other hand, it would introduce complexity and possible confusion, e.g. we’d need different example breakouts and people would need to pick the right one. I could see the quarter slot being different ending up as annoying and it also being slightly unreliable due to the cheap part. Overall if I were you I would probably not want to do it, just to keep things simple, but it depends how much trying to reduce the cost is a factor.

RebelMike

Well AIUI everyone with a quarter slot on run 2 is free silicon, so doing something a bit experimental with it is presumably ok. One issue with quarter slot on run 3 is the price of the CoB is almost as much as the silicon, so if that could actually be reduced in some way that would be a good thing. My understanding the way testing is setup is it would just be a different carrier board in the test board, and due to the low number of mating cycles, that board is consumable anyway. (As an aside, if the Hirose part has more mating cycles then for the other boards you might save money using that!) On the other hand, it would introduce complexity and possible confusion, e.g. we’d need different example breakouts and people would need to pick the right one. I could see the quarter slot being different ending up as annoying and it also being slightly unreliable due to the cheap part. Overall if I were you I would probably not want to do it, just to keep things simple, but it depends how much trying to reduce the cost is a factor.

Also to consider that people may be doing multiple mating cycles after receiving the breakouts boards too. I feel like it would be a shame to ship lower quality boards with lower reliable mating connections for the sake of ~20 cents a board

1

1. As one of the 3 people that has already spent 1.5k USD for getting the run 3 quarter slot assembled I care about YIELD ! The quarter slot assembly cost is the same as all the 1x1 even though there are 18 less wires, making it already the less expensive one to assemble. If this is a question of costs there are other cost factors that do not have any impact on yield that I think should be questioned first: like the decision to go to 4 layers rather than staying on the current 2. 2. As the person making the change, I originally signed up to make some last minute changes and fell blind sighted by this request so late in the development cycle, and so, unlike with my previous change I will not be sending this board for fabrication at my expense to validate it with JLC. Also if I do make the change I will not be maintaining 2 quarter slot versions with the different connector as that is more work that I originally signed up for. I believe other people may also share this felling but might be politer than me and not put it as bluntly. (edited)

stuart

We can do but keep in mind while using cheaper connectors is easy, changing the board from 70 to 60 pin is some work: board redesign, adaptor for testing, fw for testing, probably other things too. Interested to hear others' opinions about this too

Yeap! We would need someone to design the boards, the testing setup carrier and such.

Essen

1. As one of the 3 people that has already spent 1.5k USD for getting the run 3 quarter slot assembled I care about YIELD ! The quarter slot assembly cost is the same as all the 1x1 even though there are 18 less wires, making it already the less expensive one to assemble. If this is a question of costs there are other cost factors that do not have any impact on yield that I think should be questioned first: like the decision to go to 4 layers rather than staying on the current 2. 2. As the person making the change, I originally signed up to make some last minute changes and fell blind sighted by this request so late in the development cycle, and so, unlike with my previous change I will not be sending this board for fabrication at my expense to validate it with JLC. Also if I do make the change I will not be maintaining 2 quarter slot versions with the different connector as that is more work that I originally signed up for. I believe other people may also share this felling but might be politer than me and not put it as bluntly. (edited)

FWIW - We have been using the free designs (that people didn't want more off) on Run #1 to work through the CoB yield issues. People who paid on Run #1 should be getting back the full amount of parts. Run #1 was also a single lot run (and the first time we did things), which made the number of die coming back a bit tighter than I would have liked. There should also plenty of spare die on Run #2 (compared to Run #1) so even if we had a low yield rate means you should be getting back 1,000 mounted parts.

1

2:04 a.m.

@Essen - We also only had one quarter slot design on Run #1 -- so limited number of parts to work with, so it also got left till last.

2:06 a.m.

We also have 9 quarter slots on Run #2 (all of which were provided for free by me), so will have plenty of silicon to test and make sure the bonding for quarter slots is working correctly and make sure that Run #3 people who paid for stuff get back something that is awesome.

RebelMike

Well AIUI everyone with a quarter slot on run 2 is free silicon, so doing something a bit experimental with it is presumably ok. One issue with quarter slot on run 3 is the price of the CoB is almost as much as the silicon, so if that could actually be reduced in some way that would be a good thing. My understanding the way testing is setup is it would just be a different carrier board in the test board, and due to the low number of mating cycles, that board is consumable anyway. (As an aside, if the Hirose part has more mating cycles then for the other boards you might save money using that!) On the other hand, it would introduce complexity and possible confusion, e.g. we’d need different example breakouts and people would need to pick the right one. I could see the quarter slot being different ending up as annoying and it also being slightly unreliable due to the cheap part. Overall if I were you I would probably not want to do it, just to keep things simple, but it depends how much trying to reduce the cost is a factor.

At the moment, it is unclear if there would be a cost reduction by reducing the number of bonds by ~20%

4:23 a.m.

My long term goal is for wafer.space to not be involved with the CoB mounting side of things but still support ordering with your silicon type set up - kinda like getting a stencil from OHS Park.

4:24 a.m.

I'll probably be able to do that when we finally get people like NextPCB to accept CoB as part of PCBA.

1

4:26 a.m.

The only reason I'm doing wire bonding right now is that I refuse to let my customers pay >$10 USD per die to get things packaged -- which is the cheapest quote I got from other groups. (edited)

4:27 a.m.

It would sure suck to pay $2 USD for your silicon and then $10 USD for packaging

1

4:30 a.m.

As of right now, I'm not 100% sure we have gotten to the point of me not losing money on the $1.50 USD packaging.

@Essen - I'm also trying to figure out a way to let people "share" slots while still allowing CoB bonding so that we can do things like put two quarter slots in a single half slot or four quarter slots into a 1x1

I think there's a bit of a disconnect here because:

It sounds like the $1500 cost for CoB packaging was chosen more based on what you thought people could bare, and may not quite cover costs, which obviously leads to you looking for as much cost savings as possible even if that's not evenly distributed between the CoB types
@Essen isn't part of wafer space, so doesn't directly benefit from changes to the CoB that are purely for cost reduction, especially if they aren't going to result in lower prices on future runs. And as she actually paid for quarter slot CoBs on run 3, helping out in this case might actually reduce the quality of the product she bought! (My position is a bit more complex as you've provided me with a bunch of free silicon - I started helping out so I could get some of those chips back, and I'm happy to continue to do so on the basis that will get me some run 2 CoBs back to play with, and who knows it might also bump me up the queue for a free slot on run 3 if you end up with any unbought space... I'd also just like the open source silicon project generally to succeed - which I'm fairly sure is also a motivation for Essen - it's not all purely transactional!)

I think a change this major (switching connectors for cost reduction) should be announced well in advance, so people buying the (hopefully cheaper) quarter slot CoB option know what they're getting (a cheaper, lower-quality option) before they pay. Therefore, I'd suggest we drop the 60-pin idea for now and focus on realistic changes we can actually make at this stage. @Essen re: the 4-layer modification - by my calculation, the cost difference between 2 layer and 4 layer at 1k pcs is 0.015 USD. I think this change is reasonable for improved ground connection and thermals.

1

Also keep in mind a lot of these discussions are somewhat overlapping. While run2 is underway, we have run3 right on its tail, so some interal conversations are overlapping as well. I'm sure you'll be well taken care of @Essen I can't remember the exact quote @Tim 'mithro' Ansell said, but it was something about the permanence of temporary things and your design (thank you again) is in the repo under run2. I think it's unlikely that will change much. (Other than 4 layers/serial#s and small details)

RebelMike

I think there's a bit of a disconnect here because:

It sounds like the $1500 cost for CoB packaging was chosen more based on what you thought people could bare, and may not quite cover costs, which obviously leads to you looking for as much cost savings as possible even if that's not evenly distributed between the CoB types
@Essen isn't part of wafer space, so doesn't directly benefit from changes to the CoB that are purely for cost reduction, especially if they aren't going to result in lower prices on future runs. And as she actually paid for quarter slot CoBs on run 3, helping out in this case might actually reduce the quality of the product she bought! (My position is a bit more complex as you've provided me with a bunch of free silicon - I started helping out so I could get some of those chips back, and I'm happy to continue to do so on the basis that will get me some run 2 CoBs back to play with, and who knows it might also bump me up the queue for a free slot on run 3 if you end up with any unbought space... I'd also just like the open source silicon project generally to succeed - which I'm fairly sure is also a motivation for Essen - it's not all purely transactional!)

@RebelMike - $1,500 USD cost for CoB packaging was set by "vibes" and to specifically set a target that I thought would be reasonable.

9:43 p.m.

@RebelMike / @Essen - If wafer.space is not paying you (including if you only getting free silicon) you are under no obligation to do anything. We definitely appreciate any help the community provides and if you are involved there is also a strong chance that you end up setting the standard and that standards is well suited to your needs.

5

Yes of course, I think we just want to help out where we can

I was just trying to point out that in this specific case motivations might not be as well aligned as usual.