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📐 - Designing / 🕰️-analog
Between 2026-08-31 11:59 p.m. and 2026-10-01 12:00 a.m.
calma on a layout, it says "X problems occured." and these white things show up? It doesn’t happen if I first flatten the layout.
calma command generates this outcropping of nplus that is not present in any way in the mag file, causing DRC errors.
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I × V = I² × R = Power to hit TDP.
You've got closed loop feedback control going on, the process variations of concern shouldn't matter much here, as long as all those fingers see the same usual voltage drop across them.
FC01 (which btw. are not incompatible with performing the classic COB wedge bonding that was done to your accidentally-self-melting-DAC chip):
you could use dual-sided heat sink attachment through thin polyimide and ACF on top and the thinned silicon substrate on the back, and further exploit the current handling capability of the much larger attachment opportunity if you use some extra/bonus high-current pads formed from top metal over the power FET ("circuit under pad").
https://acffilm.com/acf-film.html#acf-cof
E.g. "TCF7040/41 Series" (https://3tfrontiers.com/anisotropic-conductive-film-acf-cof/) seems to be specified for minimum pad area of 1500 μm² and min pad space is 15μm and from what I understand claims <1Ω contact resistance (I'm assuming for a minimum nominal contact; at a 50A/mm² max current density claimed in the datasheet of AC-7206U-18, that'd be <75 mV and <3.75 W/mm² (from contact ohmic heating alone, at such upper-limit levels of current density))...
Don't worry our bond pads are not too small for ACF to work with decent reliability (like, IIRC in practice over 2 nines of yield per foundry pad ring sized bond pad if a small pillar/bump/column is formed; the tape is 10~30~50 μm thick and the bumps need to be a large fraction but less than the thickness of the tape), just the classic chip on flex formulations aren't targeting pad sizes that are closer to face-to-face chip-to-chip bonding (e.g. non-silicon photodiode array or even silicon based avalanche photo diode array, directly bonded to a small-process-node readout ASIC in a "normal [Bi]CMOS process") than purpose designed top metal pads for commodity flex-PCB-DesignForManufacturability.k) action on both parts to verify they're now connected.
If it then works without complaint you know it was the error and can try to snap all associated drawings in the schematic to grid, and clean the "wire excursion to the middle of nowhere" up.
-2 mV/K temperature dependence under vaguely constant current conditions.
So a +- 5 K tolerance for the trip point would only need +-10 mV performance from the comparator and the reference used by said comparator.
I'm not sure but I'd definitely throw the idea of using polyfuses to "remember" a reference "room temperature" and set it up to trip at "room temperature +100C" or maybe "room temperature +75C" for 150/125 degrees Celsius Tjmax self-limiting. E.g. crank the external set resistor from nominal until it trips the mechanism at room temp, then calculate the fuse code for it; or set it up as a shift register to first just feed dynamically to do binary search for what code makes it trip at room temp, and write that; or perhaps literally use a hot box kept at like 115C with a fan force-cooling the chip to near ambient, and do the binary search under those conditions.
In any case, I'd assume there's easy-to-port temperature sensor IP you could readily harness and easily add some such factory calibration/zeroing block to. If it's some kind of digital temperature sensor mechanism, and the temperature sense core itself doesn't depend on a clock, it's probably quite easy to figure out how to plonk it down next to a simple DAC in front of a comparator so that this very DAC could be set to whatever code (+nominal offset that only assumes the scale isn't far off in temp co) trips it under factory conditions. This doesn't _have to be done by external hardware, it could be done on-die at first power-up from just feeding good power and then strapping into factory-cal mode, shouldn't even need a separate clock could just use a fairly trashy ring osc with heavy divider.m multiple parameter instead of physical duplicates.
I'm surprised your extraction doesn't do that already for you.
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(SAM is boring from the software implementation side afaik.)
PU are the same net here; that's gonna extract horribly to spice, just to be aware
control_bench.sch, if that's ok, @Tholin ? 
m is the multiplier. n is the number of finger.
If you have m=2 and W=10u then the effective width is 20u. git apply on the repo btw to apply the patch.
m by 10
CE pulse source to have substantially less transients going on and thus allow larger time steps for covering long time spans with no high frequency activity?
m; much clearer overall and actually should be representative of physical reality because it does cover true length (there are endcap effects going on, that's why it even matters what length they are set to for the sim).
Maybe something something LVS-adjacent can get you such convenient aggregation even across the source/drain ambiguity?
current_ref's CURREF/CTRL/DISABLE. If you don't pull them low they don't leak (nearly as) much.CURREF but the others probably don't need to be capable of sinking current given one of them is a comparator and the other literally just a CMOS buffer 
max(CURREF, CTRL) 
control with an opamp
