wafer.space Community - 🕰️-analog

Has anyone here build an analog-computer? Especially something like a Lorentz-Attractor? And if so, how did you build the sampling? Die-to-Die Bonding to a digital circuit or evaluation by oscilloscope?

there were like 3-ish hours of pause time in the middle as I was on a VC and it was lagging a bit too much.

Stephan Bökelmann

Has anyone here build an analog-computer? Especially something like a Lorentz-Attractor? And if so, how did you build the sampling? Die-to-Die Bonding to a digital circuit or evaluation by oscilloscope?

Yeah, I'm working on an audio FPAA.

We could put converters on board, but right now ADCs/DACs are assumed external for ease/cost/fidelity. I/O is bidirectional analog pins.

1

Archit3ch (George)

Yeah, I'm working on an audio FPAA.

We could put converters on board, but right now ADCs/DACs are assumed external for ease/cost/fidelity. I/O is bidirectional analog pins.

Okay, so when you say audio, you are typically speaking less than 88kHz f_go, correct? Do you have any idea on where I can find good data about die-to-die bonding of higher frequencies?

What is f_go in this context? The pole frequency caused by finite output conductance and the capacitance at that output? No idea. Die-to-die is planned, but no custom bonds, only the mini carrier boards with the default Wafer Space bonding option.

I'm guessing f_g0 ? Cross over frequency ?

I have DAC IP on my run 2 chips that I’ll get to test soon, I hope

1

Archit3ch (George)

Yeah, I'm working on an audio FPAA.

We could put converters on board, but right now ADCs/DACs are assumed external for ease/cost/fidelity. I/O is bidirectional analog pins.

May I ask what you're using for programmability? I happen to have a lot of experience in this specifically

brookieoz

May I ask what you're using for programmability? I happen to have a lot of experience in this specifically

it separates musician controls from correctness:

routing: volatile config bits
configuration: static bits
calibration: DAC trimmers
musical performance: continuous analog CV (lin/exp)

ahh okay it's digital controls

5:50 p.m.

mostly

5:50 p.m.

the lab I was doing research in was using analog floating gates for programmability

1

yeah, i was looking into FG, but decided against it for v1. mostly due to the programming speed

Let me DM you

1

brookieoz

the lab I was doing research in was using analog floating gates for programmability

Georgia tech ICE lab ?

1

9:05 p.m.

Any chance you guys are planning on contributing back the numbers you guys will be collecting into the spice models @brookieoz ?

9:05 p.m.

I don't think anyone actually knows what the expected behavior of floating gates is apart from you guys.

Ah, I graduated in 2023. I haven't touched that stuff for years

9:06 p.m.

Oh, that?

Fun, sorry, I just assumed you where part of the team that took part in run2.

When I was a student I was using FPAAs that were.... I think made in 2014?

1

9:09 p.m.

If you wanted to model analog floating gates you basically use a gigantic resistor to set the DC point and tell SPICE to set that as your initial condition during a transient sim / etc

1

9:14 p.m.

it is a bit risky though, sometimes you get hit with weird simulator errors because it doesn't solve correctly

@Tholin btw, I know you were having sim issue with diodes. I also ran into issues today but looks like there was some diode model rework in latest ngspice main branch and updating to that solved my convergence issues.

I’ve already fixed the problem on my end by eliminating diodes from my schematics

I know, it was just "for future reference"

who sent the NS SAR and the DSM?

Wait a second, my battery charge controller chip is essentially just a linear voltage regulator with a current limiter and control state machine. If you ripped out just the linear regulator part of that, couldn’t you, say, generate a 3.3V core voltage on-die and have a single 5V power supply on a digital chip using my SCL? (edited)

9:20 a.m.

I’d have to measure the dropout on the regulator to see what the true power supply range would be and maybe come up with a way of having a selectable 3.3V/5V IO voltage (though the former would be relatively weak coming from the internal regulator).

The power transistors for this would actually be quite small since the current consumption of standard cell logic, even for a dense 1x1 chip, should be pretty low. I think the full regulator could fit in a corner of the core area without taking up too much space. I’d have to use my run 2 chips to collect more data on my SCL. If the 3.3V is also to supply the IO, it can be beefed up to 1A relatively easily while still not taking up too much space. For reference: my charge controller has a third of a 1x0p5 core area filled with just PFETs and that can conduct 110A according to SPICE. So, yeah, don’t need much FET to get 1A.

9:38 a.m.

@Tim 'mithro' Ansell Is this worth investigating?

If yes, I’ll throw together a 3.3V regulator layout and use some of the unused pads on the charge controller chip to try it.

I think this would be cool - it's a small step from here to a SoC that can run straight off USB (you'd just need a 48MHz clock from somewhere to do data). If you're doing that this offer might be of interest: https://discord.com/channels/1361349522684510449/1361349523724570941/1550939705410064526

What's your voltage reference ?

Bandgap reference

9:56 a.m.

I simulated it across all process corners and varying supply voltages and temperatures and the total error was... I think less than 5%?

9:56 a.m.

I don’t quite remember, I didn’t write the results down.

9:56 a.m.

My SCL is characterized between 3V and 3.6V, so I have +/-10% error target (edited)

1

RebelMike

I think this would be cool - it's a small step from here to a SoC that can run straight off USB (you'd just need a 48MHz clock from somewhere to do data). If you're doing that this offer might be of interest: https://discord.com/channels/1361349522684510449/1361349523724570941/1550939705410064526

There is also a on-die oscillator I am testing on the charge controller chip, over in an unused corner. I have it set to 7.5MHz, but it has no temperature compensation, so it’ll drift a lot. (edited)

10:00 a.m.

How much idk, I’ll just have to test it

10:02 a.m.

I’m not sure I can take advantage of that offer since I’ve already done the top-level layout designed around a 1x0p5 slot. I would have to start completely over with all the layouts except for the analog building blocks to adapt to a different slot size and I just do not have the time. (edited)

Did some testing. You can get 1A with an array of 45 PFETs each 75u wide.

10:11 a.m.

Just quickly generating that in magic, that’s 78u by 144u of area. Could probably shrink that height down a lot.

I quickly put together a schematic for such a voltage regulator. Typical corner 27C: 3.301V ff corner -40C: 3.588V ss corner 125C: 3.014V

10:32 a.m.

Interestingly its perfectly within the +/-10% range

10:33 a.m.

But these conditions are also quite extreme. Especially on the COB boards will die long before 125C and the thermal stresses of cooling to -40C are probably also not going to be kind to it.

10:34 a.m.

At the typical corner on a warm european summer day (40C) it sits at 3.27V, which is definitely good enough

10:35 a.m.

1.5mA quiescent under those conditions

I'm sweeping the temp of the vref alone here and I get from 805 mv to 520 mv across -40 to 120.

10:44 a.m.

so like +14% to -25% (across a very wide temp range for sure).

Right, I specified a much smaller temperature range when I tested it

10:45 a.m.

I think only 0C to 70C

But in the results above you say -40 to 125, so I'm wondering how the output is more stable than the reference it uses.

Oh

10:46 a.m.

No idea

10:46 a.m.

Oh that’s... not right

10:49 a.m.

Okay, maybe simulating a load and decoupling capacitor outside the chip is a good idea

10:49 a.m.

That fixes things right up

10:50 a.m.

And all is as it should be

Tholin

@Tim 'mithro' Ansell Is this worth investigating?

Yes, internal regulators / supplies are still very much needed. Would be even better if they had a on/off switch.

RebelMike

I think this would be cool - it's a small step from here to a SoC that can run straight off USB (you'd just need a 48MHz clock from somewhere to do data). If you're doing that this offer might be of interest: https://discord.com/channels/1361349522684510449/1361349523724570941/1550939705410064526

I would like to see an internal 48MHz oscillator that feeds a PLL which uses the internal oscillator as the reference and trims using the USB data signal.

Tholin

Just quickly generating that in magic, that’s 78u by 144u of area. Could probably shrink that height down a lot.

Uhhhhhhhh Is that at weak hot corner? with anything that's passing a decent amount of current you're gonna have to worry about metallization resistance and electromigration

brookieoz

Uhhhhhhhh Is that at weak hot corner? with anything that's passing a decent amount of current you're gonna have to worry about metallization resistance and electromigration

I'm very unclear what type of timeline things like electromigration happen and if it matters for people who are only doing thousands of units with limited expected lifetime rather than hundreds of millions that need to have work for 30+ years.

Well, I agree that it's of less risk mostly because the stakes are a lot lower, but if you're not careful it can still bite you as EM is accelerated exponentially with increasing temperature, and poor power FET layout can encourage hotspots that make this failure more likely to happen

I think I’ll make my prototype voltage regulator without worrying too much about hotspots. As long as it survives a few hours on the bench testing it, we can decide if its worth putting more time into developing further.

1

My voltage regulator isn’t perfect and the output voltage is slightly dependent on the input voltage. I think this is because my voltage reference is not the best, but I don’t know how to improve it.

I think this is a good enough compromise. The output voltage stays within 3.3V +/-10% as long as the input voltage stays within 5V +/-15%

1:50 p.m.

If this voltage regulator is intended to drive my 3.3V SCL, this is acceptable, as it is characterized over a 3.3V +/-10% range

1:51 p.m.

Like, I do hope nobody expected a perfect LDO with tight margins on this process node with this little dev time.

1:52 p.m.

@Tim 'mithro' Ansell I added the requested enable input. When low, the output completely floats. I hope this is what you meant.

Tholin

I think I’ll make my prototype voltage regulator without worrying too much about hotspots. As long as it survives a few hours on the bench testing it, we can decide if its worth putting more time into developing further.

Release early, release often

Tholin

My voltage regulator isn’t perfect and the output voltage is slightly dependent on the input voltage. I think this is because my voltage reference is not the best, but I don’t know how to improve it.

that's quite a large change in output, indicating poor PSRR What's the PSRR on your voltage reference and what's the gain & PSRR on your amplifier? (edited)

Tholin

If this voltage regulator is intended to drive my 3.3V SCL, this is acceptable, as it is characterized over a 3.3V +/-10% range

also, how much does this voltage droop when you actually start driving a load? from both a DC point of view and transient point of view?

My voltage reference has bad PSRR

Oh hey, this is better!

2

8:42 a.m.

I think THAT I can call good enough. Well within spec.

Do you have a reference to a paper or design for your voltage reference ?

11:38 a.m.

I'm looking at it and although it looks like a classic basic cmos bandgap, that circuit relies on the ratio of resistor and diode to make it work ... but your resistors are the same sizes and your diodes are the same size.

I tried playing with their values, but it doesn’t change how it behaves

tnt

I'm looking at it and although it looks like a classic basic cmos bandgap, that circuit relies on the ratio of resistor and diode to make it work ... but your resistors are the same sizes and your diodes are the same size.

a widlar bandgap?

12:17 p.m.

classic CMOS bandgaps should have a magic voltage around 1.2V

12:19 p.m.

actually yeah wait a second that's really odd, the reference is 0.7V?

Look at this. Maximum output is 0.698V, minimum is 0.685V. The difference is just 0.013V, or less than 2% drift. Probably not an ideal PSSR, but I think my opamp is the bigger culprit here.

12:28 p.m.

Like, having designed these circuits, I am way more suspicious of that jank opamp than the voltage reference.

12:29 p.m.

How do I set up a temperature sweep with ngspice? I can try that too. (edited)

dc temp -20 125 5

12:31 p.m.

Did you change your vref compared to what's in https://github.com/AvalonSemiconductors/ws-charge-controller/tree/main/analog/xschem ?

I don’t think so

12:33 p.m.

Let me check

Ah no nm, I was sweeping from 3.0v to 5.5V not 4.5V to 5.5v

Ah. For the application I’m using this in, the supported supply voltage range is only 4.5V to 5.5V

Tholin

Look at this. Maximum output is 0.698V, minimum is 0.685V. The difference is just 0.013V, or less than 2% drift. Probably not an ideal PSSR, but I think my opamp is the bigger culprit here.

Your output PSRR should be boosted by the gain of your amplifier provided it's within the bandwidth of the amplifier But if it's shifting by about 4% per volt that's uhhh, a PSRR of about 30dB? (0.2V output drift is about 6%, subtract the 2% from your reference drift) (edited)

Decreasing the width of D1 from 5u to 2.5u makes the output a few percentage points more stable with changing temperatures. First thing I’ve found so far that has helped.

12:43 p.m.

The upsetting part is that any change to the reference voltage means I need to go back and edit resistor ratios all over the chip.

I can not get it to look better than this :/

12:56 p.m.

I think I’m just gonna have to do the one diode change, trim all my resistors and accept it as it is

12:56 p.m.

I just do not have the time

12:57 p.m.

On November 20th - 22nd, I host an event and there is so much prep work I still gotta do until then, and if you eye your calendar, you may notice how little time there is between then and submission deadline as well. So, yeah, I’m finishing this today.

Tholin

I can not get it to look better than this :/

You need a lot more PTAT resistor also I looked at the circuit, uh, I don't see how the core is generating a PTAT current at all

Tholin

I have DAC IP on my run 2 chips that I’ll get to test soon, I hope

Also Matt's DAC+Sine generator on one of the Run2 TT's

Tholin

Wait a second, my battery charge controller chip is essentially just a linear voltage regulator with a current limiter and control state machine. If you ripped out just the linear regulator part of that, couldn’t you, say, generate a 3.3V core voltage on-die and have a single 5V power supply on a digital chip using my SCL? (edited)

Yes.

Tholin

The power transistors for this would actually be quite small since the current consumption of standard cell logic, even for a dense 1x1 chip, should be pretty low. I think the full regulator could fit in a corner of the core area without taking up too much space. I’d have to use my run 2 chips to collect more data on my SCL. If the 3.3V is also to supply the IO, it can be beefed up to 1A relatively easily while still not taking up too much space. For reference: my charge controller has a third of a 1x0p5 core area filled with just PFETs and that can conduct 110A according to SPICE. So, yeah, don’t need much FET to get 1A.

Imagine it living in the spare area of a VDD pad cell...

brookieoz

Uhhhhhhhh Is that at weak hot corner? with anything that's passing a decent amount of current you're gonna have to worry about metallization resistance and electromigration

I think the half volt of AFAIK expected channel drop (under typical operating conditions during the charging while current limit is dominating over voltage limit) to be more an issue thermally than electromigration effects there. The metal traces are also fairly supple, iirc I did a lil math on them and determined their resistance to be tiny even at rather local (single-finger) scale.

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3:35 a.m.

We'd need to make flip chip bond pads work and teach it how not to commit self-melting (limit current as it begins to attempts to commit self-melting) to unlock enough amps to where I'd begin to worry about electromigration. @Tholin would you be open to including flip chip power FET pads if the ACF flip chip tests work out?

brookieoz

You need a lot more PTAT resistor also I looked at the circuit, uh, I don't see how the core is generating a PTAT current at all

If you can design a schematic that does much better in not more than like 5x the area, with not substantially higher device count, we'd be happy. I'm not sure about the demands regarding low power/efficiency though.

namibj

If you can design a schematic that does much better in not more than like 5x the area, with not substantially higher device count, we'd be happy. I'm not sure about the demands regarding low power/efficiency though.

7:15 a.m.

the startup might leak a little at high temps

7:15 a.m.

but it's the simplest way to do it that I can think of

brookieoz

Click to see attachment 🖼️

fyi native VT devices are nowt allowed to be particularly narrow due to DRC (technically that'd be ERC but they call it DRC and they treat it as if it is)

oh and there should be an enable switch on the tail current too

brookieoz

oh and there should be an enable switch on the tail current too

the tail resistor?

1MOhm resistor connecting sources of the native vt input pair to GND

7:17 a.m.

yeah

https://github.com/AvalonSemiconductors/ws-charge-controller/blob/main/analog/xschem/voltage_ref_bench.sch

ws-charge-controller/analog/xschem/voltage_ref_bench.sch at main ·...

AIO charge controller and overdischarge protection IC for Li+, LiFePo, LTO and Na+ cells on wafer.space gf180mcu - AvalonSemiconductors/ws-charge-controller

7:19 a.m.

this should bench in a compatible way if you'd swap out the contents of the schematic for this circuit instead. I could look at it in maybe a day if I pace myself well, gotta sleep and do some bookkeeping first.

7:20 a.m.

can you reason the choice of native VT nmos, please?

at the moment I don't have any toolflow set up, it'll probably take me quite some time to get that working

brookieoz

at the moment I don't have any toolflow set up, it'll probably take me quite some time to get that working

oh sorry

7:21 a.m.

(I just use the IIC-OSIC container tbf....)

7:22 a.m.

I think the nix flake in the repo should also work

7:24 a.m.

hmmm I guess even with like -250 mV threshold voltage corner on it it should be fairly off once the source node of it gets to around 650 mV.....

7:25 a.m.

(I misread it also, it says min width so yeah that's not a problem, and 5 length is fine under the DRC and such)

namibj

can you reason the choice of native VT nmos, please?

It's important for a couple reasons: 1 - startup native vt device creates a current that shuts itself off once the bandgap starts up, causes the right side VBE to go up first. That creates a voltage delta in the amplifier 2 - the amplifier needs current otherwise it doesn't do anything, tail resistor with negative VTH means I don't need some kind of NMOS turnaround mirror. And the current is pretty stable because it's roughly always 0.5-0.6V 3 - amplifier input common mode voltage is quite low and to keep things simple I want NMOS input with PMOS mirror with PMOS CS output to reduce systematic mismatch from different Vds on input pair 4 - native VT devices typically match a lot better than full VT devices, important when it directly impacts bandgap voltage

also just fyi there's no degrees Kelvin....

namibj

hmmm I guess even with like -250 mV threshold voltage corner on it it should be fairly off once the source node of it gets to around 650 mV.....

at high temps the VBE goes down and the VTH goes down as well, the leakage will get pretty bad eventually

note that the threshold voltage by process is fairly wide and kinda symmetric around 0V for nvt-nmos on gf180mcuD

that should be fine, you get a decent amount of sub threshold current at -0.1vgst

namibj

also just fyi there's no degrees Kelvin....

?

brookieoz

at high temps the VBE goes down and the VTH goes down as well, the leakage will get pretty bad eventually

could you use the output voltage to trip some turn-off/gate in the startup current path?

brookieoz

?

unlike celsius and fahrenheit, there's no degrees for Kelvin, just like there's no degree volts.

namibj

could you use the output voltage to trip some turn-off/gate in the startup current path?

the easier way to fix it is to connect the source to partway up the RPTAT link

7:31 a.m.

that way you get more negative VGS to shut the device off

1.53M resistor is ... large. Best we have is 1k/sq

tnt

1.53M resistor is ... large. Best we have is 1k/sq

and 1u wide; but the space isn't quite as harsh thankfully at least

With 1um min width. So that's 1530 um length.

Oof.

7:32 a.m.

I'm surprised 1um is min W on the resistor, that's gigantic for a 180nm process (edited)

ehhhh it's not thaaaat huge, like a 50um square should cover it

If you're ok with spending current you can cut all the R's proportionally

only for the high sheet R; normal poly resistors are less than 400

Yeah, I think multiplying the current by 10 is fine.

1

7:33 a.m.

This is 2000's tech, not latest ultra low power

tnt

Yeah, I think multiplying the current by 10 is fine.

I wish I could do that at work

I mean it's a battery charger doing some sort of deep discharge cutoff action as part of it's job.... I'm not too up to date on the other sources of passive draw in "idle" but yeah.

7:35 a.m.

when intel used this class of process they didn't sell more than one core per socket to anything vaguely consumer

Sidenote I might've hooked up the polarity of the amplifier wrong, I didn't pay too close attention to it

they might not have been doing any multi core at all

The startup needs to be on the side that tries to pull the output device on

but the drains and gates as such are going the correct polarity?

7:38 a.m.

@brookieoz btw, do you happen to have any "easy" way we could put a temperature sense into the middle of the power pass FET to implement a temperature limiting behavior that just turns the output current down with more authority than the voltage target can turn it up, if the area gets toasty?

hm

7:40 a.m.

Give me a sec

7:41 a.m.

Well

7:41 a.m.

man, that's a bit of a cursed idea

IMO I'd be aiming for a junction temperature actuation range of 100 to 120C, if accuracy reasonably requires notable margin I'd be willing to go down to about 5C wide actuation band with upper and lower margins allocated as best; I am pretty sure I'd be up for doing e-fuses to trip the trip point in if it's easy to set up some way of measuring on some kind of test pin what the natural trim condition is and thus what fuse pattern to blow

Oof

though all I really care about is that the chip can be used as a charge controller for this with the current limit set as open as the connected battery will be happy with and the power current bonding solution allows

How much area are you willing to spend on it, and how much accuracy do you absolutely need

if that means to need to use a few efuse bits so be it, we do now know they work and they're not large and not particularly hard to use either, and I think they are actually usable for analog purposes even though I'd have to check and confirm. Worst case they could only drive a DAC, I guess.

brookieoz

How much area are you willing to spend on it, and how much accuracy do you absolutely need

enough accuracy to not waste tons of thermal headroom just to keep the unlucky corner from melting itself if someone throws a wool sweater over the charger on say a nightstand or something

7:46 a.m.

areas wise there's a decent bit to spare, 100x100um are a no brainer, 10x that is probably argu-able especially if it would somehow also unlock extra voltage set point accuracy

7:47 a.m.

current set point is AFAIK no need to be that tight given the kind of charging task this kind of charge controller reasonably performs

namibj

enough accuracy to not waste tons of thermal headroom just to keep the unlucky corner from melting itself if someone throws a wool sweater over the charger on say a nightstand or something

so basically you have two approaches: 1: buffer the bandgap voltage and compare a scaled version of it to the VBE of a diode temp sensor 2: make a PTAT current loop at the center of the power FET and compare that with the CTAT VBE of a diode sensor at the same location

the only cheap way to get real good voltage control though I've seen so far in LDOs is to have a factory trimmer DAC inside and use the set resistor just to feed an ADC that then tells the trimmed DAC which of a dozen or so of tabulated charge end voltages to aim for.

1

1 is usually easier to do because you typically have that already on the chip, but it's less accurate 2 is more accurate but it has its own complications

as long as the large-ish resistors don't need to be in the middle of the power FET structure some bipolar's for PTAT/CTAT shouldn't be a problem, I think

7:50 a.m.

but like, I dunno that well

one complication with approach 2 is that you can't really guarantee you have 0 temperature gradient, and that can cause your PTAT to do all sorts of weird things

also we don't need to truly measure we just need to start throttling down over a wide enough temperature range to not cause any too high frequency thermally-coupled oscillations in charging power, and throttle to close enough to zero current before the power fet gets so hot that the chip burns out in like less than 5 years of being "plugged in", usually

it's of particular concern if you have a fault condition that causes sudden power draw where you definitely will have a temperature gradient

oh yeah the only think I can reasonably promise is that the center is gonna have approximately average temperature, and under reasonable conditions not too much delta to the hottest

7:53 a.m.

IMO tbh bonus points if the measurement solution somehow allows having a few smol sensors spread about in a grid pattern and perform some osrt of soft-max by way of how it works

namibj

also we don't need to truly measure we just need to start throttling down over a wide enough temperature range to not cause any too high frequency thermally-coupled oscillations in charging power, and throttle to close enough to zero current before the power fet gets so hot that the chip burns out in like less than 5 years of being "plugged in", usually

Hmmm if you want to really do like granular temp sensing you basically just need an ADC

I think the diode approach would do that but not so sure about how strong the soft-max effect would turn out to be

Just shove a IZTC into a diode and measure the voltage using an ADC

brookieoz

Hmmm if you want to really do like granular temp sensing you basically just need an ADC

oh no not granular as such, just soft enough action to not form a relaxation oscillation through a temperature reservior

oh

7:56 a.m.

I mean if you really think about it you basically need to just guarantee that the system is stable, where your dominant pole is the low pass filter created by the thermal mass and self-heating

7:57 a.m.

modelling that isn't easy tho

might have to set the trip point through some fuses I guess? Just because e.g. 10% of absolute temperature is already about as wide of a range as we'd probably like to concede to the entire scheme; +-2% would probably be desired and if that already needs efuse bits going to +-1% would probably be taken.... like, the latter is still a 6 degree C wide band

brookieoz

modelling that isn't easy tho

hence me hoping to get by with sufficciently little gain from delta-T to delta-current and thus delta-power

8:01 a.m.

figured you might know of some reasonable ways thermal self protection that is allowed to be relied on/hit in regular sustained operation is practically done for LDOs these days; thus figured I might ask

8:02 a.m.

(I have to go catch some sleep though in a couple minutes so will read what you thought of later, other than maybe a few more words in a few minutes.)

my initial thoughts are if you,re looking for like a smooth control you could consider something like make an amplifier that compares a temp sensor diode compared to a scaled bandgap voltage, and output some kind of control voltage that limits the current

8:05 a.m.

but it's pretty hard to really go through it all without intimate knowledge of the control loop of the charge controller

8:06 a.m.

If it's just an LDO with a current limit, then yeah you could probably tune it in a way to reduce the current limit with the result of the amplifier

8:07 a.m.

but it really should be designed in tandem with the LDO, you don't want to end up introducing unintended stability issues (since you are introducing a new feedback pathway at the end of the day) (edited)

namibj

XR8, XR6, XC1, FILT, TRIG.... what's that for?

@brookieoz for up-to-date you'd have to open the repo with xschem pointed at the PDK's symbols

8:09 a.m.

though I mean you'd see the hirarchical blocks without the PDK

I'll be entirely honest I'm not sure how much direct contribution i can do considering I do work in analog IC design

it's not my design. I'm just trying to help make it be good enough to where I'd actually wanna use any of the dies for even hobbyist "production"

brookieoz

I'll be entirely honest I'm not sure how much direct contribution i can do considering I do work in analog IC design

primarily in terms of wisdom

and idk how my employer may feel about it, and I'd rather err on the side of caution and be more of a consultant than a direct contributor

I mostly refer the xschem/repo because it's much nicer to look at if "highlight net" works than if it's just a deck of PNG's

1

8:15 a.m.

prior to realizing your level of skill I felt a little bit towards "if you can demonstrate that it actually as a schematic massively beats the existing in temp co (well, lack thereof!), I'll offer to see to get layout/routing done for it if tholin doesn't get to it first", but given your level of wisdom in the matters, that's not really something to ask for anymore. Can just let you communicate in the most convenient way for you if it's not actively severely inconvenient for me to follow.

1

I should also be headed to bed too, the only reason why I'm awake is because I woke up feverish in the middle of the night and I can't fall back asleep hahaha

nini

namibj

We'd need to make flip chip bond pads work and teach it how not to commit self-melting (limit current as it begins to attempts to commit self-melting) to unlock enough amps to where I'd begin to worry about electromigration. @Tholin would you be open to including flip chip power FET pads if the ACF flip chip tests work out?

No. I’m done updating this chip. Its done.

brookieoz

Click to see attachment 🖼️

All BJT PCELLs in gf180mcu appear to be low-voltage devices only. Not sure this will work at +5V supply voltage. The densest resistors you can get are 1K/um, so 1.53M would be a long boi. 1.53mm. Not impossible, mind you, just taking up an uncomfortable amount of space.

Tholin

All BJT PCELLs in gf180mcu appear to be low-voltage devices only. Not sure this will work at +5V supply voltage. The densest resistors you can get are 1K/um, so 1.53M would be a long boi. 1.53mm. Not impossible, mind you, just taking up an uncomfortable amount of space.

...? The BJTs never see more than VBE across them (like max ~0.8V in cold corner) You don't need to make a single resistor 1W/1530L, you break it up to like say 85L and put 18 links in series (edited)

I’m aware, but that’s still a lot of area

and buried in the discussion up there is that you can definitely cut down significantly on resistor area if you're willing to burn more power

9:04 a.m.

The bias currents are pretty low at approx 0.3uA per branch, if you 4x that to 1.2uA you can cut all resistors by 4x

9:05 a.m.

so the unit resistor ends up around 1/21, and 18 links of that is roughly 400 um^2

@brookieoz BTW, shouldn't that ln(4) be ln(2) if you're using only 2x size ratio ?

tnt

@brookieoz BTW, shouldn't that ln(4) be ln(2) if you're using only 2x size ratio ?

It's 4 The resistors are also ratioed 1:2 so it splits the current unevenly

Oh I see.

You could also try a 1:3 resistor ratio to get ln(6)

9:11 a.m.

and adjust everything accordingly to get the correct amount of PTAT to CTAT

9:11 a.m.

But it's easier to match a 1:2 ratio

brookieoz

...? The BJTs never see more than VBE across them (like max ~0.8V in cold corner) You don't need to make a single resistor 1W/1530L, you break it up to like say 85L and put 18 links in series (edited)

yeah don't worry I have zero worry about lifetime for the design you proposed, we don't even have SPICE for the thin oxide nvt anyways and a bunch of that chip uses structures that I'd not reach for thin oxide structures for anyways.

tnt

@brookieoz BTW, shouldn't that ln(4) be ln(2) if you're using only 2x size ratio ?

why would I want the ln(6) unlocked from a 1:3 ratio?

namibj

yeah don't worry I have zero worry about lifetime for the design you proposed, we don't even have SPICE for the thin oxide nvt anyways and a bunch of that chip uses structures that I'd not reach for thin oxide structures for anyways.

6V natural device should be fine tbh. If you do 3V you'd need to protect the input pair with a cascode which... Actually that's pretty convenient, 6V natural device cascode from the bandgap / output voltage (edited)

namibj

why would I want the ln(6) unlocked from a 1:3 ratio?

You get more PTAT so you can have smaller ratio between the dVbe/R resistor and the PTAT resistor, so you should be able to use a smaller PTAT resistor size (edited)

Hmmm....

It's not uncommon to get ln(8), usually done by having an

AAA
ABA
AAA

pattern for your diodes/bjt's (edited)

Ohh nice, I guess the substantially smaller resistors would help here due to the poor high sheet poly density we got?

But BJTs tend to be pretty big in size and I wasn't sure how much area I had

Yeah fair (edited)

namibj

Ohh nice, I guess the substantially smaller resistors would help here due to the poor high sheet poly density we got?

yeah probably Heck, the normal poly / unsalicided resistors might be better for density

brookieoz

yeah probably Heck, the normal poly / unsalicided resistors might be better for density

Sadly not really at the end

1

6:16 p.m.

Not by much though

brookieoz

It's not uncommon to get ln(8), usually done by having an

AAA
ABA
AAA

pattern for your diodes/bjt's (edited)

This looks like it might work better inside a power FET as a temperature sensor?

namibj

This looks like it might work better inside a power FET as a temperature sensor?

The risk is temperature gradients

brookieoz

The risk is temperature gradients

But they'd balance across it, wouldn't they?

6:19 p.m.

I mean with very good top side cooling you could have the center notably colder than the outside, I guess....

It's mostly that like, say if you suddenly draw a lot more power through your power FET, that'll create a sudden temperature transient that takes time to propagate to your temp sensor, and if you're trying to protect the device from damage you want to catch that as quickly as you can

6:22 p.m.

Fault conditions and such

6:25 p.m.

It's especially problematic if you're operating the power FET in the negative tempco region where the drop in local Vth due to localized heating ends up increasing the local current instead of reducing the current from reduced carrier mobility, because in that region it's unstable and forms localized hotspots that can reach a far higher temperature than what you see at the sensor location

TIL native Vt

brookieoz

Fault conditions and such

Hmmm, speed limiter for upwards delta-power....

Archit3ch (George)

TIL native Vt

I personally really like native Vt devices. But you do have to be careful with them lest you create massive leakage issues

brookieoz

I personally really like native Vt devices. But you do have to be careful with them lest you create massive leakage issues

and you said they're not available in Wafer Space?

Archit3ch (George)

and you said they're not available in Wafer Space?

The 6V natural devices are documented in the open source pdk, I didn't see any 3.3V ones

brookieoz

The 6V natural devices are documented in the open source pdk, I didn't see any 3.3V ones

yeah, but no noise profile, so it's a bit of qualification risk... i'll drop this conversation thread here and let you both design

....a longer term project of mine I thought would use SiC JFETs who's gate source junction under forward bias is a really good temperature sensor about a channel thickness away from the channel itself was planned to use that to contain faults with coordinated emergency SCRAM's (it's a 10~30 kV to about 2~3 kV bidirectional converter aiming towards about a MW but a PoC would be built smaller power if just for parts costs; the dies are only rated 1200 or 1700 V!), but they are all really high ohmic losses in the gate wiring presumably for avalanche proof behavior under cascode operation (if the drain leaks enough into the gate to turn the channel on before breakdown leakage through the reverse junction itself causes local damage, it's safe until the channel melts which takes literally several microseconds and thus easily several PWM cycles, so plenty of time to react and a brief transient is harmless), so I've pivoted to (ideally GaN V-JFETs if there are any smaller than 50$ a die with purchase limits of like one tray a month) likely epc-co GaN e-mode lateral MOSFET-substitutes which happily work at 50 MHz if you regeneratively/resonantly charge the gate and don't turn the channel on while there's drain voltage (output stored energy limits reasonable hard switch frequency to around 3 MHz typically for them) which sadly lack a thermal sense at the channel are not avalanche proof and who's gate is about 3x more finnicky than the SiC JFET (from formerly UnitedSiC). After my SerDes efforts I hope to get to mod a microwave oven to use such a topology of likely 200/300 V epc-co devices to feed the magnetron with regulated DC of about 2kV from probably around 250~300 V nominal LiFePO4 battery backed "DC microgrid" that is also easily digestible by most computer PSUs and I think many induction stove tops and such. I'm actually planning to use wafer.space to make an active digital pre-distortion driver for these power transistors that can talk with a central controller via (very short) fiber optics as it operates floating with severe switching transients (well, I expect around 20V/ns as "regular") and still has to coordinate for possible SCRAM. It's switched capacitor technology using just enough inductance to not need to turn channels on with notable drain voltage remaining. Oh, and poly-phase architecture allows it to neutralize ripple at the DC inputs and outputs greatly reducing the blocking demands put onto the EMI filters because if you have 1kW of e.g. 27 MHz "RF" power in the switched capacitors going down to micro watt levels of radiated leakage externally is... Hard.... If you try to maintain appliance-level 99% efficiency (if it was just a DC/DC transformer not a microwave with it's horrible magnetron).

brookieoz

The 6V natural devices are documented in the open source pdk, I didn't see any 3.3V ones

They are legal. They haven't been measured yet. I'm getting some onto Run3 to get measured.

2

namibj

....a longer term project of mine I thought would use SiC JFETs who's gate source junction under forward bias is a really good temperature sensor about a channel thickness away from the channel itself was planned to use that to contain faults with coordinated emergency SCRAM's (it's a 10~30 kV to about 2~3 kV bidirectional converter aiming towards about a MW but a PoC would be built smaller power if just for parts costs; the dies are only rated 1200 or 1700 V!), but they are all really high ohmic losses in the gate wiring presumably for avalanche proof behavior under cascode operation (if the drain leaks enough into the gate to turn the channel on before breakdown leakage through the reverse junction itself causes local damage, it's safe until the channel melts which takes literally several microseconds and thus easily several PWM cycles, so plenty of time to react and a brief transient is harmless), so I've pivoted to (ideally GaN V-JFETs if there are any smaller than 50$ a die with purchase limits of like one tray a month) likely epc-co GaN e-mode lateral MOSFET-substitutes which happily work at 50 MHz if you regeneratively/resonantly charge the gate and don't turn the channel on while there's drain voltage (output stored energy limits reasonable hard switch frequency to around 3 MHz typically for them) which sadly lack a thermal sense at the channel are not avalanche proof and who's gate is about 3x more finnicky than the SiC JFET (from formerly UnitedSiC). After my SerDes efforts I hope to get to mod a microwave oven to use such a topology of likely 200/300 V epc-co devices to feed the magnetron with regulated DC of about 2kV from probably around 250~300 V nominal LiFePO4 battery backed "DC microgrid" that is also easily digestible by most computer PSUs and I think many induction stove tops and such. I'm actually planning to use wafer.space to make an active digital pre-distortion driver for these power transistors that can talk with a central controller via (very short) fiber optics as it operates floating with severe switching transients (well, I expect around 20V/ns as "regular") and still has to coordinate for possible SCRAM. It's switched capacitor technology using just enough inductance to not need to turn channels on with notable drain voltage remaining. Oh, and poly-phase architecture allows it to neutralize ripple at the DC inputs and outputs greatly reducing the blocking demands put onto the EMI filters because if you have 1kW of e.g. 27 MHz "RF" power in the switched capacitors going down to micro watt levels of radiated leakage externally is... Hard.... If you try to maintain appliance-level 99% efficiency (if it was just a DC/DC transformer not a microwave with it's horrible magnetron).

oh, god yeah high power + high voltage stuff is terrifying (edited)

Archit3ch (George)

yeah, but no noise profile, so it's a bit of qualification risk... i'll drop this conversation thread here and let you both design

Well, then I would appreciate learning how this could be measured within the limits you'd have on TinyTapeout.

brookieoz

oh, god yeah high power + high voltage stuff is terrifying (edited)

Well it lives in a can (the stuff higher power than a microwave), likely by expectations in basically a larger BBQ propane tank with a plate heat exchanger attached that condenses the propane back to liquid and with the liquid pumped through very dense coolant manifolds to the dies (the upper half of the power range doesn't need to be that efficient, so that's what suddenly asks for a 10x TDP headroom; but even from like 500 kW (half power of 1 MW) 1% loss is already 5 kW, and 5% of 1 MW is, well, 50 kW... GaN-on-silicon is a little vulnerable there. And density is quite desired to mitigate parasitics through shorter switching loops....

1

brookieoz

The 6V natural devices are documented in the open source pdk, I didn't see any 3.3V ones

This section describes Native NMOS rules. This process supports 3.3V and 5V/6V native Vt NMOS. The difference between 3.3V and 5V/6V native Vt transistor is that the 5V/6V native Vt NMOS need Dualgate layer.

https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_10_05.html

NAT.4 Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec) 1.8

NAT.5 Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec) 1.8

That's btw. also my complaint about them muddying the waters by coding ERC as DRC (while plenty applications would not want shorter channels and many designs shouldn't dabble to avoid nasty surprised in the shape of severe drain-induced-barrier-lowering, there are IMO applications where the biasing conditions allow this DIBL to be of either no concern or at least sufficciently mitigated, while the reduced saturation current of these fairly-long-channel devices as well as the severely excessive (vs. minimum size) capacitance (relative to what can be considered reasonable operating current) is actually very harmful....).... ERC are fine and coding a pitfall like this into a DRC ddeck is also fine, but then do provide a user-accessible fully-automated-applied waiver so e.g. I can include test structures with shorter channels onto an e-test die to calibrate SPICE models/bins for shorter nvt channels because modeling accuracy/matching-physical-behavior is a prerequisite to designing anything "production" that would utilize such shorter-channel nvt devices. In particular I doubt that the thin oxide (3.3V) nvt suffer catastrophic DIBL effects "starting at" the same channel length as thick oxide (5/6V) nvt. "But what do I know...."

What's the min W on them?

11:26 p.m.

because like, in the bandgap schematic I drew up the input pair is sized 2*(5/5) and the startup is "min W" / 5L

11:26 p.m.

so like, I'm not worried about the min L of 1.8 / DIBL effect

That also reminds me I wonder if there's special spacing concerns related to isolation tanks / deep n-wells for the natural Vt devices

11:41 p.m.

Oh yeah, rule NAT.10, no nwell, sounds like they're non-isolateable aka they must be on bare substrate

11:42 p.m.

(maybe? Unless deep n-well is a different layer or something)

brookieoz

1 is usually easier to do because you typically have that already on the chip, but it's less accurate 2 is more accurate but it has its own complications

I'm thinking of planning to include temperature sensors if they can be made compact enough and their wiring can be made small-enough-area-overhead, onto the "muxed e-test"; I'm thinking like having one above and one below each DUT with the analog MUX's bus being horizontal, and setting up to allow measuring the closest as well as the next one over each, so that gradient effects can be at least somewhat interpolated. non-selected DUTs are power gated as power is literally just another signal (only GND/substrate is special because there's no accessible substrate isolation) with it's drive and it's sense line (kelvin/4-wire measurement setup, just with more DUT pins than just the 2 where the 4-wire naming came from). I think there are some DUTs that are due to their nature interesting under fairly power dense biasing conditions, which would probably make pulsed/low-duty-cycle measuring (to measure under conditions that are not sustainable thermally at least not with any easy setup that tries to allow measuring near the -40C corner) practically-mandatory, despite that the analog MUX itself is otherwise (by my current plans at least) primarily focused on density and sufficiently low leakage (instead of RC time constant), to approximately measure DC operating points. Having temperature sensors should probably allow using true "DC" measurements even for power-dense DUTs, by adjusting for the increased temperature in the SPICE .DC sweep that has plenty tunables statistically calibrated to the measurement results. (E.g., my plan is to measure many dozens of dies wire bonded to regular COB-with-mezzanine-on-the-back at a cost of 1500$ (incl. @Tim 'mithro' Ansell 's profit margin) for all 1000 dies, take the existing SPICE models and (just using purely synthetic bias conditions and device sizing and at least a bit of manually copying-over the physical structure parameters) initially port/convert them from the current legacy BSIM4 models to numerically far far less crusty PSP103 (probably actually PSP104 these days...), and then do a huge model fit ("parameter estimation") compute run that tries to dial in the PSP103 model cards and some extraction tunables to explain the multimeter logs (it obviously has to estimate the local mismatch "random variable" values for each measured die; because I'd get statistically supported estimates on just how much this local mismatch really is for all the devices that suffer enough to make mismatch modeling relevant, I'm actually interested in favoring measuring more individual dies instead of just spamming more bias condition samples onto each measured die, after like some thousands (probably less than a million!) of samples per DUT and die).

3:16 a.m.

DF.2a Min Channel Width 0.22 [thin oxide] 0.3 [thick oxide]

https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html navigation via unfolding menu without navigating pages on the left, or previous/next links in the footer. The layout/menu is sadly kinda shitty for DRM section 7

brookieoz

(maybe? Unless deep n-well is a different layer or something)

technically that is a different layer

namibj

technically that is a different layer

oh interesting, if so that means you could have isolated native vt devices. that's pretty cool (I also learned that GF180 is a dual poly process which is also really cool, that allows you to do some pretty neat things regarding floating gate devices)

brookieoz

(maybe? Unless deep n-well is a different layer or something)

yeah doesn't look like it bans dnwell (with then needed lvpwell to form nmos channels!) under NAT.... huh..... if actually really DRC clean and not just looking like it is, this would definitely be something that needs to get covered by the upcoming e-test die.

brookieoz

oh interesting, if so that means you could have isolated native vt devices. that's pretty cool (I also learned that GF180 is a dual poly process which is also really cool, that allows you to do some pretty neat things regarding floating gate devices)

wdym, dual poly process?

3:22 a.m.

gf180 as-such is a HUGE family of processes that AFAIK primarily share BEOL and litho, but pretty much the entire rest is up for flexibility in some configuration

basically, there's two poly layers. poly1 and poly2. Poly1 is used for the majority of transistor gates, poly2 is used for other stuff (poly resistors, poly-poly caps, specialized transistors)

ofc BEOL stackup is also flexible, in case you forgot/overlooked

3:23 a.m.

we don't have poly1

ah

3:23 a.m.

oh well, lol

does this mean that it would have poly2 as a routing layer that could cross poly1 gates?

well.... you probably don't want to do that

kinda? I guess it's still too high influence to really do that willingly most of the time at least....

if you did have both poly1 and poly2, physically poly1 is very close to the silicon substrate, and poly2 is not that far away from poly1. Both of them should be much closer to the silicon substrate than metal1

guess there's a reaason sky130's local interconnect layer is high up where gf180's metal1 is

It's neat for floating gate devices because you can have some quite strong capacitive coupling to the floating gate instead of relying on an active-poly cap

welp if only gf180 allowed us to have poly1 as well as the rest of gf180mcuD, but alas.... (the truly thin oxide devices are not covered by any open PDK to my knowledge, i.e., the 1.8-ish-V "core" devices)

also you should be able to get some pretty dense caps by doing substrate-poly1-poly2 (edited)

hmmmm (edited)

but oh well

namibj

does this mean that it would have poly2 as a routing layer that could cross poly1 gates?

anyway the reason why you wouldn't want to do that is mostly that poly resistance is pretty bad (aka much worse than metal even when salicided) and you're going to introduce a lot more capacitive coupling between the two poly's (edited)

3:29 a.m.

and if you do it for an analog transistor you'll mess up the matching of the devices (if you care about matching) (edited)

damn it's late why am I still not at the office..... accidental distraction IIRC. damn. Guess I'm better getting some food ready and hydrate and then get on my way to at least have entered "flow" before the first coworker shows up

brookieoz

and if you do it for an analog transistor you'll mess up the matching of the devices (if you care about matching) (edited)

do you have any idea how impactful stress effects are for structures like differential pairs that are more tuned for speed and compactness than for analog DC performance? E.g. think SRAM sense amplifier, or SerDes clocked comparator/sampler. The stuff that out-runs SCL logic if you don't optimize the logic hard enough....

oh

Like of course symmetry good but most of the time symmetry conflicts with density and excessive analog performance is just wasted on things like that

1

The rule of thumb in industry is: 1 - keep your critical matched devices away from the die edge 2 - for a WCSP package or other package with metal balls on it, put it either directly underneath / at the very center of the ball, or as far away / in the middle of the space between balls as possible

(I do hope to cover such nuances with extraction and the model fitting if it's meaningful enough and conceptually practical enough to pull off, but short of a handful DUT structures taped out to specifically excercise stress mismatch aspects, it's quite a daunting question...

)

you also need to do metal dummy fill block all the way up and avoid mettop routing if you can

hmmmm, good to know; I'm more eyeing STI asymmetry tho

namibj

(I do hope to cover such nuances with extraction and the model fitting if it's meaningful enough and conceptually practical enough to pull off, but short of a handful DUT structures taped out to specifically excercise stress mismatch aspects, it's quite a daunting question...

)

Honestly? this is one of those cursed problems that doesn't really have a solution because when you solder the part down and it cools, it'll put stress on the silicon in an unpredictable fashion and all your parameters will shift all over the place (edited)

3:37 a.m.

it's actually one of the biggest limiting factors to bandgap accuracy

3:40 a.m.

I believe there are some academic papers that have literally proposed putting strain sensors near the bandgap to find the stress on the silicon and adding a correction factor to correct for the impact of the stress on silicon properties

brookieoz

Honestly? this is one of those cursed problems that doesn't really have a solution because when you solder the part down and it cools, it'll put stress on the silicon in an unpredictable fashion and all your parameters will shift all over the place (edited)

I mean of course, but the model developers cared enough about STI effects to provision for them, and I've caught mention of STI induced strain in bulk CMOS in a couple of papers I had dug through for almost certainly other reasons (don't know exact details sadly, can't readily link one of them papers, I should really start archiving and at least preparing for indexing all the non-fiction digital reading material I go through for questions like this...... also a brief reference in like a quarter of a packed slide of a deck that mentioned actually model fitting using a full CMOS die and Xyce and $$$ (probably ROL or Dakota, wish I could FIND that page, but I've spent hours already trying to recover it to no avail))....

brookieoz

I believe there are some academic papers that have literally proposed putting strain sensors near the bandgap to find the stress on the silicon and adding a correction factor to correct for the impact of the stress on silicon properties

I'm visualizing LBE-based pseudo-MEMS tactics

namibj

hmmmm, good to know; I'm more eyeing STI asymmetry tho

Hmmm, what do you mean by this?

(does one do strain sensing via some kind of X/Y orientation-0differentiating wheatstone bridge and precision poly resistors?)

brookieoz

Hmmm, what do you mean by this?

AFAIK all die that is not (COMP or DUMMYCOMP) is filled with STI (modulo setback/slope effects of the STI sidewalls)

namibj

(does one do strain sensing via some kind of X/Y orientation-0differentiating wheatstone bridge and precision poly resistors?)

something like that. It's been 4-5 years since i took a class on MEMS devices and I recall there were some really specific impacts of silicon unit cell orientation on the change in resistance vs stress, it's very direction dependent. I think you use n-diff or p-diff resistors instead

STI IIUC is grown in a way that causes it to exert compressive stress horizontally on the surrounding COMP.

namibj

AFAIK all die that is not (COMP or DUMMYCOMP) is filled with STI (modulo setback/slope effects of the STI sidewalls)

all? that seems a little bit odd, I'd expect there to be density rules regarding this kinda thing

if this has any lack of symmetry vaguely nearby, you'll have asymmetric local strain on your circuity. Question then is just how much does this actually change, and if the answer is "enough to care", how could we afford to extract it from the layout to feed to the model and at least replicate the effect in SPICE.

brookieoz

all? that seems a little bit odd, I'd expect there to be density rules regarding this kinda thing

that's why there's a density rule that says how much minimum and maximum coverage (COMP OR DUMMYCOMP) is allowed to have

1

3:50 a.m.

DCF.1b min 25%; DCF.1d max 70%.

3:51 a.m.

because of planarization you want to keep that actually deently balanced

namibj

if this has any lack of symmetry vaguely nearby, you'll have asymmetric local strain on your circuity. Question then is just how much does this actually change, and if the answer is "enough to care", how could we afford to extract it from the layout to feed to the model and at least replicate the effect in SPICE.

ah I see now, you mean the impacts of that specifically It really depends on how much stress gets created by the STI layer and that's kinda hard to estimate; symmetric layout is honestly just the easiest way to de-risk and not have to worry about it, putting dummy devices all around your critical devices to remove effects of asymmetry

(at millimeter scale at least; not so important at very fine scale though you probably want some dummy comp around a lonely active device regardless)

brookieoz

ah I see now, you mean the impacts of that specifically It really depends on how much stress gets created by the STI layer and that's kinda hard to estimate; symmetric layout is honestly just the easiest way to de-risk and not have to worry about it, putting dummy devices all around your critical devices to remove effects of asymmetry

yeah but I prefer my SRAM dense

....does SRAM need to be that precise?

and my delay locked loop low power (small devices, no excessive parasitics either) and also ideally so small I have to get strategic with routability of it's signals. Can't get there with traditional low frequency (1 MHz GBW class) analog matched pair layout guidelines, sadly.

3:56 a.m.

notable offenders are things like nearby control signal decoders/inverters/buffers, as well as non-spammed-for-symmetry well/substrate taps.

brookieoz

....does SRAM need to be that precise?

sense amplifier offset is high-impact on how long you can make a bitline before you get issues with reading in any timely manner

1

4:02 a.m.

(if the RC arrangement is suitable and the operating voltage plentiful enough, accidentally loosing internal latched state isn't so much a worry as the long bitline taking "forever" to get differentially charged enough to be safe for the sense amplifier to start resolving; basically just need to make sure the access transistors are sufficciently weakening vs. the quality of imperfect pre-charge (residual delta voltage on a differential bitline pair prior to activating the wordline for a read; c.f. writing on such a simple classic 6T single-port SRAM cell is done by fully charging the bitline pair to VDD and VSS respectively before activating the wordline and letting the abundance of potential and charge overthrow the cross-coupled inverters inside)) (edited)

yeah I can't say I've designed an SRAM sense amp before, it's interesting to hear the requirements...

4:05 a.m.

I'd assume that something like an SRAM sense amp ends up being more like a clocked comparator

for DRAM it's actually not a speed impact anymore, because eventually you fail to resolve the miniscule differential voltage that came up after activation; for SRAM like this at least you get the option of just waiting until the weak latch has driven the bitline pair to however high a fraction of full-throw as even a rancid sense amplifier could demand to promise "no bit errors from input swing not reliably exceeding amplifier input offset"

brookieoz

I'd assume that something like an SRAM sense amp ends up being more like a clocked comparator

still, they have input offset.

yes, that's true; I'd assume that you have an extremely limited amount of space for an SRAM sense amp since any large area would be detrimental to SRAM density, in which case I feel like your mismatch contributions will end up being dominated by how large you can make your input pairs and still have them have low capacitance enough to not kill your speed... in which case I suspect that the impact of asymmetric STI stress will be a second order factor

but take for comparison a 1:2 current mirror where you want to keep the 2-side drain capacitance small with little regard to anything else except matching. That'd dictate 3 fingers in total, and two of those to share a drain contact diffusion area. D1 G S G D2 G S would be the most direct compact layout. In theory it's balanced/symmetric, except for junction capacitance (we already know that's something to minimize and you can't really minimize that when you're trying to keep that matched) and STI stress because left of D1 and right of S there's a chunk of STI and the outer gates feel more strain than the inner gate.

there's another source of asymmetry that isn't junction capacitance; current flow direction. to be honest I've only really be taught about this and I've never seen any data to see the matching degradation regarding it, so it could just be holdover paranoia from earlier processes

brookieoz

yes, that's true; I'd assume that you have an extremely limited amount of space for an SRAM sense amp since any large area would be detrimental to SRAM density, in which case I feel like your mismatch contributions will end up being dominated by how large you can make your input pairs and still have them have low capacitance enough to not kill your speed... in which case I suspect that the impact of asymmetric STI stress will be a second order factor

I guess a possibly less overshadowed situation might be a differential clock buffer's differential balance-ness.

brookieoz

there's another source of asymmetry that isn't junction capacitance; current flow direction. to be honest I've only really be taught about this and I've never seen any data to see the matching degradation regarding it, so it could just be holdover paranoia from earlier processes

maybe if there's non-negligible magnetic fields around?

4:18 a.m.

(iirc hall effect isn't thaaaat hard to trip enough to visually see correlation if you plot measurements under strong magnet conditions)

I don't think it's a magnetic effect, my hypothesis is that it's more of a dopant implant direction sort of thing

I guess the angle might be adjusted with notable lack of symmetric precison

4:20 a.m.

IIUC "use nvt to skip"

like if the dopants are being implanted at a slight angle instead of perfectly straight on into the silicon, maybe you get slightly different dopant concentrations at all the north edges compared to all the south edges

4:21 a.m.

which could cause the transistors to behave slightly differently if the source is on the north side vs south side

there are actually implants that get shot 4 times to lurk under the mask edges/"undercut" the mask, tho may not be a thing yet in gf180mcuD; is a thing in sky130A and IHP SG13CMOS5L/SG13G2.

oh yeah, pocket implants. devices with those kinda break the rules for scaling W and L

but yeah I understand that lack of excessive symmetry will give avoidable amounts of mismatch. Just would be good to actually know/understand/predict the actual amounts of such layout-dependent mismatch vs. already fairly well understood (tho not too sure how good of a handle we have on the standard deviation magnitude that actually applies for the mistmatch local variation) "local mismatch" that scales the regular way of based-on-active-area.

(oh and FYI some of those devices can have very strong Vt dependence on W and L)

yeah

brookieoz

(oh and FYI some of those devices can have very strong Vt dependence on W and L)

though AFAIK at the sizes where those implants are standard features used by default in a PDK, mere plain short channel effects like DIBL are already so intense that this kind of scaling to W and L so close to DRC minimums is already futile if you expect analog scaling "rules".....

hahaha yeah I've just had very unintuitive experiences dealing with them like drive strength at constant VGS going down with increasing W because it increased my Vt by so much

4:30 a.m.

(conversely, my leakage current also goes down with increasing W

)

would a 4-wire-measured (from a benchtop multimeter capable of doing that) be "good" for a mere vBE temperature diode sensor to put on-die if there are packaging pads to spare? Might a "even simpler" plain lvpwell-to-dnwell buried junction do "just as" fine?

brookieoz

hahaha yeah I've just had very unintuitive experiences dealing with them like drive strength at constant VGS going down with increasing W because it increased my Vt by so much

I'm not too sure but that might actually be STI sidewall compression stress you've seen if that's minimum width devices, not "just" doping.

4:33 a.m.

if the STI is much bulkier than the narrow channel between......

namibj

I'm not too sure but that might actually be STI sidewall compression stress you've seen if that's minimum width devices, not "just" doping.

I don't think so, the process I've seen that didn't have STI all over the place

4:33 a.m.

at least, I don't think it did

huh..... u sure? how else did it define where the channel ended width-wise?

that's a good question, I'm not sure

(I'm not referrign to dummy STI here.... just natural minimum spacing chunks surrounding the channel's COMP)

yeah maybe I'm misremembering, I can't picture the specific proprietary PDK + design rules file in my mind right now hahaha

namibj

would a 4-wire-measured (from a benchtop multimeter capable of doing that) be "good" for a mere vBE temperature diode sensor to put on-die if there are packaging pads to spare? Might a "even simpler" plain lvpwell-to-dnwell buried junction do "just as" fine?

let me answer the second question first - i'd be quite careful about using just a simple p-well to deep n-well "diode" because that's not really a diode, it's a parasitic vertical bjt with a p-substrate collector (edited)

4:37 a.m.

and any time you actually pass a current into that specific diode you're going to be injecting carriers into the substrate and creating substrate current

4:40 a.m.

additionally, that deep n-well can also collect substrate currents and that can be very scary if you put it in the middle of a power FET and the body diode of that power fet turns on

huh? shouldn't that under forward bias of the lvpwell-to-dnwell junction have the dnwell at a lower voltage, and as long as that voltage remains at or above the substrate itself, not have substrate current?

namibj

huh? shouldn't that under forward bias of the lvpwell-to-dnwell junction have the dnwell at a lower voltage, and as long as that voltage remains at or above the substrate itself, not have substrate current?

4:42 a.m.

The deep n-well isn't thick enough to assume that all the carriers recombine in it

hmmmm

so you can't assume that it's purely two diodes all the time

4:43 a.m.

if you're purposefully turning on the p-well to deep n-well junction, you're flooding holes into the deep n-well. some will recombine but the rest will be collected by the p-sub

4:44 a.m.

that's kind of the beta of the parasitic BJT there

4:44 a.m.

which I believe the PDK mentions is somewhere around 1?

I thought it'd have been better than just surrounding a speck of ncomp with a ring-shaped substrate tie

1

4:45 a.m.

not alone because that'd require driving the ncomp below GND

4:46 a.m.

VPNP HFE (3.3V LV) W/L= 0.42/10 (Emitter Size) 0.8 min 1.6 typ 2.4 max

oh, the pdk says typ beta of 1.6

4:47 a.m.

yeah

4:47 a.m.

so you actually have more current going into the sub (in most cases) (edited)

so it'd have to have dnwell tied to psub to block this current?

Eehhhhhhhhhh

4:48 a.m.

You'd have to be careful about any potential large PMOS's nearby in case you introduce latchup risk

I mean I'm ears for other suggests of how to draw a decent thermometer that can be read with a 4-wire benchtop multimeter

namibj

I mean I'm ears for other suggests of how to draw a decent thermometer that can be read with a 4-wire benchtop multimeter

you could use the P->N body diode of an isolated PMOS like so

brookieoz

You'd have to be careful about any potential large PMOS's nearby in case you introduce latchup risk

I'd expect a guard ring of psub-tap around this diode and if nearby pmos-nwell's well-tap guard-fence to suffice against latchup if the DRC guides about how not to catch latchup are followed? I mean, I'm not fixated on that kind of diode for the thermometer task..... if you have a suggestion for how effectively a diode-connected nvt nmos channel would thermometer, or other such majority-carrier-only structure, I'm open.

brookieoz

you could use the P->N body diode of an isolated PMOS like so

by connecting the shallow n-well and epitaxial p-well together you can kinda collect any carriers of either type before things get wacky

brookieoz

you could use the P->N body diode of an isolated PMOS like so

there is no p-epi as you've drawn or other isolating P-doped layer to stack between dnwell and shallow nwell

oh no, the isolated PMOS's have connected shallow n-well to deep n-well?

1

the only shallow thing that exists is ncomp on lvpwell on dnwell (on psub)

maaaaan i've seen that in the process I'm working in right now

4:56 a.m.

it sucks

ehhhh

4:57 a.m.

hey I got shottkey!

I haven't used a shottky in anything so far, i have no clue how well controlled their vf's are

and at least I got dnwell. IHP's bargain-variant CMOS5L of their SG13 family doesn't have that. no isolated nmos at all

oh yeesh

(SG13G2 is also offered on an open source gated MPW with resulting discount pricing/AFAIK-federal-sponsoring, but I blame the HBT's for the area cost being like 2.5x as high)

5:00 a.m.

If you've not seen them HBT yet..... well, you might spontaneously develop yearning for them once you do learn.

brookieoz

oh yeesh

fT/fmax = 350/450 GHz

1

5:01 a.m.

note: this is on 130nm-CMOS-class litho

namibj

If you've not seen them HBT yet..... well, you might spontaneously develop yearning for them once you do learn.

i won't lie i'm definitely more on the lower power side of design, less so power

5:03 a.m.

used to sub-uA biases hahaha

and you get 130nm CMOS, incl. dnwell, 5 thin metal, 2 thick metal, high sheet poly (iirc 2k and 0.5u min width), one MIM layer iirc just above m5..... and while you I think would have to not enjoy the special open source discount, RRAM and TSV are add-ons available on AFAIK MPW runs (and localized backside etching is also around)

neat

namibj

and you get 130nm CMOS, incl. dnwell, 5 thin metal, 2 thick metal, high sheet poly (iirc 2k and 0.5u min width), one MIM layer iirc just above m5..... and while you I think would have to not enjoy the special open source discount, RRAM and TSV are add-ons available on AFAIK MPW runs (and localized backside etching is also around)

i thought CMOS5L was no-MIM?

He was talking about the full SG13G2

1

11:15 a.m.

It's also available has a discounted open mpw program, but it's still much more expensive than cmos5l and it only runs once a year.

namibj

the only shallow thing that exists is ncomp on lvpwell on dnwell (on psub)

Actually this might be workable, but it'll be a little bit odd Connect dnwell and lvpwell together and use that as the positive side to a negative ncomp

2:41 p.m.

You'll want to connect the dnwell/lvpwell to a relatively strong supply because it is exposed to substrate (aka don't use this node in a high impedance way if it's surrounded by a noisy environment) (edited)

brookieoz

You'll want to connect the dnwell/lvpwell to a relatively strong supply because it is exposed to substrate (aka don't use this node in a high impedance way if it's surrounded by a noisy environment) (edited)

Yeah, sure. I mean I expected 4-wire measuring anyways

Honestly I'm not sure if you really need 4 wire measurement, 2 wire should be OK?

7:09 p.m.

Once I get home I'll draw out the scheme I had in mind

2:13 a.m.

Something like this should cancel the routing impedance, and you get a delta V

brookieoz

Click to see attachment 🖼️

hmmmm..... (Tbf, I did kinda hope/expect the measuring to be single-point-calibration-capable across the entire operating temperature range for the dies, but I guess this shouldn't preclude such tactics, at least not necessarily. I guess it's sort-of-vaguely 4-wire-still, though probably more of a 3-wire with one shared across as many such sensors as one wants to have. So, like, yeah? I'd probably have to run comparative numbers/simulations anyways though. But I think a good thank you is due for that approach given it only needs two sense lines muxed. At least as long as the routing mux impedance between the v1 and the v2 paths are sufficiently matched in practice to not matter much. That specifically might be a notable downside if the setup could otherwise have had substantially smaller mux gates it could rely on 4-wire calibration to cancel out the routing and mux impedance in post of. The extra wires of course suggest more routing congestion limitations of MUX packing density...) (edited)

namibj

hmmmm..... (Tbf, I did kinda hope/expect the measuring to be single-point-calibration-capable across the entire operating temperature range for the dies, but I guess this shouldn't preclude such tactics, at least not necessarily. I guess it's sort-of-vaguely 4-wire-still, though probably more of a 3-wire with one shared across as many such sensors as one wants to have. So, like, yeah? I'd probably have to run comparative numbers/simulations anyways though. But I think a good thank you is due for that approach given it only needs two sense lines muxed. At least as long as the routing mux impedance between the v1 and the v2 paths are sufficiently matched in practice to not matter much. That specifically might be a notable downside if the setup could otherwise have had substantially smaller mux gates it could rely on 4-wire calibration to cancel out the routing and mux impedance in post of. The extra wires of course suggest more routing congestion limitations of MUX packing density...) (edited)

I think diode vf characteristics probably have enough process variation to overwhelm impacts of routing resistance unless you're routing like a super long and thin trace? Like if you put a 1uA bias through a 1kOhm routing resistance that's 1mV and process variation in diode vf is almost certainly more than that

1:14 a.m.

So tbh if you want accuracy that isn't a spread of like, +/-15C you'll need to calibrate it (edited)

1:16 a.m.

especially if you're doing this across multiple dies, process variation across a single wafer is certainly higher than a single die

brookieoz

I think diode vf characteristics probably have enough process variation to overwhelm impacts of routing resistance unless you're routing like a super long and thin trace? Like if you put a 1uA bias through a 1kOhm routing resistance that's 1mV and process variation in diode vf is almost certainly more than that

but process variation of diode vf should be easy to cancel with single point calibration? Or, at least, with 2-current fixed-temperature calibration? Like, start off with them in a static environment or maybe even just a box with a convection fan and a thermometer in the box air to know how warm the die is; measure what the diode(s) say, know what to adjust with the voltage(s)-to-temperature formula later used to measure local temperatures under notably different thermal conditions. Say, e.g. as a likely particularly intense case, HCI behavior biasing conditions around the bottom of the temperature range (-20C or therabouts), where I at least would expect the unusually-high local power density with correspondingly strong local thermal gradients that necessitate particularly effective grid-of-diodes thermal gradient mapping to measure well.

Why is there a "magnet" layer in magic now?

2:24 p.m.

Actually, what is fence as well?

Tholin

Why is there a "magnet" layer in magic now?

Ah