wafer.space Community

Architeuthis Flux

Yeah I watched that stream you did a few months ago, super rad. I've been meaning to hit you up @peterkinget and chat.

Hi, feel free to suggest some times for a zoom meeting. I am on Pacific time right now. I do not check Discord often enough ... so feel free to send me an email as well peter.kinget@columbia.edu. (edited)

2

@Tim 'mithro' Ansell @Andrew Wingate We have finished the COB design for the MOSbius chip on the first wafer space run. Where do we take it from here? [BTW, Tim, also sent you an email, we can continue the discussion there also.]

Hey guys, We're narrowing down on what a panel should look like I have committed some files and we will see what the PCB house and the wirebonders have to say, but wanted to keep you all informed. The boards are 77mm/side which should be good enough for JLCPCB to be ok, and still fit within wirebonders jig This file can be found here: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/blob/main/74pad-70pin-mezzanine/panel-74pad-70pin-mezzanine/production/panel-74pad-70pin-mezzanine.zip Panel files here: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/tree/main/74pad-70pin-mezzanine/panel-74pad-70pin-mezzanine online viewer here: https://kicanvas.org/?repo=https%3A%2F%2Fgithub.com%2Fwafer-space%2Fchip-on-board-wire-bonded-pcbs%2Ftree%2Fmain%2F74pad-70pin-mezzanine%2Fpanel-74pad-70pin-mezzanine @Tholin @peterkinget @Meinhard Kissich @xianglin_pu Afaik, you are the only ones wanting custom COB. Let me know if you need any assistance.

chip-on-board-wire-bonded-pcbs/74pad-70pin-mezzanine/panel-74pad-70...

Wire bonded chip on board PCB designs. Contribute to wafer-space/chip-on-board-wire-bonded-pcbs development by creating an account on GitHub.

chip-on-board-wire-bonded-pcbs/74pad-70pin-mezzanine/panel-74pad-70...

Wire bonded chip on board PCB designs. Contribute to wafer-space/chip-on-board-wire-bonded-pcbs development by creating an account on GitHub.

2

And I just need to change the routing, so there should be no complications.

1

9:55 a.m.

Actually, I think I already have mine pushed to github

9:56 a.m.

https://github.com/AvalonSemiconductors/gf180mcu_cob/tree/main/74pad-mp-mezzanine

Tholin

https://github.com/AvalonSemiconductors/gf180mcu_cob/tree/main/74pad-mp-mezzanine

Replying to your comment from https://discord.com/channels/1361349522684510449/1361349523724570941/1481581473235468289 It looks like you don't have the same components or placement. I think this is alright, but just want you do be aware. Default uses qty(8) 0201 components

Oh, the capacitors?

1

@Andrew Wingate BTW, you can use `Top/Bottom/Connected layers" for the settings of vias in KiCAD, that avoid rings on non-connected internal layers and reduces cuts in the internal planes and JLC processes that with no problems.

I can fix that. Are the mezzanine and COB footprint in the right places?

Tholin

I can fix that. Are the mezzanine and COB footprint in the right places?

I don't want to say yes without verifying, but I believe it should be centered.

tnt

@Andrew Wingate BTW, you can use `Top/Bottom/Connected layers" for the settings of vias in KiCAD, that avoid rings on non-connected internal layers and reduces cuts in the internal planes and JLC processes that with no problems.

Thanks. I guess I don't know what that means though?

The annular ring settings.

2

tnt

The annular ring settings.

I'll look into that. Thank you

Btw, I am open to collaborating for wafers/die (preferably wafers). I have access to some pretty nice equipment: https://docs.google.com/document/d/1n0aPQOVQ90qUniRZclDV7zVC_QPGmtOmgF9b8g0f-MM/edit?usp=sharing

MPW Dicing to Packaging

We can establish an NDA for handling the MPW Wafers. Dice, Attach, Package/Chip on Board. Potential Learning Outcomes: It would be informative to create digital learning modules that could be added into a course for students about the entire process. Could there be an undergraduate level or C...

1

urish started a thread. 2026-03-14 8:44 p.m.

Hey all, just a little backstory on the COB. The wirebonder machine has a vacuum chuck and it's able to take a board no larger than 70mm/side. They will be populating the boards with the mezzanine connector and the passives before the die is wire-bonded. They also will be creating a custom chuck that can fit the mezzanine connector and have room for the passives area we defined before. Someone can correct me if I'm wrong, but I think we're going to have them all glob-topped with clear. Speak up if this is concerning to you. Long story short, thank you all who spoke up early about how they thought things would go, because for the most part it seems to be going about how we thought it would.

1

Andrew Wingate

Hey all, just a little backstory on the COB. The wirebonder machine has a vacuum chuck and it's able to take a board no larger than 70mm/side. They will be populating the boards with the mezzanine connector and the passives before the die is wire-bonded. They also will be creating a custom chuck that can fit the mezzanine connector and have room for the passives area we defined before. Someone can correct me if I'm wrong, but I think we're going to have them all glob-topped with clear. Speak up if this is concerning to you. Long story short, thank you all who spoke up early about how they thought things would go, because for the most part it seems to be going about how we thought it would.

(actually I think clear is a beautiful aesthetic)

Lofty

(actually I think clear is a beautiful aesthetic)

Of course! Me too. This is only a problem if you're worried about interference from light. I think they're going to look quite beautiful!

On sky130 I didn't see a ton of interference from light unless in sensitive circuits. Things like SRAM and analog stuff might be more problematic.

2

Andrew Wingate

Hey guys, We're narrowing down on what a panel should look like I have committed some files and we will see what the PCB house and the wirebonders have to say, but wanted to keep you all informed. The boards are 77mm/side which should be good enough for JLCPCB to be ok, and still fit within wirebonders jig This file can be found here: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/blob/main/74pad-70pin-mezzanine/panel-74pad-70pin-mezzanine/production/panel-74pad-70pin-mezzanine.zip Panel files here: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/tree/main/74pad-70pin-mezzanine/panel-74pad-70pin-mezzanine online viewer here: https://kicanvas.org/?repo=https%3A%2F%2Fgithub.com%2Fwafer-space%2Fchip-on-board-wire-bonded-pcbs%2Ftree%2Fmain%2F74pad-70pin-mezzanine%2Fpanel-74pad-70pin-mezzanine @Tholin @peterkinget @Meinhard Kissich @xianglin_pu Afaik, you are the only ones wanting custom COB. Let me know if you need any assistance.

I'm all good with the default CoB. Thus, my previous question to get the mating connector/routing right. Thanks for keeping us all in the loop

No issue with clear glob-top. Actually, I quite like seeing the die through it. Gives it a nice touch, that you usually don't have in commercial products.

1

Meinhard Kissich

I'm all good with the default CoB. Thus, my previous question to get the mating connector/routing right. Thanks for keeping us all in the loop

No issue with clear glob-top. Actually, I quite like seeing the die through it. Gives it a nice touch, that you usually don't have in commercial products.

Sounds great! I was just trying to ping everyone i remembered who said anything about custom anything. Cheers

Andrew Wingate

Hey all, just a little backstory on the COB. The wirebonder machine has a vacuum chuck and it's able to take a board no larger than 70mm/side. They will be populating the boards with the mezzanine connector and the passives before the die is wire-bonded. They also will be creating a custom chuck that can fit the mezzanine connector and have room for the passives area we defined before. Someone can correct me if I'm wrong, but I think we're going to have them all glob-topped with clear. Speak up if this is concerning to you. Long story short, thank you all who spoke up early about how they thought things would go, because for the most part it seems to be going about how we thought it would.

Thanks for the information, We have modified our COB PCB based on the deafult design, and I would like to comfrim that due to different pin functions, if it's possible we could custimze our routing (re-route some wires) and passive components (re-location and delete some components) Our design is uploaded here: https://github.com/mosbiuschip/WaferSpace_COB_70pins/tree/main/V3_COB_Original/V3_COB_Original Any feedbacks will be appreciated

WaferSpace_COB_70pins/V3_COB_Original/V3_COB_Original at main · mo...

PCB design for COB packaging through wafer.space. Contribute to mosbiuschip/WaferSpace_COB_70pins development by creating an account on GitHub.

xianglin_pu

Thanks for the information, We have modified our COB PCB based on the deafult design, and I would like to comfrim that due to different pin functions, if it's possible we could custimze our routing (re-route some wires) and passive components (re-location and delete some components) Our design is uploaded here: https://github.com/mosbiuschip/WaferSpace_COB_70pins/tree/main/V3_COB_Original/V3_COB_Original Any feedbacks will be appreciated

Just got home from a long day and am very tired. I think it looks alright at first glance, but you probably need to refill your pours, and the passives need to be on the same side as the mezzanine connector (back)

6:20 a.m.

https://kicanvas.org/?repo=https%3A%2F%2Fgithub.com%2Fmosbiuschip%2FWaferSpace_COB_70pins%2Ftree%2Fmain%2FV3_COB_Original%2FV3_COB_Original

The passive also need to be in the "designated" area to not interfere with the chuck mounting right ?

2

1

tnt

The passive also need to be in the "designated" area to not interfere with the chuck mounting right ?

That is also correct, but given how they already were and would likely stay, i omitted that part.

2

Has there been any thoughts about COB package for half and quarter size chips? I don't see anything in the repo. From my point of view it would be cool if the pinout was somewhat consistent between them (w.r.t. the input and bidir pin numbering in the default template) - if you are planning to package all of the variants, that is!

Andrew Wingate

Just got home from a long day and am very tired. I think it looks alright at first glance, but you probably need to refill your pours, and the passives need to be on the same side as the mezzanine connector (back)

Many thanks Andrew!

xianglin_pu

Thanks for the information, We have modified our COB PCB based on the deafult design, and I would like to comfrim that due to different pin functions, if it's possible we could custimze our routing (re-route some wires) and passive components (re-location and delete some components) Our design is uploaded here: https://github.com/mosbiuschip/WaferSpace_COB_70pins/tree/main/V3_COB_Original/V3_COB_Original Any feedbacks will be appreciated

@peterkinget please see the design here for the MOSbius COB design

Passives are OK on the top as long as they're not too tall. If on the bottom then they should be in the 'designated' area since we will be making a jig with cut outs for that area to hold the PCBs flat in the machine for the bonding

1

stuart

Passives are OK on the top as long as they're not too tall. If on the bottom then they should be in the 'designated' area since we will be making a jig with cut outs for that area to hold the PCBs flat in the machine for the bonding

'too tall' meaning 0201s/0402s and similar are fine, headers and pins are not

@stuart I think here the "no passive on top" is to not pay for dual sided SMT

1

2

makes sense

Andrew Wingate

Just got home from a long day and am very tired. I think it looks alright at first glance, but you probably need to refill your pours, and the passives need to be on the same side as the mezzanine connector (back)

Hi @Andrew Wingate and @xianglin_pu (Xianglin Pu?) — I am a bit confused why we are not using Xianglin’s design with the rotated pads. That will help with the bonding yield. E.g. take a look at the attached picture. Ignore the chip and the wires, but look at how the landing pads on the package are arranged. Notice how they are formed and slightly rotated so they are aligned with the bonding wire. Xianglin’s design was doing the same, why are we coming back from that? @Tim 'mithro' Ansell is there opportunity to try to COB designs for this run so we can gain experience with both alternatives?

Andrew Wingate

Hey all, just a little backstory on the COB. The wirebonder machine has a vacuum chuck and it's able to take a board no larger than 70mm/side. They will be populating the boards with the mezzanine connector and the passives before the die is wire-bonded. They also will be creating a custom chuck that can fit the mezzanine connector and have room for the passives area we defined before. Someone can correct me if I'm wrong, but I think we're going to have them all glob-topped with clear. Speak up if this is concerning to you. Long story short, thank you all who spoke up early about how they thought things would go, because for the most part it seems to be going about how we thought it would.

@Andrew Wingate et al., Can you do a couple with clear, but the large majority with dark epoxy. The source and drain junctions of MOS transistors will act as photodiodes and are light sensitive so if I have to pick between dark and clear, I would prefer dark. (That’s also what you see when you open up toys or so that used COB bonded chips.) Clear will be nicer for pictures, but that is secondary.

For the reference, this was the COB PCB design we used to have for rotated pads

@Andrew Wingate @Tim 'mithro' Ansell @xianglin_pu this is a picture I received from a tiny tape out COB. their landing pads are also “rotated”. What am I missing that we are going for a rectangular arrangement?

This is how we'll have the WS chips bonded on this run : https://github.com/htfab/breakout-ttgf0p2-cob/blob/main/images/bonding.png

tnt

This is how we'll have the WS chips bonded on this run : https://github.com/htfab/breakout-ttgf0p2-cob/blob/main/images/bonding.png

Oh so TT isn't using the COB?

No, the dies get directly mounted on a board compatible with our existing demo/test board. I think at one point there was also the possibility we'd ship some COB "module" to users so they could integrate on their own project, but given this is a test run and there is no real "customer" for theses boards , and there is only 400 dies and not 1000, it was decided to not do that here.

1

Hey @peterkinget I think a lot of this can fall on me more or less running out of time. In the beginning we didn't know a lot about the requirements from the wirebonders, but are working with them now. As stated above, we're needing specialized tooling to hold our boards along with a number of other supplementary documents stating design requirements. Creating and submitting all these with all the uncertainties we already have seems like a high bar for this run.

is there opportunity to try to COB designs for this run so we can gain experience with both alternatives?

I would probably punt this to the second run as we will have a lot of the process down

Can you do a couple with clear, but the large majority with dark epoxy.

I can try, but again, we have a large number of boards. I'm sure we can do them all dark, I am less confident on partials, but I can ask.

@stuart is helping us work with the wire bonders

1

Andrew Wingate

Hey @peterkinget I think a lot of this can fall on me more or less running out of time. In the beginning we didn't know a lot about the requirements from the wirebonders, but are working with them now. As stated above, we're needing specialized tooling to hold our boards along with a number of other supplementary documents stating design requirements. Creating and submitting all these with all the uncertainties we already have seems like a high bar for this run.

is there opportunity to try to COB designs for this run so we can gain experience with both alternatives?

I would probably punt this to the second run as we will have a lot of the process down

Can you do a couple with clear, but the large majority with dark epoxy.

I can try, but again, we have a large number of boards. I'm sure we can do them all dark, I am less confident on partials, but I can ask.

Thanks, @Andrew Wingate, no worries, understandable you are very busy. Question is how do we go forward since it sounds like TT is going with a different COB already. Should we make Xianglin’s with the rotated pads the standard template for the rest of the chips? Whatever works is fine with me, as long as we get working chips. If the packaging house has signed of on your rectangular design, then that is fine too and we can go for the other design in future rounds. I assume @Tim 'mithro' Ansell will provide some guidance on next steps. (edited)

@peterkinget - I think the rotated pad version might be a good default for everyone but need to figure out what the bond house says

1

Tim 'mithro' Ansell

@peterkinget - I think the rotated pad version might be a good default for everyone but need to figure out what the bond house says

OK, keep us posted and let us know how to assist. @xianglin_pu can point to the design files on GitHub. Note that others might have to change the board depending on where their grounds and VDDs are. We double bond the VDD and have VSS in the four corners, but I do not recall if that is a standard for the run or up to every design.

I believe the one critical thing is the PCB size and location of the components because that effects the chuck that holds everything. I'm unsure how the pads on the PCB effect things.

1

peterkinget

OK, keep us posted and let us know how to assist. @xianglin_pu can point to the design files on GitHub. Note that others might have to change the board depending on where their grounds and VDDs are. We double bond the VDD and have VSS in the four corners, but I do not recall if that is a standard for the run or up to every design.

Please see the attatched linke for the rotated pad COB PCB https://github.com/mosbiuschip/WaferSpace_COB_70pins/tree/main/V3_COB

WaferSpaceCOB_70pins/V3_COB at main · mosbiuschip/WaferSpace_COB...

PCB design for COB packaging through wafer.space. Contribute to mosbiuschip/WaferSpace_COB_70pins development by creating an account on GitHub.

Tim 'mithro' Ansell

I believe the one critical thing is the PCB size and location of the components because that effects the chuck that holds everything. I'm unsure how the pads on the PCB effect things.

Indeed, the size is critical, and for our current rotated-pad PCB design, the PCB size is 17mm x 18mm since all rotated pads need to be located without clearance issues. I am not sure if that is possible fitting in the chunk or not. What would be the maximum size that the chunk can tolerate ?

Hi @Andrew Wingate, @stuart mentioned that he would need wire bonding diagrams for each project to reduce the chance of bonding a chip the wrong way around, for example. Since some of the chips have distinctive features, I could provide you with a rendering of the top metal layer for each project, which you could then combine with a screenshot of the PCB and add the bond wire connections. Would it be fine if I provide you the images with their ID as names, so that you can automate the bonding diagram creation?

Leo Moser (mole99)

Hi @Andrew Wingate, @stuart mentioned that he would need wire bonding diagrams for each project to reduce the chance of bonding a chip the wrong way around, for example. Since some of the chips have distinctive features, I could provide you with a rendering of the top metal layer for each project, which you could then combine with a screenshot of the PCB and add the bond wire connections. Would it be fine if I provide you the images with their ID as names, so that you can automate the bonding diagram creation?

I already have the wirebonding detail added to the repo. https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs?tab=readme-ov-file#wirebonding-detail All chips have the QR code as pin0 marking yes?

GitHub - wafer-space/chip-on-board-wire-bonded-pcbs: Wire bonded ch...

Wire bonded chip on board PCB designs. Contribute to wafer-space/chip-on-board-wire-bonded-pcbs development by creating an account on GitHub.

@Andrew Wingate Need that diagram for each die picture so the tech can recognize the orientation with what the die physically looks like.

tnt

@Andrew Wingate Need that diagram for each die picture so the tech can recognize the orientation with what the die physically looks like.

We have the QR code as pad 0 marker. The reels will be coming fully marked

Also we will need them for the non-full-size die too

@stuart - I have been assuming that the non-full size die would be a "figure out when the first full size die are currently running successfully".

Ok cool, makes sense. @Leo Moser (mole99) had offered to help with the bonding diagrams with some scripting so I thought it would make sense for him to do all of them at the same time

Leo Moser (mole99) started a thread. 2026-03-26 1:02 p.m.

Hello everyone, could you briefly explain what the issue is here? I am not that deep into the technical details and would like to understand it better.

Andrew Wingate

I already have the wirebonding detail added to the repo. https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs?tab=readme-ov-file#wirebonding-detail All chips have the QR code as pin0 marking yes?

@Andrew Wingate excuse my ignorance, but I noticed that in the bonding diagram, the lines are connected between the black squares and not the "actual pads". Is that just for cosmetic reasons or is there a separate step to bond the black squares to the actual pads? Also, just to be clear based on the image, the QR code should be on the northeast corner of the COB (corner with the wafer.space logo)? We had assumed that the on-chip wafer.space logo location would correlate to the same corner wafer.space logo location on the COB.

asc

@Andrew Wingate excuse my ignorance, but I noticed that in the bonding diagram, the lines are connected between the black squares and not the "actual pads". Is that just for cosmetic reasons or is there a separate step to bond the black squares to the actual pads? Also, just to be clear based on the image, the QR code should be on the northeast corner of the COB (corner with the wafer.space logo)? We had assumed that the on-chip wafer.space logo location would correlate to the same corner wafer.space logo location on the COB.

At the end of the day these pictures and diagrams are used to display intent to a human who programs the machine. At no point are any of these actually used directly for anything.

1

12:20 a.m.

Also way at the beginning when we were talking about defining different projects, we ended up with the qr code as the fiducial and information carrier. The logo was added after afaiu and there was some inadvertant overlap as I used the waferspace logo as a large fiducial without knowing there was another conflicting mark on the dies themselves

Ok no worries. Is it reasonable to have the mosbius chip bonded with the QR code on the southwest corner or would it be better to fix the COB to match with the standard bonding orientation?

If they used the same pad template they are all the same.

We have the same pad template but different pads for ground and vdd

12:27 a.m.

The same 17x20 pads but for example, our vdds are at pads 29 and 30. So im afraid that wrong orientation would tie two unique analog pads together if flipped.

The pins and pads should all be correct the way that it is. If you want it in the sw corner just flip the whole thing 180deg.

asc

The same 17x20 pads but for example, our vdds are at pads 29 and 30. So im afraid that wrong orientation would tie two unique analog pads together if flipped.

Also you guys are designing your own COB chip yes? Just make your changes there

Sorry, to be more clear, im asking if the QR code absolutely needs to be in the ne corner for bonding? In that case, we will alter our COB (like you said, just rotate 180). If we can bond the die with the QR code in the sw corner, which we had assumed when creating our COB, we don't need to alter our current COB.

I see, for the sake of continuity and the fact there is a human in the loop. I would strongly suggest that you adhere as closely to the others as possible

Got it, no worries. We will alter our design. Thank you

If you all have the mosbius logo as your pin1 marker, that's fine. Just make it upside down so it's in the corner however you like once it's put on your motherboard

1

Hi @Andrew Wingate and @Tim 'mithro' Ansell, We have finished design of our own COB (the QR code on chip should now be at NE corner), and generated Gerber & Drill Files (in 'Gerber_Drill_Files' folder), everything is uploaded to GitHub Repo (https://github.com/mosbiuschip/WaferSpace_COB_70pins/tree/xp/V3_COB_Original/V3_COB_Original). Any feedback or comments to the design are appreciated. I would also like to double check that I can direcly submit the design in this discord channel or are there other places where I can submit/upload the files ? Thanks for the support. (edited)

ReJ aka Renaldas Zioma

I wonder if that is a real thing

Evergreen Semiconductor Materials and Spectrum Semi both sell ceramic package cavities. One of the challenges is getting lids but if you don't care about hermetic sealing you can have flat lids cnc'd and then you can glue them down if it's a low volume prototype situation. (edited)

Adrienne

Evergreen SemiConductor Materials Inc. 408-238-0200

Evergreen is committed to sourcing the highest quality materials. All our materials are sourced directly from ISO Certified manufacturers who certify their products comply with the requirements of RoHS, REACH, and Non-Conflict Minerals. We confirm to ISO9001:2008 and AS9120:2009 Standards.

those PGA packages make me nostalgic but I bet they're not cheap