wafer.space Community

Andrew Wingate

A batch of test harness boards have been created Again, these are for testing the bonds and the reason for so many is we have them time out after a number of tests to keep connectors from wearing out.

I've pinged HCTL to see if they have anything like an industrial connector with higher mating cycle rating that we could use - or any other solution they can suggest for testing

what about a massive array of pogo pins lol

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probe cards say hi

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BreakingTaps

probe cards say hi

Wow!!! Haha

woa that looks insane

kris

what about a massive array of pogo pins lol

Pogopins just swap one headache for another. Every PCB would need probing pads, which complicates the COB PCB layout, and design changes may require creating new fixtures. And also alignment gets tricky as we'd want to test CoBs while they're in the panel, but some get pulled out during wirebonding, so we might need two different fixtures for the same PCB. The current connector isn't as durable, but it works for every design we make, and we (can) have plenty of those adapter boards for now.

Lauri

Pogopins just swap one headache for another. Every PCB would need probing pads, which complicates the COB PCB layout, and design changes may require creating new fixtures. And also alignment gets tricky as we'd want to test CoBs while they're in the panel, but some get pulled out during wirebonding, so we might need two different fixtures for the same PCB. The current connector isn't as durable, but it works for every design we make, and we (can) have plenty of those adapter boards for now.

Tell us how you really feel

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Andrew Wingate

Tell us how you really feel

pins and needles

Lauri

Pogopins just swap one headache for another. Every PCB would need probing pads, which complicates the COB PCB layout, and design changes may require creating new fixtures. And also alignment gets tricky as we'd want to test CoBs while they're in the panel, but some get pulled out during wirebonding, so we might need two different fixtures for the same PCB. The current connector isn't as durable, but it works for every design we make, and we (can) have plenty of those adapter boards for now.

ohh i didn't know they got tested whilst on the panel, i figured that the reason you wouldn't want to swap is because you're also testing the connector itself here tbh i was thinking of this (https://www.raspberrypi.com/products/cm5-programming-jig/) when i mentioned it lol

Buy a Raspberry Pi Compute Module 5 Programming Jig – Raspberry Pi

A single-head provisioning system designed to program Raspberry Pi Compute Module 5

Andrew Wingate

Wow!!! Haha

yeah probe cards are nuts. had a friend who helped manufacture them, crazy expensive too. Used to be cantilever probes assembled onto PCBs, but over time they've moved to MEMS pins and photochemically-etched bumps/tabs due to density requirements. think they are used to test wafers more often than finished/packaged chips though.

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BreakingTaps

yeah probe cards are nuts. had a friend who helped manufacture them, crazy expensive too. Used to be cantilever probes assembled onto PCBs, but over time they've moved to MEMS pins and photochemically-etched bumps/tabs due to density requirements. think they are used to test wafers more often than finished/packaged chips though.

That's so cool!!

kris

ohh i didn't know they got tested whilst on the panel, i figured that the reason you wouldn't want to swap is because you're also testing the connector itself here tbh i was thinking of this (https://www.raspberrypi.com/products/cm5-programming-jig/) when i mentioned it lol

The connector based design has already helped us catch some bad soldering and bent pins. While pogopin jigs are cool, we have plenty of different designs and some CoBs use custom PCB and making jigs every custom board doesn't seem feasible. For now, connector based testing keeps it simple and flexible. Also, as @Tim 'mithro' Ansell mentioned, in the future we may offer CoB testers to the community so a connector based design will definitely help to keep the cost down.

Lauri

The connector based design has already helped us catch some bad soldering and bent pins. While pogopin jigs are cool, we have plenty of different designs and some CoBs use custom PCB and making jigs every custom board doesn't seem feasible. For now, connector based testing keeps it simple and flexible. Also, as @Tim 'mithro' Ansell mentioned, in the future we may offer CoB testers to the community so a connector based design will definitely help to keep the cost down.

thanks for the info, definitely got it thought through lol

BreakingTaps

yeah probe cards are nuts. had a friend who helped manufacture them, crazy expensive too. Used to be cantilever probes assembled onto PCBs, but over time they've moved to MEMS pins and photochemically-etched bumps/tabs due to density requirements. think they are used to test wafers more often than finished/packaged chips though.

I can smell the hole in the bank account from here.

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1

Bond tester update: smarter, more die-agnostic testing Sorry for the long post. TLDR

Neighbouring-bond short check removed
New 10 µA and 1000 µA test currents for much clearer ESD diode detection
Pseudo-Kelvin (3-wire) measurement: force and sense paths separated through the MUX
Results simplified to OPEN / GOOD, the tester no longer judges shorts
Power pads now tested via capacitor charging curve monitoring Design principle: the tester knows less* about die

Two of these changes come from the same place. A generic tester shouldn't assume anything about the die under test:

Neighbour short check removed. We previously used spare MUX channels to check neighbouring bonds. But we've already seen this backfire on a real die: one of the designs we tested has DVSS on adjacent pads, so a perfectly good die looks like it has a short. A generic tester can't distinguish "shorted by design" from "shorted by a bond defect," so the check is gone.
Results are now just OPEN or GOOD. The tester confirms a bond exists by comparing the measurement against a wide acceptance threshold; it doesn't interpret the result in detail. For example, on analog designs an IO pad may be replaced with a power pad (e.g. GND) on an otherwise standard CoB board. Measuring that pad could look like a short to a supply rail, but it's by design, not a failure. So the tester now answers one question: is it an open, or not? Better ESD diode detection

Added 10 uA and 1000 uA current sources alongside the existing one. Now have ~10uA, ~100uA, ~1000uA. They're simple resistor-based sources and not precision-calibrated, but that's fine for v1: this revision is a platform for us to learn on and improve our detection, and with the extra measurement points a diode is now much easier to detect. Pseudo-Kelvin measurement We had a free COM output on the MUX, so might as well put it to use: the force (current injection) and sense (ADC reading) paths are now separated through the MUX, instead of the ADC probing the current-source node directly. This removes the force-path MUX on-resistance from the measurement. It's not true 4-wire Kelvin, effectively 3wire: the return path is still shared through the MUX, so the return-leg R_on still contributes, as do the connector and its contact resistance. Fully removing those would need a separate sense contact per pad, and pogo pins would be a suitable way to achieve this

. But let's try to leave that to next year. For our simple pass/fail testing, the current setup does the job. Power pads: capacitor charging curve Power pins used to cause trouble because of the decoupling capacitors on the PCB. Instead of fighting that, the tester now measures the charging curve itself: a good bond connects the pad to the die, whose ESD diode clamps the voltage before the capacitor charges fully. An open bond has no such clamp and lets it charge to full. What's next I expect there are still plenty of surprises waiting once we start bonding more CoBs. So far I've only managed to test a handful of different dies, and with new upcoming CoBs I expect the tool to fail in new ways, which is a good thing: every failure shows how to make the tester better and more universal. Once the run 1 CoBs are done, we should be in a good position for an updated PCB design. Longer term, I'd like to keep improving the tester, with upgrading the current sources and the ADC at the top of the list. If you have any questions or suggestions, please feel free to leave a reply

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I'm wondering if it'd be useful to allow customers to provide a specific test profile for their chips. In the failed TT samples I got, several had shorts to GND and not detecting them seems not a good idea ...

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tnt

I'm wondering if it'd be useful to allow customers to provide a specific test profile for their chips. In the failed TT samples I got, several had shorts to GND and not detecting them seems not a good idea ...

Can you elaborate a bit? Such as what tests would you like to see? Would this be some json blob or something?

5:29 p.m.

also, are you sure those were ever tested? TT got a bunch of the first stuff, so I assume you got the rawest of the raw

Maybe a simple step would just be for the customer to indicate whether any changes have been made to the power pad config compared to the default padframe - i.e. whether any IO pins have been replaced with power/ground, or whether any power/grounds have been switched around? It sounds like if the design uses the default setup then the more enhanced checks could be used safely.

Yeah like a json describing expected pad type for instance ( GND / PWR / IO ) or even IV curve bounds if you want to go that far.

Thank you @tnt, @Andrew Wingate , @RebelMike for your responses. I also, at some point thought it would be very useful to know the pads and their functions before testing. But I came to the conclusion that it would be very time consuming to collect this information and then create and validate the tests, and after a run, throw them away and start over for the next one. That's why I'm trying to lean toward having less die specific knowledge. It makes more sense to measure first, then analyze the results later (re: below). re: customer pad config Relying on user provided config is not ideal. Perhaps the platform can figure out the pad types automatically? I'm not familiar with the inner workings of the platform, but maybe someone more familiar with it can confirm?

even IV curve bounds if you want to go that far.

Custom IV curves raise a yield question: if a wrong curve is provided, the tester fails every CoB and the customer gets near 0% yield. A wrong customer provided spec shouldn't be able to make hard pass/fail decisions at test time. My suggestion is to add filtering capability to the results website. By applying filters to the CoB test results, it would be possible to find the CoBs that match the required curve. This kind of post-test analysis would also enable another useful feature: once all CoBs are tested and measured, the site could reveal outliers and flag potentially faulty ones.

Sure, I agree that the ability to save all results and analyze later is better, but this creates an inventory and data management burden since now every COB needs individual ID and tracking.

Also keep in mind the PCB for all the cob must be the standard. So that limits what kind of variability there would be from the outset. I was more curious what you were suggesting?

tnt

Sure, I agree that the ability to save all results and analyze later is better, but this creates an inventory and data management burden since now every COB needs individual ID and tracking.

Currently the panels have ID-s and CoBs in the panel have their position. Basically as long as panel is intact you can find the CoB's test results easily. For later runs I think we are exploring option to get unique id's printed on the CoB's themselves. Overrall, data is good and afaik we have space to store data.

Well limits yes and no. GND pins are shorted so those need to be gnd. But a user could add more if they wanted to. Power pins have decoupling, but are separate so user could use them for power but also for internal bias and those have different IV curves and they could also use them for very high or very low internal bias and use pads without some of the diodes for instance.

Basically we have 2 directions: 1. [current] stay generic, focus on basic 'is there a wire between PCB pad and die pad'. During manufacturing the testing will pass CoB's with wirebonds. Later, when analyzing the results, more die-specific conditions can be applied and the best CoBs selected. 2. go more die specific. Platform will provide pad types and expectected characteristics. The tester needs to know exactly what is being tested and how to test it. I think making a run or two with current generic testing will provide us valuable data and lessons on feasibility of die specific testing.

2:12 p.m.

Could always offer a more expensive CoB packaging option that would allow custom testing options??

Does anyone have a working 1-edge pad ring template for the long edge of the quarter slot?

Thanks for the update @Lauri. A few more minor questions: 1) I too would be very interested in getting my hands on your tester (custom configurations and false fails are no issue). Are there any plans of having the tester included with the CoB packaging option long term ? 2) Was the neighboring short check removed because it was wrong ? Or was it primarily done because it relied on none generic information ? Comments: A) I found your yield dataset very interesting and useful, I would be really appreciative it you could please keep uploading to it.

Essen

Thanks for the update @Lauri. A few more minor questions: 1) I too would be very interested in getting my hands on your tester (custom configurations and false fails are no issue). Are there any plans of having the tester included with the CoB packaging option long term ? 2) Was the neighboring short check removed because it was wrong ? Or was it primarily done because it relied on none generic information ? Comments: A) I found your yield dataset very interesting and useful, I would be really appreciative it you could please keep uploading to it.

1) Doubtful, but I do think we're planning on including one of the header motherboards so you can do real testing simply. 2) I will defer to Lauri A) We plan to continue sharing what we can as more info allows us all to improve. Thanks

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Andrew Wingate

1) Doubtful, but I do think we're planning on including one of the header motherboards so you can do real testing simply. 2) I will defer to Lauri A) We plan to continue sharing what we can as more info allows us all to improve. Thanks

1) Noted. Are the plans of the tester available by any change so we can build our own? Because shorted pins could damage the boards, so this might call for a separate board for testing to be safe. (edited)

Archit3ch (George)

Does anyone have a working 1-edge pad ring template for the long edge of the quarter slot?

https://github.com/MichaelBell/ws02-minimal-tinyQV uses a single edge on a quarter slot. Whether it works is yet to be seen

I think the pad config script that removes unused edges is all merged into the template now so it should just happen automatically if you remove all the pins from the three unwanted sides. However, as is this leaves the corners adjacent to the used edge in place, so might not be exactly what you want. (edited)

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Ah, I guess you were thinking of a CoB board for that design. I don't have one of those yet but I intend to make one

Essen

1) Noted. Are the plans of the tester available by any change so we can build our own? Because shorted pins could damage the boards, so this might call for a separate board for testing to be safe. (edited)

Slight update here re (1) - we are in fact planning on making up a few of the 'simple' (without camera) test boards and can send some out to people willing to do some testing and give feedback

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stuart started a thread. 2026-09-04 3:24 p.m.

Essen

Thanks for the update @Lauri. A few more minor questions: 1) I too would be very interested in getting my hands on your tester (custom configurations and false fails are no issue). Are there any plans of having the tester included with the CoB packaging option long term ? 2) Was the neighboring short check removed because it was wrong ? Or was it primarily done because it relied on none generic information ? Comments: A) I found your yield dataset very interesting and useful, I would be really appreciative it you could please keep uploading to it.

1) what @stuart said 2) It was due to 3 circumstances: 1. the dies we were testing in the beginning followed standard pad definitions. (all adjacent pad signals we're different0 2. poor wirebonding - initial bonding house often reworked the bonds manually and that lead to sometimes bonds being bent and very close to each other, if not touching. 3. having extra mux channels - first tester schematic used Analog's MUXs with 2 outputs for testing. Unfortunately due to export restrictions I couldn't source this part in China and had to switch to WCH CH446X MUX's. As the 2. was likely to happen in production, the next/previous test made some sense. Now as have better bonding houses, that feature is less relevant. Also, removing this, it conveniently freed up channels for different current tests. I think that was a good decision, as the bond is not judged based on 1 datapoint, but use 3 datapoints. 3) With all the hardware and software changes over the summer, the data format has changed couple of times. But now, I think it's stable enough that I'd be happy to upload more recent test results. I will probably make a simple document to go with the newer results. I can let you know once I've pushed new results?

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Lauri

1) what @stuart said 2) It was due to 3 circumstances: 1. the dies we were testing in the beginning followed standard pad definitions. (all adjacent pad signals we're different0 2. poor wirebonding - initial bonding house often reworked the bonds manually and that lead to sometimes bonds being bent and very close to each other, if not touching. 3. having extra mux channels - first tester schematic used Analog's MUXs with 2 outputs for testing. Unfortunately due to export restrictions I couldn't source this part in China and had to switch to WCH CH446X MUX's. As the 2. was likely to happen in production, the next/previous test made some sense. Now as have better bonding houses, that feature is less relevant. Also, removing this, it conveniently freed up channels for different current tests. I think that was a good decision, as the bond is not judged based on 1 datapoint, but use 3 datapoints. 3) With all the hardware and software changes over the summer, the data format has changed couple of times. But now, I think it's stable enough that I'd be happy to upload more recent test results. I will probably make a simple document to go with the newer results. I can let you know once I've pushed new results?

Nice, thanks for the update. 1) I would be very interested in eventually testing out the simple test board if you need volunteers. 2) Thanks for the info, this makes perfect sense. 3) Please do, I am looking forward to it as I have a small data analysis tool on my end that I have been running. I will update these to accommodate the new test format. Also, don't stress too much about doc, I will figure it out.

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Archit3ch (George)

Does anyone have a working 1-edge pad ring template for the long edge of the quarter slot?

I believe @RebelMike was doing a test of something like that in Run #2?

BreakingTaps

yeah probe cards are nuts. had a friend who helped manufacture them, crazy expensive too. Used to be cantilever probes assembled onto PCBs, but over time they've moved to MEMS pins and photochemically-etched bumps/tabs due to density requirements. think they are used to test wafers more often than finished/packaged chips though.

@digshadow - I know you are a fan of probe cards

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Lauri

Bond tester update: smarter, more die-agnostic testing Sorry for the long post. TLDR

Neighbouring-bond short check removed
New 10 µA and 1000 µA test currents for much clearer ESD diode detection
Pseudo-Kelvin (3-wire) measurement: force and sense paths separated through the MUX
Results simplified to OPEN / GOOD, the tester no longer judges shorts
Power pads now tested via capacitor charging curve monitoring Design principle: the tester knows less* about die

Two of these changes come from the same place. A generic tester shouldn't assume anything about the die under test:

Neighbour short check removed. We previously used spare MUX channels to check neighbouring bonds. But we've already seen this backfire on a real die: one of the designs we tested has DVSS on adjacent pads, so a perfectly good die looks like it has a short. A generic tester can't distinguish "shorted by design" from "shorted by a bond defect," so the check is gone.
Results are now just OPEN or GOOD. The tester confirms a bond exists by comparing the measurement against a wide acceptance threshold; it doesn't interpret the result in detail. For example, on analog designs an IO pad may be replaced with a power pad (e.g. GND) on an otherwise standard CoB board. Measuring that pad could look like a short to a supply rail, but it's by design, not a failure. So the tester now answers one question: is it an open, or not? Better ESD diode detection

Added 10 uA and 1000 uA current sources alongside the existing one. Now have ~10uA, ~100uA, ~1000uA. They're simple resistor-based sources and not precision-calibrated, but that's fine for v1: this revision is a platform for us to learn on and improve our detection, and with the extra measurement points a diode is now much easier to detect. Pseudo-Kelvin measurement We had a free COM output on the MUX, so might as well put it to use: the force (current injection) and sense (ADC reading) paths are now separated through the MUX, instead of the ADC probing the current-source node directly. This removes the force-path MUX on-resistance from the measurement. It's not true 4-wire Kelvin, effectively 3wire: the return path is still shared through the MUX, so the return-leg R_on still contributes, as do the connector and its contact resistance. Fully removing those would need a separate sense contact per pad, and pogo pins would be a suitable way to achieve this

. But let's try to leave that to next year. For our simple pass/fail testing, the current setup does the job. Power pads: capacitor charging curve Power pins used to cause trouble because of the decoupling capacitors on the PCB. Instead of fighting that, the tester now measures the charging curve itself: a good bond connects the pad to the die, whose ESD diode clamps the voltage before the capacitor charges fully. An open bond has no such clamp and lets it charge to full. What's next I expect there are still plenty of surprises waiting once we start bonding more CoBs. So far I've only managed to test a handful of different dies, and with new upcoming CoBs I expect the tool to fail in new ways, which is a good thing: every failure shows how to make the tester better and more universal. Once the run 1 CoBs are done, we should be in a good position for an updated PCB design. Longer term, I'd like to keep improving the tester, with upgrading the current sources and the ADC at the top of the list. If you have any questions or suggestions, please feel free to leave a reply

Can you share some of the reports that the tester has been producing? I know there was https://github.com/wafer-space/ws-run1-cob/ and https://wafer.space/ws-run1-cob/ but that doesn't seem to have been updated recently? There also seems to be https://data.wafer.space/ten64-welland/lauri/public_html/run1-wb/ Can you also share the bond tester PCB/source code/etc?

GitHub - wafer-space/ws-run1-cob: Results from the wafer.space Run ...

Results from the wafer.space Run #1 chip on board packaging. - wafer-space/ws-run1-cob

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Tim 'mithro' Ansell

I believe @RebelMike was doing a test of something like that in Run #2?

Yes, Leo suggested I did a version of Tiny QV using pads on a single edge to test the tweaks he made to the pad ring script to remove unused edges

Essen

1) Noted. Are the plans of the tester available by any change so we can build our own? Because shorted pins could damage the boards, so this might call for a separate board for testing to be safe. (edited)

I'm hoping we can have the tester boards on sale for people to purchase. @stuart can keep you in the loop on that.

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Lauri

Basically we have 2 directions: 1. [current] stay generic, focus on basic 'is there a wire between PCB pad and die pad'. During manufacturing the testing will pass CoB's with wirebonds. Later, when analyzing the results, more die-specific conditions can be applied and the best CoBs selected. 2. go more die specific. Platform will provide pad types and expectected characteristics. The tester needs to know exactly what is being tested and how to test it. I think making a run or two with current generic testing will provide us valuable data and lessons on feasibility of die specific testing.

Sounds like we might need to increase / improve the CoB verification on the platform which makes sure the bond testing will work? @Leo Moser (mole99) - Thoughts? I'm okay with people doing custom / weird things needing to figure out their own bonding / testing plans -- they can always contract @stuart & @Lauri themselves for custom work.

@Essen, I've uploaded more data to https://github.com/wafer-space/ws-run1-cob/ (pages can be viewed at https://wafer.space/ws-run1-cob/).

Tim 'mithro' Ansell

Can you share some of the reports that the tester has been producing? I know there was https://github.com/wafer-space/ws-run1-cob/ and https://wafer.space/ws-run1-cob/ but that doesn't seem to have been updated recently? There also seems to be https://data.wafer.space/ten64-welland/lauri/public_html/run1-wb/ Can you also share the bond tester PCB/source code/etc?

Can you also share the bond tester PCB/source code/etc?

Tester PCB files https://github.com/szfate/BondTest72, firmware https://github.com/szfate/BondTest72-Firmware. PCB files haven't been updated since v1, but can do that in coming weeks as we're doing v1.1.

3:53 p.m.

@tnt re: latest bonding run, I grouped the test results by die pad to see how much deviation we can see and if it's possible to find outliers. This contains 100 CoB's test results: https://wafer.space/ws-run1-cob/BRWN/2026-09-02/BRWN-636-PADS.html

Lauri

@Essen, I've uploaded more data to https://github.com/wafer-space/ws-run1-cob/ (pages can be viewed at https://wafer.space/ws-run1-cob/).

Thanks so much ❤️

Leo Moser (mole99) started a thread. 2026-09-05 7:46 p.m.

Bonding diagrams for 0p5x0p5 and 0p5x1 dies.

2026-09-08_0p5x0p5_bonding_diagram_TQVA.pdf

1.06 MB

2026-09-08_0p5x1_bonding_diagram.pdf

1.29 MB

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Lauri

Bonding diagrams for 0p5x0p5 and 0p5x1 dies.

These look correct to me

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Thank you @Lauri

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Lauri

Currently the panels have ID-s and CoBs in the panel have their position. Basically as long as panel is intact you can find the CoB's test results easily. For later runs I think we are exploring option to get unique id's printed on the CoB's themselves. Overrall, data is good and afaik we have space to store data.

This was serialized per-board from JLC with me getting full assembled panels shipped. I specified a prefix and counter start value and they incremented the counter such that each board on the panel got it's own serial. You can do much smaller if you don't want as much entropy in your prefix.

tnt

Sure, I agree that the ability to save all results and analyze later is better, but this creates an inventory and data management burden since now every COB needs individual ID and tracking.

If they're in some simple vacuum formed tray or the like it should be easy to scan them for possible post-test sorting? But the major benefit would be unlocked without having to offer sorting based on test results: you could let whoever plugs them into the carrier boards hold them to a scanner that's loaded with the prefix and list of PASS serials, for example stock https://github.com/markusfisch/BinaryEye on Android supports 1024 long regexes for matching on which can hold many serials with even very simple minimization algorithms to reduce its size. Also I guess I should just file a feature request to increase that cutoff anyways not like there's a truly good reason for it to be so low (I've managed to run into it using it for PASS picking of HDDs after batch processing with some shell scripts spitting out serials of the different sorting classifications/grades)...

GitHub - markusfisch/BinaryEye: Yet another barcode scanner for And...

Yet another barcode scanner for Android. Contribute to markusfisch/BinaryEye development by creating an account on GitHub.

namibj

This was serialized per-board from JLC with me getting full assembled panels shipped. I specified a prefix and counter start value and they incremented the counter such that each board on the panel got it's own serial. You can do much smaller if you don't want as much entropy in your prefix.

We're adding JLC's serials to top silk but so far the results have not been reliable. Our designated area for serial number is kind of small and the printed surface is not flat (re traces and vias underneath), making these difficult to read. I've attached couple of pictures I could quickly find to show what results we've seen recently:

sometimes they ignore their own requirement (re: rectangle area)
our PCB design had untented vias making the serial unreadable
iirc we even received 2 panels with same serial numbers. I think we'll continue to add these serials to the PCBs and if results improve or become more consistent then it would be great to actually use these serials one day

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Lauri

We're adding JLC's serials to top silk but so far the results have not been reliable. Our designated area for serial number is kind of small and the printed surface is not flat (re traces and vias underneath), making these difficult to read. I've attached couple of pictures I could quickly find to show what results we've seen recently:

sometimes they ignore their own requirement (re: rectangle area)
our PCB design had untented vias making the serial unreadable
iirc we even received 2 panels with same serial numbers. I think we'll continue to add these serials to the PCBs and if results improve or become more consistent then it would be great to actually use these serials one day

don't use human readable ones, given the space nature I'd suggest a rectangular datamatrix

1:41 a.m.

do you have an image of the backside of the COB on hand by chance?

1:42 a.m.

....they don't offer rectangular datamatrix codes

so yeah 5x5mm it is

1:43 a.m.

you shouldn't get repeat numbers unless you order such; they should be at most wasting IDs by panels that get scrapped before they're delivered

namibj

do you have an image of the backside of the COB on hand by chance?

Not much space here either

oh yeah there's space for a 5x5mm I'd feel?

1:43 a.m.

or not enough again?

1:44 a.m.

ofc needs to be tented then

1:45 a.m.

to depend on it I'd always do the approve production files thing and get them to confirm the code target area was registered as such.

1:50 a.m.

yeah best idea then I guess would be an extra large font size alphanum rectangle with a minimal serial number on one side of the plug (backside) and a panel/board version encoding identifier on the other side of that connector; think like 1 or 2 rows of text in as big of a font as fits between the capacitors and the mezzazine solder pads with just enough gap to each of those two to be not too sensitive to the angle it's photographed from regarding those obscuring the text from the camera's view.

1:51 a.m.

didn't quite realize how limited the space is on these quite minimal size boards.....

1:52 a.m.

also giant benefit of back side is that it's not gonna suffer lensing/refraction distortion from the cover goop spreading over the ID text

1:54 a.m.

if anyone wants a front side ID it could be a sticker on the front side in a corner

1:54 a.m.

(the adhesive of which could be selected in thickness to take care of the underlying height differences that come from the traces/vias)

1:59 a.m.

so yeah best of luck it does seem substantially harder here than I had hoped. You may consider putting a perhaps DIY-rendered datamatrix code like their ID would be in a place where it could fit to trial scannability of it

2:00 a.m.

(on one strip on the back side)

namibj

so yeah best of luck it does seem substantially harder here than I had hoped. You may consider putting a perhaps DIY-rendered datamatrix code like their ID would be in a place where it could fit to trial scannability of it

Anything DIY won't index. All the ones JLC do, index even within the panel (edited)

one of the corners top side might sacrifice it's ground-plane-ness to use it's copper resolution and superior printing-reliability to manufacture a version ID code, especially if ENIG with solder mask exclusion zone.

Having serials or barcodes on bottom side will make it difficult to scan. Factory testing tool has camera that's looking at the globtop. It would be difficult to add a camera on bottom side

2

Andrew Wingate

Anything DIY won't index. All the ones JLC do, index even within the panel (edited)

I'm aware but you can still trial printing reliability this way to a substantial extend. OFC finer pixel-interacts-with-background-structure effects won't be caught, but you'd retain the use of printing large font alphanumeric serial during it

Lauri

Having serials or barcodes on bottom side will make it difficult to scan. Factory testing tool has camera that's looking at the globtop. It would be difficult to add a camera on bottom side

mirror

need to consider the mating height

and I wouldn't suggest if I'd see a place where it could reasonably fit with large enough font to not be itself a substantial yield impact

Lauri

need to consider the mating height

can't the factory tester use a tall one and/or have the interposer board that's a consumable be laid out to let the COB overhang enugh that the mirror could extend below the interposer board?

2:08 a.m.

(I'm not saying trivial but unless you can get them to do a big fat 2-row 10-column hamming coded binary ID on the front with their serializing uniquness I don't see how you're gonna get much beyond 2 nines of yield from the front side serial ID print....)

2:09 a.m.

the blue board approach might kinda lacking enough samples to really tell

2:10 a.m.

might require plated over vias to be reliably readable print; I'm not sure if that's COB compatible pricing at the COB run quantities to be offered at Run2.

@namibj / @Lauri / @stuart - I was wondering if NextPCB's rev0 service where everything is supposedly automated / computer controlled rather than human might make the IDs more reliable or something? I don't think we know what the cost difference between them and JLC PCB would be at the moment?

oh AFAIK the questionable step at JLC is at the up front engineering human treatment/review

2:58 a.m.

I would not rule them out unless they tell you they can't promise that/work out a way that allows it to be promised.

2:59 a.m.

there should be pretty much no reason they can't promise to re-make a board they already did just with fresh IDs for e.g. the next customer code on your side and appropriate non-overlapping serials unique on each COB.

3:00 a.m.

the rest of JLC is very much automated

Tim 'mithro' Ansell

@namibj / @Lauri / @stuart - I was wondering if NextPCB's rev0 service where everything is supposedly automated / computer controlled rather than human might make the IDs more reliable or something? I don't think we know what the cost difference between them and JLC PCB would be at the moment?

I'd suggest to do a single board (not a full panel) through their process to see how it prints, assuming they have decent pricing for that workload?

namibj

I'd suggest to do a single board (not a full panel) through their process to see how it prints, assuming they have decent pricing for that workload?

Generally to see how this stuff works you need to do X number of panels - otherwise you don't see the issues we are seeing from JLC PCB...

1

oh well sure for overall organizational reliability sure; but I mean whether they even manage to get the serials printed in good enough print quality to make that even be useful. Good organization doesn't help if the print quality is unreadable

(edited)

Lauri

@tnt re: latest bonding run, I grouped the test results by die pad to see how much deviation we can see and if it's possible to find outliers. This contains 100 CoB's test results: https://wafer.space/ws-run1-cob/BRWN/2026-09-02/BRWN-636-PADS.html

talked with @Tim 'mithro' Ansell about test results earlier today and that reminded me of an interesting finding in this 100 CoB test results worth sharing. The diode IV curve outlier detection flagged 20 CoBs. All of them are from panels 000 and 001. Panels 000 and 001 have black globtop, while panels 002-009 have soft clear globtop. Picture attached Kind of interesting how the globtop material (or perhaps light, as Tim suggested) has an effect on the IV curve measurements.

1

10:04 a.m.

Did you try covering a clear top one ?

tnt

Did you try covering a clear top one ?

No, I haven't retested these CoB's

tnt

Did you try covering a clear top one ?

My idea also, I believe I heard somewhere that every diode is a photodiode...

3

Just tried on one of the hackaday badge we made. When you measure with a multimeter at a fixed 1mA current you don't see much difference.

12:55 p.m.

But if instead you apply a constant voltage at the beginning of the conduction ( say ~ 0.3~0.4V ), then the current changes drastically when covering it or not.

12:56 p.m.

Interestingly the current drops if you shine light on it.

1

@tnt is this badge for only for hackaday europe or will it be used for the one coming up on in pasadena as well?

ah I see it was not for the main badge but a goodie bag thing

@m_w Yeah it was just a TT goodie in the bag

I think it was just HaD europe and IIUC correcly we'll give extra left over to people at ORConf.

ohhh orconf is tomorrow

The boards are the reason I ended up at HaD europe

1

Generated bonding diagrams for run1 and run2 dies: https://github.com/szfate/ws-bonding-diagrams (pdfs included).

GitHub - szfate/ws-bonding-diagrams: wafer.space bonding diagrams

wafer.space bonding diagrams. Contribute to szfate/ws-bonding-diagrams development by creating an account on GitHub.

1

Chips4Makers aka Staf Verhaegen

My idea also, I believe I heard somewhere that every diode is a photodiode...

Yes, I've heard that said before too

tnt

But if instead you apply a constant voltage at the beginning of the conduction ( say ~ 0.3~0.4V ), then the current changes drastically when covering it or not.

@BreakingTaps @Ethan Mahintorabi - I think this might prove that is could be possible to do some type of photo diode on GF180MCU?

2

What are the Circuit-Under-Pad rules for wire bonding? GF180 limits only mention wedge bonding and ball bonding.

Wedge and Ball are the two ways to do wire bonding ...

Archit3ch (George)

What are the Circuit-Under-Pad rules for wire bonding? GF180 limits only mention wedge bonding and ball bonding.

Yeah, I'm not sure I understand the question either, but last I knew both die and cob side were both wedge bonded.

Assuming the option you can buy in Wafer Space is wedge, the guidelines say no circuit under pad, correct?

Archit3ch (George)

Assuming the option you can buy in Wafer Space is wedge, the guidelines say no circuit under pad, correct?

Can you share where you're seeing these guidelines?

https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_3.html

12:01 p.m.

And you're correct, no CUP is allowed when using wedge bonding.

1

I just spoke with @Stephan Bökelmann about wire bonding and associated things - hoping that he will be able to give some useful insights based on his experience doing interesting COB stuff. Welcome Stephan

Hey everyone! Thank you @stuart for the invite. To everyone that hasn't met me before, my name is Stephan (@Stephan Bökelmann). I am working as a freelancer in data-acquisition-electronics. Additionally I am part of the HV-MAPS mixed-signal asic team at the chair of experimental hadron physics in Bochum, designing, bonding, testing chips for CERN, NASA and FAIR Great to be here

4

1

@Stephan Bökelmann - You are the guy talking about wire bonding at KiConn?

Tim 'mithro' Ansell

@Stephan Bökelmann - You are the guy talking about wire bonding at KiConn?

That's right! And since my session yesterday with @stuart, I guess I will prepare another talk about my <xxx>.cob.json file workflow for documenting bonding parameters and EDA landpatterns

1

Update on CoB testing Yesterdays test results have been uploaded to GitHub: https://github.com/wafer-space/ws-run1-cob. Individual reports are here: https://wafer.space/ws-run1-cob. Tested:

JKU1: 20 pcs, 100% yield
GD02: 20 pcs, 95-100% yield
- first 0.5x1 CoBs
- will retest the failing CoB tomorrow
MOSB: 200 pcs, 97.5% yield
- 5 failed CoBs
- 3 missing wirebonds
Tester issue: flaky connector pin

Ran into a problem with some of the newly assembled adapter boards. Pin 1 on the connector between the adapter and the tester seems to have no connection. That contact pin feels 'softer' compared to the others. Not sure yet if this is a general connector quality problem or a compatibility issue between the tester (Hirose) and the adapter mating connectors. New testers should have mating connectors from the same company as the adapters. My current workaround for this is to insert a tiny piece of foam inside the connector, pushing the pin into contact. (edited)

GitHub - wafer-space/ws-run1-cob: Results from the wafer.space Run ...

Results from the wafer.space Run #1 chip on board packaging. - wafer-space/ws-run1-cob

1:18 p.m.

The 3 missing bonds.... and some bubbles

1

Lauri

talked with @Tim 'mithro' Ansell about test results earlier today and that reminded me of an interesting finding in this 100 CoB test results worth sharing. The diode IV curve outlier detection flagged 20 CoBs. All of them are from panels 000 and 001. Panels 000 and 001 have black globtop, while panels 002-009 have soft clear globtop. Picture attached Kind of interesting how the globtop material (or perhaps light, as Tim suggested) has an effect on the IV curve measurements.

Can you share a picture of how the testing bench looks with the light setup/situation at hand?

Tim 'mithro' Ansell

@BreakingTaps @Ethan Mahintorabi - I think this might prove that is could be possible to do some type of photo diode on GF180MCU?

Oh thanks for reminding of that (again); we definitely should see to get a decent variety of photodiodes as test structures onto Run3. I'll see if I can find some COTS lasers that are more suited to fiber coupling than this https://ams-osram.com/products/lasers/ir-lasers-vcsel/osram-bidos-e1005-l-plpvyl1-940a-e (the cuboid is 500x500x1000 μm; the triangle of green circles are the three VCSEL diodes; this part is notable for being low cost and vaguely-decently couple-able into a cheap multimode fiber. "Should" just need a coupling lens on the end of the multimode fiber; it's (1/e²) beam divergence is given at 18° typ 25° max and reading the intensity plot in the datasheet the full width half maximum is about 8.5°), so I could try to approximately target having an on-die photodiode good for fiber data communications with a suitable low cost VCSEL diode transmitter. Notably vague ideas of brightness and less vague ideas of beam size and spectrum matter.

tnt

Interestingly the current drops if you shine light on it.

In case you weren't quite aware how photovoltaic mode works/acts: the PN diode when subjected to individual photons in it's absorption spectrum (AFAIK mostly this means "of energy exceeding the band gap but not far excessively so"; for silicon we're talking UV (A, probably B, maybe even C and somewhat exceeding that) to about 1000 nm. IIRC Nd:YAG's 1064nm is just a little too far.): There is an inversion zone where charge carriers aren't nearly as free as in the notably doped p and n zones. A photon hitting there knocks an electron out and spawns an electron/hole pair. Due to this very inversion zone those two charges drift off to the p and n zones, respectively. Electrons drift to the N side. This pair creation itself is essentially proportional to the incoming photons and mostly just cares about how likely it is for the photon to hit in this reception zone. One photon only creates one pair. If left open-circuit, these electrons on the N doped side accumulate until they discharge the very same way they would under regular forward bias conditions. This is why solar cells have more output voltage in winter (diode forward voltage temp co) and why the external current at a fixed forward bias voltage drops when you apply more light: you're substituting the current with photocurrent. If you want to see current go up as light goes bright, you'll have to reverse-bias the PN junction. Note: the photocurrent from the light still flows the same direction through the "simplified small signal silicon PN diode model", but due to the forced inverted bias the bias current is now flipped in sign at the internal diode and thus the external view seems to be one of "current go up as light goes bright". For response speed you btw. want to stay in reverse bias due to the inversion layer between the P and N widening and this reducing the capacitance (simple plate capacitor approximation). Ideally you'd have been able to measure current flow proportional to brightness (as far as thermal conditions can be approximated as constant) with the diode shorted into the current meter, i.e. 0V applied. Could you just for clarity tell me what you meant exactly with the "measure with a multimeter at a fixed 1mA current"? Measure what? Current from where?

1

namibj

Can you share a picture of how the testing bench looks with the light setup/situation at hand?

Couldn't find any recent photos, just this one from June testing run at the cob factory. Current setup is same except ring light is back on the lens.

1

Lauri

Couldn't find any recent photos, just this one from June testing run at the cob factory. Current setup is same except ring light is back on the lens.

Hmm, yeah, pretty bright then.

Hey there! So @stuart asked me how I prepare my PCBs for my chips. Over the past years, I gathered some ideas and today I took the time to piece them together and finally put them into a public repository. The toolset is centered around a file I called .cob.json. Maybe this is interesting or helpful for some of you. Please let me know what you think. You should be able to try it with your own GDSII files, place PCB pads and export it to a kicad schematic + footprint. You can also use the exporter from KiCad to use the sym and fp in Altium. Here is a writedown: https://maxclerkwell.tech/posts/open-cob-json-september-2026/ Here is the repo: https://github.com/MaxClerkwell/open.cob.json I will add a wire-editor into my cobedit tool soonish, but so far I have figured out the wire-geometry as well as the bonding-parameters along the way.

open.cob.json: One File Between the Chip Designer and the PCB Designer

For years I kept my chip-on-board bonding notes in private JSON files. A conversation with wafer.space made me publish them as a format. This is the story of the decisions that were hardest to make: none versus unspecified, why pad shapes are their own files, and what a real padframe taught the p...

GitHub - MaxClerkwell/open.cob.json: Open, machine-readable exchang...

Open, machine-readable exchange format for chip-on-board wire bonding: die pads, PCB pads, wires. Generates KiCad symbols and footprints. - MaxClerkwell/open.cob.json

2

1

namibj

Oh thanks for reminding of that (again); we definitely should see to get a decent variety of photodiodes as test structures onto Run3. I'll see if I can find some COTS lasers that are more suited to fiber coupling than this https://ams-osram.com/products/lasers/ir-lasers-vcsel/osram-bidos-e1005-l-plpvyl1-940a-e (the cuboid is 500x500x1000 μm; the triangle of green circles are the three VCSEL diodes; this part is notable for being low cost and vaguely-decently couple-able into a cheap multimode fiber. "Should" just need a coupling lens on the end of the multimode fiber; it's (1/e²) beam divergence is given at 18° typ 25° max and reading the intensity plot in the datasheet the full width half maximum is about 8.5°), so I could try to approximately target having an on-die photodiode good for fiber data communications with a suitable low cost VCSEL diode transmitter. Notably vague ideas of brightness and less vague ideas of beam size and spectrum matter.

@BreakingTaps I'm not sure if you had planned such already; I have been reminded by gemini about the omnipresent (by default, on COMP; gate poly does self-aligned stuff to it turning it into salicide) silicide layer at the surface.... Basically: if you don't want the Si surface to be kinda excessively shiny/metallic, might be a good idea to use SAB drawings over the desired photosensitive areas of the pixels. also let me know nwell to psub/dnwell to psub would probably most relevant for visual light and p+ to nwell for UV. Technically if you're willing to put it "on ice" there's a bandgap from the shottkey junction that's excitable by 1550 nm.... but terrible quantum efficciency and shottkey typical levels of inherent "dark" current, so comfortably usable SNR only with very aggressive time gating/lock-in-amplifier tactics or byhalving the operating temperature. As I'm not planning to use a magnifying glass or such to adapt the resulting resolution/pixel size to the subject at hand, to then look at 1550 nm EDFA-amplifier-class optical fibers or their light transmission for some sort of inspection/auto-adjust processes, at least not with a custom ASIC, I'm not gonna really further that at all. Might put some structure on if convenient on a test die to measure and fill the e-test datasheets of mildly-abused things, but that'd be it....

2

@namibj - Any idea how / if you could build a simulator for this?

Tim 'mithro' Ansell

@namibj - Any idea how / if you could build a simulator for this?

"this" referring to "what"?

4:25 a.m.

the photodiode stuff (all I should have mentioned in the past day in here at least) should be readily covered by even decade old TCAD

@namibj - How the silicon responds to light given a GDS? IE Could we show the resistance change effect is expected?

(the kind of tooling that is actually used for actual semiconductor process R&D and actually designing something like a process or process-option tuned to, for example, such a schottkey based 1550nm active CMOS camera even if it has to be refrigerated for practical usage it's easily cheaper than face2face bonding of InGaAs dies of literal just plain photo diodes to Si CMOS readout electronics)

Tim 'mithro' Ansell

@namibj - How the silicon responds to light given a GDS? IE Could we show the resistance change effect is expected?

The PDK as we have been given doesn't tell us enough sadly.

4:28 a.m.

It's also not resistance it's literally current that spawns.

@namibj - I mean can we guess at the details and compare against what we see?

4:29 a.m.

@namibj - And someone in the future can build test structures to figure out more?

I assume something that works with Xyce can model a decent Si CMOS monolithic image sensor/camera, and thus model all the bits that matter for us here.

@namibj - Guess it's just a matter of someone being interested enough and having enough time to work out all the details?

Tim 'mithro' Ansell

@namibj - And someone in the future can build test structures to figure out more?

oh yeah if we have photodiode pinned out structures of all reelvant devices subjected to e-test along with sufficient modeling/measuring of how upper layer structures block light from getting down, yeah. There are affordability limits to computational optics for the upper layer structures though, especially if you involve broad-spectrum light.

https://docs.google.com/spreadsheets/d/1dK1GxGl1C7v3rhWKw3RcbeZsRre66HPAOPFbgYni74A/edit?gid=0#gid=0

Open source TCAD Market Overview - bit.ly/pg-tcad

Tim 'mithro' Ansell

@namibj - Guess it's just a matter of someone being interested enough and having enough time to work out all the details?

Well, phtodiodes aren't sooooo exotic....

namibj

Well, phtodiodes aren't sooooo exotic....

Maybe we can nerd snipe one of the GDS Factory people into doing it

maybe

4:33 a.m.

I do highly suggest to plan for getting e-test coverage for all reasonable layer configurations of photodiodes and photodiode-active structures (gate poly! thick oxide vs. thin oxide! threshold voltage options!) into Run3, though. (edited)

4:34 a.m.

I can't do the muxed e-test alone, or if I could, I shouldn't.

If you mean what the foundry does -- then we don't control the e-test structures or data.

Aside from the optical access difficulties/specialties I'd see no reason it shouldn't be suitable for the task, though.

@namibj - If there is a choice, I would prefer you working on high speed SERDES and then packaging before random optical stuff

No, muxed E-test, a concept I hoped to get into delayed Run2; didn't manage; basically imagine roughly how the tiny tapeout analog tiles work. Now re-size the cells to where the chip core area is 50% covered by VERY dense mux bus. Two wires to each DUT via/"pin" to be able to use one as drive and the other as sense and also to further calibrate out variations in the mux itself. Imagine just placing a lone SCL member there, except that it's flanked by fillcap's and then taps and then obligatory row end cells. To be measured under DC/near-DC conditions and used with heavy spice modeling to find a statistical fit of things like extraction parameters and for SCL at least some fudge factors in how nearby structures interact, to represent how it all acts in practice. Because they are way too high frequency for us to at all afford to do true dynamic tests of finer structures, so we might as well focus on doing good static/DC-op-point tests. Or at least static enough to see interesting behavior in something like a dynamic DFF.

Tim 'mithro' Ansell

@namibj - If there is a choice, I would prefer you working on high speed SERDES and then packaging before random optical stuff

Yeah; I've got the serdes 25G on SG13CMOS5L first and then in no implied order (I literally don't know ordering or amount of overlap) backport to gf180mcuD trying to get at least 10G out of that, and cross-port to sky130A trying to retain full 25G function even if it means fancier PCBs and a local retimer IC which is configured to mitigate limitations on the sky130A's analog high speed frontend performance. Packaging is more limited by access and iteration count. I'm not looking forward to doing optical stuffs for fun other than seeing towards appropriate test dies including something that vaguely looks suited to work for receiving a few hundred Mbit/s of data from a simple fiber directly into a gf180mcuD die.

1

You'll be my hero if you get anything which can do USB 5Gbit/s speed.

1

stuart started a thread. 2026-09-17 5:28 a.m.

Lauri

Update on CoB testing Yesterdays test results have been uploaded to GitHub: https://github.com/wafer-space/ws-run1-cob. Individual reports are here: https://wafer.space/ws-run1-cob. Tested:

JKU1: 20 pcs, 100% yield
GD02: 20 pcs, 95-100% yield
- first 0.5x1 CoBs
- will retest the failing CoB tomorrow
MOSB: 200 pcs, 97.5% yield
- 5 failed CoBs
- 3 missing wirebonds
Tester issue: flaky connector pin

Ran into a problem with some of the newly assembled adapter boards. Pin 1 on the connector between the adapter and the tester seems to have no connection. That contact pin feels 'softer' compared to the others. Not sure yet if this is a general connector quality problem or a compatibility issue between the tester (Hirose) and the adapter mating connectors. New testers should have mating connectors from the same company as the adapters. My current workaround for this is to insert a tiny piece of foam inside the connector, pushing the pin into contact. (edited)

@stuart this is what the foam piece looks like in the connector

1

catching up on photodiode talk: I haven't had time to work on it unfortunately (for Run3 or later), been focusing on Run1 video. But photodiodes can definitely be made on any CMOS process! They just won't be very good

missing stuff like buried diodes and STI. should still work for a demo chip though I think CCD would be tricky since we only have one Poly layer. But I think you could space them very close together and drive it with 3- or 4-phase clock. Probably really lossy and will bloom/smear but maybe part of the charm?

4:24 p.m.

good idea about SAB btw!

CCD / Bucket Brigade is something I wanted to try too

If we get functional TCAD CCD ought to be almost trivial to tune

6:32 p.m.

the many dimensions of P variations likely among the few big effects/aspects left to make it difficult

Essen started a thread. 2026-09-20 1:44 a.m.

New test results have been uploaded to GitHub: https://github.com/wafer-space/ws-run1-cob. Individual reports are here: https://wafer.space/ws-run1-cob. Tested:

TQVA: 80 pcs, 100% yield
HZ80: 100pcs, 100% yield

GitHub - wafer-space/ws-run1-cob: Results from the wafer.space Run ...

Results from the wafer.space Run #1 chip on board packaging. - wafer-space/ws-run1-cob

3

1

namibj

If we get functional TCAD CCD ought to be almost trivial to tune

I would love to see someone getting open source TCAD going for the open source process nodes;

@PhilippGuehring (who did a bunch of LibreSilicon related stuff) put together this spreadsheet back in like 2020ish when I asked him about this after releasing the PDK - https://bit.ly/pg-tcad -- Don't know if it is still correct or relevant.

I also spent a lot of time pushing - https://bit.ly/test-open-pdk which resulted in https://github.com/google/skywater-pdk-sky130-raw-data and a bunch of stuff that @Mehdi did in collaboration with NIST - https://data.nist.gov/pdr/lps/ark:/88434/mds2-2997 -- which found a bunch of issues in the skywater spice models but we never had the bandwidth to get the problems resolved.

Open source TCAD Market Overview - bit.ly/pg-tcad

Building out (automated) test generation and (automated) measuremen...

Test structure generation and measurement For improving open source PDKs bit.ly/test-open-pdk Owner: Tim ‘mithro’ Ansell <me@mith.ro> Contributors: XXX Last Updated: 2023 Q1 Goal The goal of this document is to provide a central point for the (automated) development of test structures and...

GitHub - google/skywater-pdk-sky130-raw-data: Raw data collected ab...

Raw data collected about the SKY130 process technology. - google/skywater-pdk-sky130-raw-data

Lauri

New test results have been uploaded to GitHub: https://github.com/wafer-space/ws-run1-cob. Individual reports are here: https://wafer.space/ws-run1-cob. Tested:

TQVA: 80 pcs, 100% yield
HZ80: 100pcs, 100% yield

Those are the types of numbers I expected to see when we started! Great that seems to have worked well!

Lauri

New test results have been uploaded to GitHub: https://github.com/wafer-space/ws-run1-cob. Individual reports are here: https://wafer.space/ws-run1-cob. Tested:

TQVA: 80 pcs, 100% yield
HZ80: 100pcs, 100% yield

Now I'm just slightly paranoid that we have broken the testing and it is just saying 100% success.

2

Tim 'mithro' Ansell started a thread. 2026-09-20 8:20 a.m.

Updated tester schematic and PCB. Repo: https://github.com/szfate/BondTest72 @Tim 'mithro' Ansell @Andrew Wingate @stuart r2 (2026-09-21) changes: Schematic:

Neighbour testing removed, replaced with 10 µA / 100 µA / 1 mA current sources; pullup resistors (280 kΩ / 27.4 kΩ / 2.49 kΩ) sized from the expected diode voltage drop at each current
ICL7660 (or alternative) added for the negative VEE supply
100 kΩ pulldown on Pico pad 22 (CON6, EEPROM SIO)
10 kΩ pullup on Pico pad 1 (START) per the RP2350 A2 errata
120 pF capacitor added to the ADC sensing net
Status LEDs reduced from three to two SK6812
Push button changed to EVP-BT3C4A000; r1's alternate second switch footprint removed PCB:
Board size reduced from 80 × 100 mm to 80 × 90 mm
LEDs and button moved to the right side of the board so the panel no longer covers the LEDs
Space left for button caps
Feet marks on the bottom silk enlarged from 8 mm to 10 mm

1

Lauri

Updated tester schematic and PCB. Repo: https://github.com/szfate/BondTest72 @Tim 'mithro' Ansell @Andrew Wingate @stuart r2 (2026-09-21) changes: Schematic:

Neighbour testing removed, replaced with 10 µA / 100 µA / 1 mA current sources; pullup resistors (280 kΩ / 27.4 kΩ / 2.49 kΩ) sized from the expected diode voltage drop at each current
ICL7660 (or alternative) added for the negative VEE supply
100 kΩ pulldown on Pico pad 22 (CON6, EEPROM SIO)
10 kΩ pullup on Pico pad 1 (START) per the RP2350 A2 errata
120 pF capacitor added to the ADC sensing net
Status LEDs reduced from three to two SK6812
Push button changed to EVP-BT3C4A000; r1's alternate second switch footprint removed PCB:
Board size reduced from 80 × 100 mm to 80 × 90 mm
LEDs and button moved to the right side of the board so the panel no longer covers the LEDs
Space left for button caps
Feet marks on the bottom silk enlarged from 8 mm to 10 mm

Thanks @Lauri - I'll wait to see if there's any feedback / comments before ordering

@stuart - Did we figure out what the cost delta for doing filled vias is on the CoB PCBs?

Lauri

Updated tester schematic and PCB. Repo: https://github.com/szfate/BondTest72 @Tim 'mithro' Ansell @Andrew Wingate @stuart r2 (2026-09-21) changes: Schematic:

Neighbour testing removed, replaced with 10 µA / 100 µA / 1 mA current sources; pullup resistors (280 kΩ / 27.4 kΩ / 2.49 kΩ) sized from the expected diode voltage drop at each current
ICL7660 (or alternative) added for the negative VEE supply
100 kΩ pulldown on Pico pad 22 (CON6, EEPROM SIO)
10 kΩ pullup on Pico pad 1 (START) per the RP2350 A2 errata
120 pF capacitor added to the ADC sensing net
Status LEDs reduced from three to two SK6812
Push button changed to EVP-BT3C4A000; r1's alternate second switch footprint removed PCB:
Board size reduced from 80 × 100 mm to 80 × 90 mm
LEDs and button moved to the right side of the board so the panel no longer covers the LEDs
Space left for button caps
Feet marks on the bottom silk enlarged from 8 mm to 10 mm

PCBs ordered

1

I've begun some changes for run 2 here: https://github.com/MichaelBell/chip-on-board-wire-bonded-pcbs/tree/run-2-changes/run-2

Modify 1x0p5 footprint so wire bond angle doesn't exceed 45 degrees
Rotate CoBs by 180 degrees so CoB and die orientation match
Move wafer space rocket to top left to match default position on run 2 project template
Pin 1 now indicated by a circle on either silkscreen or copper (Not actually a change for these CoBs but the principle is the logo is no longer used as a reference).

Open questions/still to do:

Should we move to 60 pin mezzanine connector for quarter size CoB?
Should soldermask be removed between pads and die? It shouldn't be required if using filled vias, but that does increase CoB cost. Thought is that glue adhesion would be better without the soldermask. Another option is to remove all the vias from this region, but I don't fancy attempting that for the half and full slots. Essen made a PR that did do this for the quarter slot where there's more space as there are fewer connections, but that PR probably went too far in also removing the ground through holes which are required for ground integrity.
If we remove the soldermask, is adhesion to the ENIG of the ground fill OK or should we remove ground fill between pads and die and go back to a ring of ground around the die?
Should we switch to 4 layer boards for improved ground integrity? Stuart is also gathering feedback which may feed into the above and/or prompt additional items.

10:15 p.m.

@Andrew Wingate I haven't ever touched the 1x1 CoB, do you want to continue to own that or shall I make similar changes to it?

Yes to removing mask between die and bond pads

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RebelMike

@Andrew Wingate I haven't ever touched the 1x1 CoB, do you want to continue to own that or shall I make similar changes to it?

Sure, go for it! Change what you like!

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@stuart mithro might be sponsoring some of this depending on how affordable it'll be at least; I'm asking if you have contacts that could plate exposed-metal-defined bumps on some of the FC01 test dies. Thickness target would be between 5 and 30 micrometers, approximately. Surface is targeting to be attached via ACF to ENIG-plated flex-PCB, 0.33 oz 2-layer (the JLCPCB special; though this is of course negotiable but in absence of any particularly decent reason to stray from it I would favor it for being both accessible and capable of probably the finest PCB traces you can get for under 50$ shipped.

namibj

@stuart mithro might be sponsoring some of this depending on how affordable it'll be at least; I'm asking if you have contacts that could plate exposed-metal-defined bumps on some of the FC01 test dies. Thickness target would be between 5 and 30 micrometers, approximately. Surface is targeting to be attached via ACF to ENIG-plated flex-PCB, 0.33 oz 2-layer (the JLCPCB special; though this is of course negotiable but in absence of any particularly decent reason to stray from it I would favor it for being both accessible and capable of probably the finest PCB traces you can get for under 50$ shipped.

Not something I have contacts for right now and I'm pretty busy until the end of the year but could look at it next year. Happy for others to investigate though

stuart

Not something I have contacts for right now and I'm pretty busy until the end of the year but could look at it next year. Happy for others to investigate though

Honestly, even more relaxed some place that could/would do ACF bonding of our dies to "printed circuit board/flex" (of any kind that's gonna end up affordable) would probably help. I'm legit expecting planar aluminum on glass to possibly be the way we'll make this work; with coarse pitch suitable for directly bonding to a cheap PCB on the outside (like a leadframe that needs the die to sit in a 300μm deep cutout) but it otherwise similar to a QFN but attached via a ring of ACF to the PCB rather than via soldering). Hmmm.......

Current state of CoB updates

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The pinouts are still the same, right?

9:48 p.m.

On the mezzanine

Yes, except for on the 1x0p5 I have switched around pads 66-69 (in0 - in3 in the default project template) so they are in the same order on the mezzanine connector as on the die. So in all cases now signals on the mezzanine are in the same order as the signal pads on the die. Hopefully that will minimize future confusion even if it does potentially cause trouble for one of the few people that used a run 1 half height slot. (edited)

RebelMike

Current state of CoB updates

I think there was some talk about trying to eliminate vias inside the pad ring or something?

Tim 'mithro' Ansell

I think there was some talk about trying to eliminate vias inside the pad ring or something?

On my radar for this week to get other feedback to @RebelMike including this point

Tim 'mithro' Ansell

I think there was some talk about trying to eliminate vias inside the pad ring or something?

You mean like : https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/pull/13

[quarter slot] Remove all vias in encapsulation region by Essenceia...

Changes: Removed though holes in 0.5x0.5 footprint and corresponding schematic Remove all visa + though holes in encapsulation region Reroute nets on layout ( see https://discord.com/channels/136...

Essen

You mean like : https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/pull/13

Oooo..... pretty! What are you doing there and how are you doing it?

Essen

You mean like : https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/pull/13

https://kicanvas.org/?repo=https%3A%2F%2Fgithub.com%2FEssenceia%2Fchip-on-board-wire-bonded-pcbs%2Ftree%2Fmezannine_footprint%2Frun-2%2F0p5x0p5-cob Merged! It is quite beautiful! Thank you!!

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Cool! I'll admit I had interpreted the lack of enthusiasm for that PR as a worry about the ground integrity, rather than you just hadn't spotted it. Going to 4 layer would probably help a fair bit, and I reckon some of the ground vias can be pushed a bit closer in too. @Essen do you want to attempt this for the others? I worry that things will get extremely busy, but I'm far from an expert at PCB layout!

My thought had been to keep the through holes (which are positioned to give short paths to the ground pins on the mezzanine connector), but see how many of the other vias could be eliminated.

RebelMike

Yes, except for on the 1x0p5 I have switched around pads 66-69 (in0 - in3 in the default project template) so they are in the same order on the mezzanine connector as on the die. So in all cases now signals on the mezzanine are in the same order as the signal pads on the die. Hopefully that will minimize future confusion even if it does potentially cause trouble for one of the few people that used a run 1 half height slot. (edited)

where's the best place to add issues / things to take into account for the board redesigns?

stuart

where's the best place to add issues / things to take into account for the board redesigns?

here? https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/issues

Issues · wafer-space/chip-on-board-wire-bonded-pcbs

Wire bonded chip on board PCB designs. Contribute to wafer-space/chip-on-board-wire-bonded-pcbs development by creating an account on GitHub.

stuart

here? https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/issues

Maybe add to https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/issues/11 - ah I see you already are

RUN-2 Change Requests · Issue #11 · wafer-space/chip-on-board-wir...

There are a number of changes we may or may not be making for the run-2 versions. Current List: All boards 4 layers Location of the pin1 fiducial Globtop bubble fixes No vias/holes/etc. under globt...

1

Looked right enough that I decided to just get on with it

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11:03 a.m.

Thanks!

@RebelMike @stuart I took photos of 4 different panels we've done recently to check the bubble situation. Pictures are showing worst samples i found. My preference list from best to worst: 1. 0p5x1 2. Green 1x0.5 1. TQVA 0.5x0.5 2. Blue 1x1

Lauri

@RebelMike @stuart I took photos of 4 different panels we've done recently to check the bubble situation. Pictures are showing worst samples i found. My preference list from best to worst: 1. 0p5x1 2. Green 1x0.5 1. TQVA 0.5x0.5 2. Blue 1x1

Interesting that it look like the 'better' ones actually have open vias under the glue, whereas afaik it's recommended to not have open vias under the glob top area. @Stephan Bökelmann any opinion or thoughts re this?

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Interesting - the through holes on TQVA have been filled, whereas on 0p5x1 they are left as holes. Those are copy/paste from ech other so I'm not sure how they ended up interpreted differently. But that does suggest that capped vias not covered by soldermask will cause problems

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@Lauri do you know if the glue type is the same for each of the above samples? Afaik the trials we have done did have different types of glue (silicone, AB epoxy, UV cured)

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Which is consistent with seeing lots of issues on the 1x1 where there are lots of uncovered capped vias

2:03 p.m.

And the green 1x0p5 is setup the "original" way that we thought caused issues - open vias on the front, tented on the back - I'm struggling to see any bubbles in that

stuart

Interesting that it look like the 'better' ones actually have open vias under the glue, whereas afaik it's recommended to not have open vias under the glob top area. @Stephan Bökelmann any opinion or thoughts re this?

@Lauri do you know if the glue type is the same for each of the above samples? Afaik the trials we have done did have different types of glue (silicone, AB epoxy, UV cured)

These are all from same supplier, and no don't know what exact type they use. I believe you have the docs about this? Also, one more important aspect is that we don't know the process. Was vacuum used or not. If yes, at what setting? Seems for the TQVA, there's bubble coming out of the capped via.

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RebelMike

And the green 1x0p5 is setup the "original" way that we thought caused issues - open vias on the front, tented on the back - I'm struggling to see any bubbles in that

We only had 20pcs of these made.

So on the basis of this my suggested approach is: No vias in the glob region, but use 6 through holes to provide a good ground connection to each mezzanine ground pin, as it looks like the through holes don't tend to cause issues. Then go back to normal (cheaper) tented vias on the outside of the pad ring for everything else.

RebelMike

So on the basis of this my suggested approach is: No vias in the glob region, but use 6 through holes to provide a good ground connection to each mezzanine ground pin, as it looks like the through holes don't tend to cause issues. Then go back to normal (cheaper) tented vias on the outside of the pad ring for everything else.

That seems like a good plan if you like that.

Not sure how easy it will be to achieve, but I can give it a go if that's the consensus. Something else has come up this weekend so I'm not sure how much time I'll have, but I'll post my progress as and when I make some! If @Essen is up for helping out too that would be great - the new 0p5x0p5 looks very neat!

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Essen started a thread. 2026-09-25 3:21 p.m.

Essen started a thread. 2026-09-25 3:30 p.m.

RebelMike

Not sure how easy it will be to achieve, but I can give it a go if that's the consensus. Something else has come up this weekend so I'm not sure how much time I'll have, but I'll post my progress as and when I make some! If @Essen is up for helping out too that would be great - the new 0p5x0p5 looks very neat!

I commit to finishing all the changes on the 0.5x0.5 board, but committing to more would be unwise of me, unless the situation is desperate: https://discord.com/channels/1361349522684510449/1552824737875501119/1553068138151551070

3:57 p.m.

[0.5x0.5 changes]

I will make a list of all requested changes for the 0.5x0.5 based on the github PR and you can ping me here if you want to request additional changes.

OK, this was not as tricky as I thought it would be - all vias eliminated from the central region on the 1x0p5, and holes moved so they connect nicely to the mezzanine ground pins. Does mean the paths for some of the power connections are a bit longer, but I don't think they are too bad. (edited)

RebelMike

OK, this was not as tricky as I thought it would be - all vias eliminated from the central region on the 1x0p5, and holes moved so they connect nicely to the mezzanine ground pins. Does mean the paths for some of the power connections are a bit longer, but I don't think they are too bad. (edited)

That looks quite beautiful!

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9:15 p.m.

I (ignorantly probably) feel only the 1x1 may be the most difficult to eliminate as there is hardly any room

Yeah, I'm not sure which of 0p5x1 and 1x1 will be harder - the 1x1 has the advantage that its pads are slightly larger so the vias naturally pack a little better, but the disadvantage that there is minimal space around the outside. But the 0p5x1 has so few pads top and bottom that the top left and bottom right of the sides have to do quite a lot of clockwise travel to get to their mezzanine pin, so it does end up quite busy.

I forgot about the twist. Thank you!

I've just requested a quotation from the manufacturer for the 60pin version of the connectors, then we can compare the costs

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Will Run 3 COB use the same HC-PBB40C-70DP-0.4V-02 / HC-PBB40C-70DS-0.4V-2.0-02 as Run 1 ?

Shumpei

Will Run 3 COB use the same HC-PBB40C-70DP-0.4V-02 / HC-PBB40C-70DS-0.4V-2.0-02 as Run 1 ?

Or compatible, yes

@Essen Hey, you did a great job I think with the attempted full die pad ring FPC fan-out; can you whip up an FPC for testing bonding the FC01 die?

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