wafer.space Community

@Andrew Wingate / @Lauri Can you remind me where the repo for the CoB tester ? Didn't find it on ws github at first glance. I assume the one I received is already ready to use ? The little wafer space logo needs to be aligned with pin 1 ( rather than the wafer.space logo on the COB ). ?

tnt

@Andrew Wingate / @Lauri Can you remind me where the repo for the CoB tester ? Didn't find it on ws github at first glance. I assume the one I received is already ready to use ? The little wafer space logo needs to be aligned with pin 1 ( rather than the wafer.space logo on the COB ). ?

https://github.com/szfate/BondTest72 and https://github.com/szfate/BondTest72-Firmware

2

tnt

@Andrew Wingate / @Lauri Can you remind me where the repo for the CoB tester ? Didn't find it on ws github at first glance. I assume the one I received is already ready to use ? The little wafer space logo needs to be aligned with pin 1 ( rather than the wafer.space logo on the COB ). ?

Yes, I it should be ready to use with the gui (in fw repo). Re: alignment - CoB corner hole to the adapter ws logo

Ok thanks. That's what I expected but the 2 chips I tested failed so I was starting to think I was missing something.

adapter eeprom specifies some chip type which may not be the one you have. Using GUI you can specify and set the correct chip type as default. After this the tester can be used without gui

Ah I see.

11:52 a.m.

Will try that.

1

I need to write up some FAQ or something for the tester. I'll add that to my todo list

Mmm ... problem might be the tester

pin 9 reports as faulty on 3 out of 3 chips I tested.

you can try to reseat the adapter board

Didn't help. I have another mezzanine from the v1 I got. I can try to swap it in.

are you using 1x1 v2?

Yes.

12:03 p.m.

Ah the other mezzanines I have are both r1 so I guess not compatible.

should be okay to use

12:09 p.m.

somehow i have no CoB's left on my desk to test with

Yeah, works with the r1 mezzanine I have.

So "Pad 9 - Adapter pin 1", it means pin 1 on the 70 pin connector right ?

Yep

Seems to be pin ch0 of the white mezzanine connector ...

And if I try to use the r1 mezzanine I have but that's marked "COB v2", then I always get pad 51 and pad 53 as faulty ... So only combo that works is the new r2 tested with the r1 mezzanine marked COB v1 ( but still selecting COB v2 in the GUI )

2:04 p.m.

So those two register as "OK". But in reality some of the power rails are shorted.

namibj started a thread. 2026-11-09 4:29 p.m.

tnt

So those two register as "OK". But in reality some of the power rails are shorted.

shorted how? Like, through the on-die PDN?

I have no idea where ... but they are shorted to GND.

6:45 p.m.

On a run 1 board I had a board with such a short and was able to clear it with a high current pulse ... didn't work this time, tried it on one of the shorted sample and now all rails are shorted and there is a bubble in the epoxy where it blew up.

oh

tnt

I have no idea where ... but they are shorted to GND.

how shorted? Because if I'm not mistaken, a revsere biased junction from VDD to VSS would act as a decently high quantum efficciency photo-conductive diode, and it sounds like you're dealing with clear encapsulation on your short-suffering COB?

Like 800 mA at 3.3V

oh yeah that's not photocurrent unless you're.... nah it's not you'd melt that itty bitty die with the losses (well, not lierally melt, but fry hard enough to break the semiconducting mode)

tnt

On a run 1 board I had a board with such a short and was able to clear it with a high current pulse ... didn't work this time, tried it on one of the shorted sample and now all rails are shorted and there is a bubble in the epoxy where it blew up.

Is this a board problem or a chip problem? Is this the tinytapeout chip for wafer space run2?