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    "topic": "Channel for discussing the implementation of USB cores on #gf180mcu\n\nInitially targeting USB full speed (12Mbit/s) but hopefully expanding to high speed (480Mbit/s) and super speed (5Gbit/s) in the future."
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      "timestamp": "2026-07-31T22:32:06.039+00:00",
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      "content": "is gf180bcd a bicmos pdk? (looks like it's proprietary, plans of open sourcing from gf?)",
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      "content": "**b**ipolar-**c**mos-**d**mos",
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      "content": "Further work has since shown that 10GBASE-R probably works on gf180mcuD; TX is basically just missing drawing up the actual clock tree, sizing the output multiplexer and output PA drivers, and figuring out the correct working phasing of the datapath from the 1.25GBit/s latches through the last MUX2 into the 2.5 GBit/s latches and then the output multiplexer itself.\n\nNothing major though. \nI just didn't get to finish/polish/tune those parts in time for the Run2 deadline. \n\nIt's currently getting ported to IHP SG13cmos5L but will be back to gf180mcuD on, by current estimates, Run4 silicon.\n\nMy Run3 contributions will be for muxed e-test and maybe a couple isolated critical blocks that'll be needed for making a great transceiver on Run4 (verifying/adjusting models/quantifying oscillator noise to correctly set PLL bandwidths/etc.).",
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