wafer.space Community

Information / fpgas-online

Channel for continued development of https://fpgas.online

Between 01/31/2026 23:59 and 03/01/2026 00:00

well.. my boxes aren't configed for v6. but I suspect I can dhcp6 or something

bunnie

I'll try to catch up on some PRs etc on the repo then, thanks for working through this!

@bunnie I am wiring up the CH347 to the NeTV2, will make a wiring diagram as part of making it work with Raspberry Pi 5, does the netv2 have an on board JTAG chip / programming port ? On the JTAG port attached to the Raspberry Pi is the RST pin equivalent of SRST on JTAG ?

07:01

Image attachment

Image attachment

Image attachment

Image attachment

Image attachment

the ⁨RES⁩ pin next to GND goes to PROGRAM_B on the FPGA

08:12

in other words, holding that low will fully reset the FPGA and cause it to reload its bitstream

08:12

it's not a jtag reset

08:12

it's a full system reset

carlfk

I hate to ask.. and it bothers me that we are having this conversation - is any of your PR needed?

The IP address changes are needed due to changes in my networking.

05:41

@bunnie - I notice the boards have that USB connector and chip, is that just a UART or could that be used to program things too? @Tisham Dhar (CSIRO EASI) Does that USB exist on the 35t boards too?

Yea the 35T has an FTDI chip and a USB connector, I was wondering if that was an on-board JTAG

05:43

I haven't tested the CH347 with 35T yet. Was just confirming the wiring

you mean the microUSB connector to the right of the HDMI connector? it's just a pair of FPGA pins brought out to a microUSB.

05:49

i think the idea is that if you wanted to add e.g. a valentyUSB core to it you could do so

Image attachment

08:08

I mean this one on the 35T

Tried flashing the NeTV2 with my CH347T, no joy, raspberry pi does pick it up as a JTAG+UART, so that's a win. Could I please get a definitive wiring diagram from the CH347 to the NeTV2 JTAG port.

00:21

The images above should have all the footprints and pinouts. My instinct on how JTAG wiring works seems off and the Captain DMA boards which using CH347 JTAG don't have open designs.

@Tisham Dhar (CSIRO EASI) - I would expect that if OpenOCD is able to do things like read the FPGA ID and then program the SPI flashing gateware to write to the spi flash you have things connected correctly.

02:13

@Tisham Dhar (CSIRO EASI) - It might also be worth trying with the Xilinx JTAG adapter first too.

The programmer is not so much an issue as wiring it up correctly.

05:54

The FPGA if fetched is not correct indicating I haven't mapped it nicely

Tim 'mithro' Ansell

The IP address changes are needed due to changes in my networking.

https://github.com/CarlFK/pici/wiki/ServerSetup that image, you made the first version. maybe that version. Any idea where the source is?

Contribute to CarlFK/pici development by creating an account on GitHub.

@carlfk - That was a Google Drawing - I believe it is in the folder @ https://drive.google.com/drive/folders/103OYiqZFsTi16W23VrjE-Wm-A9bftEVj?usp=drive_link

@Tisham Dhar (CSIRO EASI) - Did you ever see this diagram -> https://docs.google.com/drawings/d/1N9guhJIMGBHqsPUN32olwNP8XzjwhM52Qibt6FMoyq0/edit ?

NeTV2 + RPi CI System

PoE+ provides power. System power cycled via switch PoE+ API. RPi netboot, no local state. USB Ethernet

21:26

@carlfk - Doesn't look like that diagram ended up in that folder...

agreeed. it was made long before fpgas.online was regeisted

21:28

search your drive for "Independent" - and page though the 100 hits :p

21:29

really this was to give you a starting point for explaing your IP address needs

Image attachment

Tim 'mithro' Ansell

@Tisham Dhar (CSIRO EASI) - Did you ever see this diagram -> https://docs.google.com/drawings/d/1N9guhJIMGBHqsPUN32olwNP8XzjwhM52Qibt6FMoyq0/edit ?

The GPIO for programming in that diagram is not feasible. I am trying to replace it with CH347 over USB

@Tisham Dhar (CSIRO EASI) - I was really talking about all the other connections

All other connections seem to work and should be part of the build.

@carlfk -

Image attachment

\o/

22:28

did you make the font smaler or something? There seems to be more chars in the shell terminal

@Tim 'mithro' Ansell now we get to play Why doesn't it boot?

23:21

https://welland.fpgas.online/fpgas/pi25.html the Pi did a dhcp request, evidance is the server responce:

23:21

4:38:26 PM: dnsmasq: dhcp old b8:27:eb:47:9f:d1 10.31.0.125 pi25 rpi-47-9f-d1

I'm ssh to tweed. I can guess the setup, but a diagram might be nice

@carlfk - I wouldn't touch tweed at the moment, I'm trying to get the AI to summarize the changes it made

Tim 'mithro' Ansell

@carlfk - I wouldn't touch tweed at the moment, I'm trying to get the AI to summarize the changes it made

@Tim 'mithro' Ansell have it make digrams untill it matches how you connected the wires :p

19:57

I'm a little affraid you have 2 dhcp servers on the same ... subnet? lan? whatever you don't want

carlfk

I'm a little affraid you have 2 dhcp servers on the same ... subnet? lan? whatever you don't want

I think I have fixed that with vlans, but there are some complications.

I think AI broke it beyond repair

23:18

https://github.com/CarlFK/pici/blob/main/ansible/roles/pxe/templates/pibs.conf.j2

pici/ansible/roles/pxe/templates/pibs.conf.j2 at main · CarlFK/pici

Contribute to CarlFK/pici development by creating an account on GitHub.

23:18

# 4th IP octet = 100+index x.y.z.103

23:19

dhcp-range=10.31.0.128,10.31.0.254,255.255.0.0,12h

23:19

100 to 127 are ... I have no idea what happens.

@carlfk - I'm going to rework my home network so that the fpgas and IPs stay at 10.31.X.X rather than having to move to 10.41.X.X which should reduce the curn in the pici ansible

im still curious what you are trying to do

Oh, wait it looks like pici uses 10.21.X.X ?

Tim 'mithro' Ansell

Oh, wait it looks like pici uses 10.21.X.X ?

correct

carlfk

im still curious what you are trying to do

I'm trying to fit an "isolated network" of the fpgas.online hardware into my home network which is also trying isolate the supermicro BMC/coreboot hardware, the IoT network, the guest network and such. The goal is to prevent accidental exposure of my servers to devices which random people can connect too.

the PIs and everyting else on the same PoE switch?

Internet --> ten64.welland.mithis.com (gateway machine) --> Random networking hardware --> tweed --> PoE switch --> RPis

03:17

@carlfk - And unlike in the US, I only have one public static IPv4 address rather than a small number of them.

I suspect it will be easier to put tweed in place of ten64

03:22

but if you have figured out how to tunnel to tweed, good.

@carlfk - I can't do that because I need ten64 for my home network. As I said, unlike in Sunnyvale where I could give tweed a public IPv4 address I can't do that here.

03:26

I also have the problem that tweed and the fpgas are a long way away from the internet ingress point, so there is a bunch of networking equipment between the gateway and tweed.

long = too long for a run of cat5?

03:30

im not really sure what the real limit is

03:31

is outgoing byte count something to wory about?

03:32

the home page of videos are not scaled server side - I send the full res and the player is shurnk

carlfk

is outgoing byte count something to wory about?

The site has 1Gbs down / 100Mbit up

carlfk

long = too long for a run of cat5?

I think a cat6 cable might just reach but it'll be a while before I can run that cable.

@Tim 'mithro' Ansell how easy can you hook up 2 TT boards (different runs) to anything I can ssh to. tweed or a arty pi. or whatever. something I can text how to address differenrt boards

20:59

the one board I have online can us /dev/serial/by-id/usb-MicroPython_Board_in_FS_mode_de640cb1d3975a26-if00

21:00

I'm wondering how unique de640cb1d3975a26

@carlfk If you remind me on Wednesday, it should be pretty easy in theory.

1

23:27

I"m up at Monarto setting things for my parents until late tomorrow.

@Tim 'mithro' Ansell I need help - I think git sub-modules is the answer.

git submodules is an answer, it is rarely a good answer despite how much we use it

1

to boot Kianv o tt6, I need this stuff https://github.com/CarlFK/tt-commander-app/blob/feature/cli_bl910/src/ttcontrol/cli/boot_kianv_ulinux.sh

tt-commander-app/src/ttcontrol/cli/boot_kianv_ulinux.sh at feature/...

Web app to control the Tiny Tapeout Demo board. Contribute to CarlFK/tt-commander-app development by creating an account on GitHub.

23:29

part of the problem is the Arty fpga thing expanded to TT, and kinda just the 1 Kianv thing

@carlfk - My plan is that when @Matt Venn and friends finish the TT FPGA emulation board, then we will have a bunch of those in the pool.

23:45

@carlfk - I'm not game to do the vlan rename to fix the IP address stuff while I'm remote

@Tim 'mithro' Ansell im still stuck on how to get little_term.py on or close to the rp2040

little_term.py meaning litex_term.py or?

https://github.com/CarlFK/tt-commander-app/blob/feature/cli_bl910/src/ttcontrol/cli/little_term.py

tt-commander-app/src/ttcontrol/cli/little_term.py at feature/cli_bl...

Web app to control the Tiny Tapeout Demo board. Contribute to CarlFK/tt-commander-app development by creating an account on GitHub.

23:58

your ssh client -network- Pi -usb serial- RP2040 -uart serial- TT06 / 910 (KianV Linux)

23:59

little_term.py runs on RP2040 to connect Pi -usb serial- to -uart serial- TT06

00:02

mpremote fs cp little_term.py : is the final step to install it, but none of the steps are automated.

00:03

I'm trying to make it part of https://github.com/CarlFK/pici/wiki/Install

Contribute to CarlFK/pici development by creating an account on GitHub.

@carlfk - I think your text diagram is a little bit hard to understand? Is this what you mean?

<something> <-????-> ssh client <- network -> RPi <- usb serial -> RP2040 <- UART serial -> TT06 Chip (Running 910 - KianV Linux)

01:54

BTW I have been learning about conserver which seems to be a tool for sharing serial ports over the network and supports things like multiple connections, logging the output and such..... (edited)

01:56

I've recently started getting it working with the BMC serial over lan ports and also the USB-serial adapter on a RPi Zero which is connected to the consoles on my netgear network switches

Tim 'mithro' Ansell

@carlfk - I think your text diagram is a little bit hard to understand? Is this what you mean?

<something> <-????-> ssh client <- network -> RPi <- usb serial -> RP2040 <- UART serial -> TT06 Chip (Running 910 - KianV Linux)

yes - as long as you understand what little_term.py does

Tim 'mithro' Ansell

I've recently started getting it working with the BMC serial over lan ports and also the USB-serial adapter on a RPi Zero which is connected to the consoles on my netgear network switches

What is BMC serial?

BMC == Board Management Controller -- it's a little Linux computer that is found on server motherboards which allows you to remotely access things like the power buttons, virtual vga screen, virtual serial port, etc....

Tim 'mithro' Ansell

BMC == Board Management Controller -- it's a little Linux computer that is found on server motherboards which allows you to remotely access things like the power buttons, virtual vga screen, virtual serial port, etc....

ok - I undersatnd BMC - how does serial fit in?

The BMC lets you connect to the computer's serial port so you can see things like very early BIOS messages or if the linux running on the system is configured correctly even a console. Provides a way to get access to the machine when SSH isn't working or similar. I wanted computers like tweed to output dmesg messages to their serial port and log them so I could see things like kernal panics and such, hence why I was looking at conserver. But it seems like conserver could be useful for just generally providing remote access to usb serial ports in an RPi as it deals with the problem of multiple devices trying to access the serial port at once (IE you could be connected with something like cu at the same time you connect little_term and another python script)....

I'm skeptical :p - the only time I have that problem is when I forget I alreaday have something conected.

02:57

for early dmesg messages - do you know about https://www.kernel.org/doc/Documentation/networking/netconsole.txt

02:58

pass a kernel parameter append ... netconsole=@192.156.1.5/eth0,@192.168.1.3/00:08:02:a0

cf

02:59

very early it smashes that ip config and starts spewing udp

I did in the past but had forgotten about that....

I https://github.com/CarlFK/pici/blob/main/ansible/roles/fixpi/files/boot/ncc.py

pici/ansible/roles/fixpi/files/boot/ncc.py at main · CarlFK/pici

Contribute to CarlFK/pici development by creating an account on GitHub.

03:10

that beeps when it recieves, which is often when the box is crashing

Fpga boards are now in the tt shop

Matt Venn

Fpga boards are now in the tt shop

Now there are less FPGA boards in your shop

3

@carlfk - I setup a couple more of the Tiny Tapeout boards on RPis here for you

21:43

@carlfk - But I had the realisation this morning that I was doing the vlans slightly wrong

I'm not sure what to do wiht this

21:44

a diagram of what you have done would probably help

@carlfk - Don't worry about it, give me about an hour and I should have it all fixed up

@carlfk - Basically, the connection between ten64 (the gateway) and tweed's uplink port should be a different vlan to tweed's local port and the RPis so I end up with: [tfpgas.ten64] <-- tfpga vlan on switches --> [eth-uplink.tweed : eth-local.tweed] <-- fpga vlan on S3300-1 --> [RPis]

Tim 'mithro' Ansell

@carlfk - Basically, the connection between ten64 (the gateway) and tweed's uplink port should be a different vlan to tweed's local port and the RPis so I end up with: [tfpgas.ten64] <-- tfpga vlan on switches --> [eth-uplink.tweed : eth-local.tweed] <-- fpga vlan on S3300-1 --> [RPis]

S3300-1 is a switch?

carlfk

S3300-1 is a switch?

Yes.

A picture would answer these questions

22:55

is "tfpga vlan on switches" include the - ":fpga vlan on S3300-1" ?

22:57

the PoE control code can and does have "turn off all the PoE on all the ports" which might brick the thing until pull the power cord and maybe poke the reset hole

https://github.com/CarlFK/pici/blob/main/ansible/roles/site/files/pib/snmp_switch/scripts/allpoeoff.sh

pici/ansible/roles/site/files/pib/snmp_switch/scripts/allpoeoff.sh ...

Contribute to CarlFK/pici development by creating an account on GitHub.

23:37

there is /etc/environment ... pi_ports="2 3 5 7 9 11 13 21 23 " which is only the ports in ansible inventory but thats only good/valid for what is stable, not experimenting with new things, like adding a TT setup to the fpga/arty setup

also in /etc/environment is SNMP_SWITCH_AUTHKEY= which I think needs an export for source /etc/environment but adding export to that file will break EnvironmentFile=/etc/environment

23:44

https://github.com/CarlFK/pici/blob/main/ansible/roles/site/templates/daphne.service.j2#L10C1-L10C33

pici/ansible/roles/site/templates/daphne.service.j2 at main · Carl...

Contribute to CarlFK/pici development by creating an account on GitHub.

23:45

I could use some help with that.

https://github.com/CarlFK/pici/issues/51

creditional deployment / availablity needs help · Issue #51 · Car...

SNMP_SWITCH_AUTHKEY pi_pw and whatever other secrets - they are stored nicely in inventory vault but the deployment to the box is a bit of a mess. I am pretty sure there is something that doesn&#39...

I just added a Ping button to help figure out if a pi is alive

08:46

https://github.com/CarlFK/pici/blob/main/ansible/roles/site/files/pib/pistat/src/pistat/views.py#L67

pici/ansible/roles/site/files/pib/pistat/src/pistat/views.py at mai...

Contribute to CarlFK/pici development by creating an account on GitHub.

08:46

https://ps1.fpgas.online/fpgas/pi21.html

08:47

4:52:28 PM: piview: Raspberry_Pi_5_Model_B_Rev_1

08:47

it might still be over heating and turning itself off

@Tisham Dhar (CSIRO EASI) - I was able to program the NeTV2 FPGA on a RPi5 using the GPIO headers.

Same ones or different ones ?

02:23

OpeOCD linuxgpiod driver ?

@Tisham Dhar (CSIRO EASI) - Initially I was using OpenOCD with the gpiod driver (which was quite slow but still worked), but it looks like Claude has managed to create a new driver using the PIO found in the RP1 chip which is faster than the original broadcom bitbanging driver - https://github.com/mithro/rp1-jtag

GitHub - mithro/rp1-jtag: High-speed JTAG via Raspberry Pi 5 RP1 PIO

High-speed JTAG via Raspberry Pi 5 RP1 PIO. Contribute to mithro/rp1-jtag development by creating an account on GitHub.

There is no drivers openOCD, push that to git and I will have a go with the NeTV2 I have here

21:41

I will vendor it into OpenOCD tree and compile it there.

Claude hasn't finished the OpenOCD integration, but it has finished the openFPGAloader version

21:43

@Tisham Dhar (CSIRO EASI) - I could use some testing firmware to verify things beyond just reading the Xilinx ID and loading the spiflash proxy.

@Tisham Dhar (CSIRO EASI) - Did you do that write up building LiteX firmware for the NeTV2 anywhere?

I chucked it in my blog

Install LiteX following the standard setup, then: cd litex-boards/litex_boards/targets

Build for XC7A35T variant with Ethernet

./kosagi_netv2.py --variant=a7-35 --with-ethernet --build

Or for the 100T variant with PCIe

./kosagi_netv2.py --variant=a7-100 --with-pcie --build The target supports: DDR3 SDRAM: Using the K4B2G1646F module with LiteDRAM Ethernet: RMII PHY via LiteEth PCIe: x4 Gen2 via LitePCIe SD Card: Both SPI mode and native SDIO LED Chaser: For the obligatory blinky demo

I probably have the compiled bitstreams for Litex and PCI Leech floating around will find them in a few minutes after lunch.

@Tim 'mithro' Ansell if you have a 35T then the bitstream is at the bottom of this page : https://github.com/ufrisk/pcileech-fpga/blob/master/NeTV2/readme.md

pcileech-fpga/NeTV2/readme.md at master · ufrisk/pcileech-fpga

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software - ufrisk/pcileech-fpga

03:39

100T bitstream

pcileech_100t484_x1_top.zip

460.78 KB

Tisham Dhar (CSIRO EASI)

I chucked it in my blog

blog url?

Complete with code snippets : https://whatnicklife.blogspot.com/2026/01/loading-fpga-bitstreams-with-openocd.html?m=0

Loading FPGA Bitstreams with OpenOCD and Raspberry Pi - From Captai...

A Hot Adelaide Afternoon and a Pile of FPGAs I was recruited to wire together the NeTV2 to the Raspberry Pi 5 PCI bus by some means. Tim d...

@RebelMike - According to Claude you have done a bunch of work with the RP1 in the RPi5

I did some stuff trying to hack it when it first came out

22:14

There's piolib now though so you don't need to find an exploit just to use the PIOs

@RebelMike

I have a crazy idea of having the RPi5 emulate larger (IE megabyte sized) spiflash/psram with the PIO for use both with Tiny Tapeout and BMC motherboard development -- kinda of a more advanced version of your emulation on the RP2040.

It looks like originally it was quite hard to get >10 Megabyte/second transfers between the RPi5 and PIO device but it looks like ~20->40 Megabyte/seconds might be possible now.

https://github.com/mithro/rp1-jtag

https://github.com/mithro/rpi5-rp1-pio-bench

GitHub - mithro/rp1-jtag: High-speed JTAG via Raspberry Pi 5 RP1 PIO

High-speed JTAG via Raspberry Pi 5 RP1 PIO. Contribute to mithro/rp1-jtag development by creating an account on GitHub.

21:41

@Tisham Dhar (CSIRO EASI) - I should have debs and static versions of openFPGAloader with the rpi1-jtag support being built now

1

I'm not sure what kind of latency you'd manage to get given there is PCIe in the middle ...

I suspect getting deterministic performance over the PCIe bus would be tricky. I would have thought a RP2350 with PSRAM attached (maybe to GPIO instead of through XIP) would be preferable

21:48

Although at that point why not just actually attach the PSRAM to the project. I guess you could support slightly different protocols, although never at a high clock speed

21:51

One thing I think Pi 5 could be great at that I haven’t seen (though I haven’t looked recently) is a cheap logic analyser. PIO should be able to sample pins at 200MHz and you have reasonably fast access to GBs of memory

@RebelMike / @tnt - I'll see what claude is able to do here if I put some hardware in the loop and let it iterate.

22:04

I also have the crazy idea of using the RP1 PIO to do a C code LUNA type stack where you can to USB1/USB1.1/UTMI/ULPI on the GPIO pins.

22:09

I don't think the USB idea would be very useful but it might be fun to try anyway....

For USB there's https://github.com/sekigon-gonnoc/Pico-PIO-USB which only needs one PIO so might work - probably mainly depends on whether there's any latency issues.

GitHub - sekigon-gonnoc/Pico-PIO-USB: USB host/device implementatio...

USB host/device implementation using PIO of raspberry pi pico (RP2040/RP2350). - sekigon-gonnoc/Pico-PIO-USB

22:29

As far as I'm aware there's no facility for running code on the RP1's spare ARM core - but when it became clear Raspberry Pi weren't realy interested in making it possible for the community to do stuff in this area I kind of lost interest in it so I don't know about any more recent work (edited)

@RebelMike - It appears that cleverca22 has been doing your logic analyser stuff https://github.com/cleverca22/libsigrok/commit/e3783bac8176e7454863b37723ab6d8a3f99731a

initial pi5 pio support · cleverca22/libsigrok@e3783ba

Cool!

Tim 'mithro' Ansell

@RebelMike

I have a crazy idea of having the RPi5 emulate larger (IE megabyte sized) spiflash/psram with the PIO for use both with Tiny Tapeout and BMC motherboard development -- kinda of a more advanced version of your emulation on the RP2040.

It looks like originally it was quite hard to get >10 Megabyte/second transfers between the RPi5 and PIO device but it looks like ~20->40 Megabyte/seconds might be possible now.

https://github.com/mithro/rp1-jtag

https://github.com/mithro/rpi5-rp1-pio-bench

How about using an FPGA for that?

@urish - You mean like spispy?

I think so

That is what I'm planning on using at the moment

1

Tim 'mithro' Ansell

@RebelMike - It appears that cleverca22 has been doing your logic analyser stuff https://github.com/cleverca22/libsigrok/commit/e3783bac8176e7454863b37723ab6d8a3f99731a

@clever helped me with fpga.online pi net boot

17:24

which lead to https://kicanvas.org/?github=https%3A%2F%2Fgithub.com%2FCarlFK%2Fpimo%2Ftree%2Fmain%2Fproject

@carlfk - I was going to tell you to invite @clever to this channel but it turns out he is already here!

20:27

@carlfk - I think the corporate world would call this "synergy"

@Tim 'mithro' Ansell rpi-pio-jtag talking to NeTV2 35T ->

Image attachment

03:40

OpenFPGALoader is patched and built , however it is saying empty on detect

Never mind , setting pins makes it work

03:48

Making a PR

03:48

k8s@node10:~/openFPGALoader $ cd /home/k8s/openFPGALoader && sudo ./build/openFPGALoader -c rp1pio --detect 2>&1 empty rp1pio: using default pins TCK=4 TMS=17 TDI=27 TDO=22 index 0: idcode 0x362d093 manufacturer xilinx family artix a7 35t model xc7a35 irlength 6

https://github.com/mithro/rp1-jtag/pull/4

docs+feat: document openFPGALoader integration, default NeTV2 pins,...

Summary Documents the openFPGALoader integration workflow, adds the missing libfdt-dev dependency, adds default NeTV2 pin assignment, and improves CMake find_path/find_library for librp1jtag. Addre...

04:01

Lemme know if you are working on the OpenOCD implementation. I have Copilot hopping on that. I cannot test it under lspci yet since I dont have a power supply.

OpenOCD works too : https://github.com/mithro/rp1-jtag/pull/5

Feature/openocd implementation by whatnick · Pull Request #5 · mi...

OpenOCD driver implementation by GH Copilot. Tested working. sudo /home/k8s/rp1-jtag/drivers/openocd/netv2_spiflash.sh flash /home/k8s/pcileech_netv2_top.bin &gt;&gt;&gt; Flashing /home...

Exported 171 message(s)

Timezone: UTC+0