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Between 04/30/2025 23:59 and 06/01/2025 00:00
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1 I wonder how reliable the array was on GFMPW0/1. Efabless was always worried about how to produce a safe/reliable eFuse solution for Sky130. I remember fears about things either not popping, or doing so too violently (rupturing laminations or leading to shorts elsewhere)
I wonder how reliable the array was on GFMPW0/1. Efabless was always worried about how to produce a safe/reliable eFuse solution for Sky130. I remember fears about things either not popping, or doing so too violently (rupturing laminations or leading to shorts elsewhere) 
Here is a history of this Efuse compiler:
1. Originally the compiler was made in haste for the GFMPW-0 run. My chip with a 9 kBit Efuse block was accepted by Efabless, but unfortunately there was no full chip LVS available in Efabless tapeout flow at the time. So I've missed a critical flaw in this chip - VDD & GND stripes in Efuse blocks were not connected to top level power stripes. The only missing thing were vias connecting stripes on Metal5 to stripes on Metal4.
2. After discovering the power issue I thought there would be no hope to verify the Efuse block in this chip so when the chips arrived I tested mostly other parts of the chip. Efuse was dead as expected, but Caravel and some of my digital test structures worked flawlessly with VDD in range from 3 to 8 Volts which amazed me. GF180MCU seems to be a really robust process :).
3. For the GFMPW-1 I've submitted a chip with fixed power connections problem and introduced several small improvements in Efuse macro, but my chip was not selected for the run.
4. As missing top metal vias was the only thing standing between my curiosity and testing Efuse on GFMPW-0 chips, I thought that maybe it's possible to create vias on finished chips somehow. Some time ago I've got a contact of guys from chip testing industry from a friend, and they agreed to create a couple of vias for me.
5. After chip decap and vias creation on two of Efuse subblocks these subblocks miraculously just worked. I had no single write (one time obviously) or read error on all efuse bytes that were powered during several days I've tested this chip.
6. As I thought that accessible GF180 runs would never happen again I kinda lost the motivation in improving the compiler, but now if there is such a possibility I would like to make it useful.Here is a history of this Efuse compiler:
1. Originally the compiler was made in haste for the GFMPW-0 run. My chip with a 9 kBit Efuse block was accepted by Efabless, but unfortunately there was no full chip LVS available in Efabless tapeout flow at the time. So I've missed a critical flaw in this chip - VDD & GND stripes in Efuse blocks were not connected to top level power stripes. The only missing thing were vias connecting stripes on Metal5 to stripes on Metal4.
2. After discovering the power issue I thought there would be no hope to verify the Efuse block in this chip so when the chips arrived I tested mostly other parts of the chip. Efuse was dead as expected, but Caravel and some of my digital test structures worked flawlessly with VDD in range from 3 to 8 Volts which amazed me. GF180MCU seems to be a really robust process :).
3. For the GFMPW-1 I've submitted a chip with fixed power connections problem and introduced several small improvements in Efuse macro, but my chip was not selected for the run.
4. As missing top metal vias was the only thing standing between my curiosity and testing Efuse on GFMPW-0 chips, I thought that maybe it's possible to create vias on finished chips somehow. Some time ago I've got a contact of guys from chip testing industry from a friend, and they agreed to create a couple of vias for me.
5. After chip decap and vias creation on two of Efuse subblocks these subblocks miraculously just worked. I had no single write (one time obviously) or read error on all efuse bytes that were powered during several days I've tested this chip.
6. As I thought that accessible GF180 runs would never happen again I kinda lost the motivation in improving the compiler, but now if there is such a possibility I would like to make it useful. 1
Here is a history of this Efuse compiler:
1. Originally the compiler was made in haste for the GFMPW-0 run. My chip with a 9 kBit Efuse block was accepted by Efabless, but unfortunately there was no full chip LVS available in Efabless tapeout flow at the time. So I've missed a critical flaw in this chip - VDD & GND stripes in Efuse blocks were not connected to top level power stripes. The only missing thing were vias connecting stripes on Metal5 to stripes on Metal4.
2. After discovering the power issue I thought there would be no hope to verify the Efuse block in this chip so when the chips arrived I tested mostly other parts of the chip. Efuse was dead as expected, but Caravel and some of my digital test structures worked flawlessly with VDD in range from 3 to 8 Volts which amazed me. GF180MCU seems to be a really robust process :).
3. For the GFMPW-1 I've submitted a chip with fixed power connections problem and introduced several small improvements in Efuse macro, but my chip was not selected for the run.
4. As missing top metal vias was the only thing standing between my curiosity and testing Efuse on GFMPW-0 chips, I thought that maybe it's possible to create vias on finished chips somehow. Some time ago I've got a contact of guys from chip testing industry from a friend, and they agreed to create a couple of vias for me.
5. After chip decap and vias creation on two of Efuse subblocks these subblocks miraculously just worked. I had no single write (one time obviously) or read error on all efuse bytes that were powered during several days I've tested this chip.
6. As I thought that accessible GF180 runs would never happen again I kinda lost the motivation in improving the compiler, but now if there is such a possibility I would like to make it useful. thanks for following up