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    "topic": "Welcome to [wafer.space](https://wafer.space/) - \ndocumentation at [wafer.space github](https://github.com/wafer-space) - \nbuy at [buy.wafer.space](https://buy.wafer.space) - \narchives at [discord.wafer.space](https://discord.wafer.space/)"
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      "content": "Hi everyone! The logo I've ended up going with is the following",
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      "content": "I\u2019m trying to think of wacky ideas\u2026 maybe some sort of die that is actually a micro-probe array for testing other dice, flip-chip-bed-of-nails? I wonder if there\u2019s any way you could make a \u201csquishy\u201d interposer to put between such a die and the thing you want to probe",
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      "content": "@Matt Venn - It's been fun to actually get closer to the metal then I have been for a while",
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      "content": "It's the number of 3 input AND cells you can put in the same area as an SRAM ... But I'm not sure how that metric is helpful ?",
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      "content": "Oh, I see, they don't have the same naming scheme.",
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      "content": "I was looking for `dlxxx` for latches but it's named `latq`",
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      "content": "@tnt - Dammit, that was an oversight, seems like they should have been dlxxx",
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      "content": "@tnt - I was looking at how to do a compact standard cell based \"programmable\" mux",
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          "description": "I2 I3 I1 I0 Z S1 S0 Latch A Latch B Latch D Latch C MUX4 Q I2 I3 Q Q Q I1 I0 Z S1 S0 D E D E D E D E Latch A Latch B Latch D Latch C MUX4 Q Q D E D E D Q D Q Q E E Programming Data Shift Register Path Programming Data Clock Path Programming Data to Mux Path Latch A BUFZ Latch A BUFZ Latch A BUFZ ...",
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      "content": "```\ngf180mcu_fd_sc_mcu7t5v0__mux4_4 -- 21.28 um\ngf180mcu_fd_sc_mcu7t5v0__latq_1 -- 11.20 um\n```",
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      "content": "Then I discovered the `bufz_4` is also 11.20um in size",
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      "content": "Not sure what you mean exactly by \"programmable mux\" TBH.",
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      "content": "A mux where the input choice is controlled by a storage element",
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      "content": "Ok. So like a FPGA LUT cell basically.",
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      "content": "But your diagram seem to show a serial configuraiton like a shift register ... and you can only do that with actul register (i.e. FFs), you can't make a shift register with latches, that just doesn't work.",
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      "content": "Oh, yeah - I guess you are right",
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      "content": "@tnt - Actually, if you had two enables then it should work, right?",
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      "content": "No. Two consecutive latches will always have the same output.",
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      "content": "Basically two latches with non overlapping enable is one flip-flop ...",
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      "content": "@tnt - If you have Enable A and Enable B, then every \"even numbered latch\" in the chain is connected to Enable A and ever \"old numbered\" latch in the chain is connected to Enable B, then you should be able to pulse Enable A, then Enable B, right?",
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      "content": "Say you pulse Enable A ... all `A` latches now hold the value of the `B` latches before them. Whatever value they used to hold is now gone. So you only have N/2 distinct values in the chain.",
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      "content": "Ahh, yeah",
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      "content": "Having the alternative enables does prevent hold violations between the elements if they where flipflops",
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      "content": "What is it that the AI's always say when you point out that there stuff is borked? \ud83d\ude1b",
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      "content": "```\n2 * gf180mcu_fd_sc_mcu7t5v0__dffq_1 ~= 1 * gf180mcu_fd_sc_mcu7t5v0__mux4_1 + 1 * gf180mcu_fd_sc_mcu7t5v0__inv_8\n```",
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      "content": "I also have yet to understand if the routing I'm drawing is even possible on the technology",
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      "content": "Sadly the numbers don't line up as well....",
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      "content": "Stupid reality screwing up nice theory \ud83d\ude42",
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      "content": "I wonder how the drive strength effects timing and stuff",
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      "content": "I assume that a higher drive strength cell also puts more load on the cell driving it?",
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      "content": "@tnt - I do have your talk with Matt Venn on the Tiny Tapeout multiplexer stuff on my to watch list",
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      "content": "Usually large size buffer like _8 / _12 / _16 will have a progressive build up internally. Like the first stage will be a single transitor inverter, then driving a 4 transistor one then drivingthe final 16 one for instance.",
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      "content": "And  2 clock for FFs is a horrible idea. It doesn't help for hold violations, on the contrary, it's a sure way to have more issues ...",
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      "content": "@tnt - I found these diagrams from a long while back. I think it actually connected back to the N/2 distinct values on the chain issue you pointed out with the latches -- Tim Edwards explained something about how flip flops are kinda of built internally with two latches with one enable driven by an inverted clock signal so both latches are never \"open/passing data\" at the same time. Somehow I've forgotten all the correct details and am super fuzzy on what I'm trying to say here.",
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      "content": "Ahh ha",
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      "content": "Yes, if you construct the FFs \"manually\" using 2 latches, then using two non-overlapping clocks you can make things safer ... assuming you generate those two non overlapping clocks correcly.",
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      "content": "I'm missing how this relates to an mpw service, can someone explain?",
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      "content": "@Matt Venn - The discussion started at \"Figuring out what the limits are has been interesting\"",
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      "content": "@Matt Venn - All comes back to trying to make sure that I can run the MPW even if not fully full.",
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      "content": "what does \"not full\" mean?",
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      "content": "as in if only 50% of the project slots are sold",
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      "content": "other than money, what would prevent doing a run?",
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      "content": "does more mask detail cost more?",
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      "content": "I would expect blank slots could be filled in with something, like lets make a bunch of similar tests to see how well they line up with simulations",
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      "content": "If it were me, just the money. How long can I go before I'm broke",
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      "content": "And yes blank slots can be filled, but high quality projects are rare and take a lot of work",
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      "content": "k - that all fits with what I figured.",
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      "content": "sounds like we should have a bunch of filler projects so the space doesn't go to waste",
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      "content": "Totally\u2026 get cracking! https://discord.com/channels/1361349522684510449/1361349523724570941/1371324214178611271",
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      "content": "That is what https://docs.google.com/document/d/1kyo9Qcsu0RMXwUS2woMCOvf14YvA0IqpgDkZmIRFZpc/edit?tab=t.0 is all about",
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          "description": "wafer.space GF180MCU Projects      Single Usage Tiles    Programmable Tiles    One Time Programmable",
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      "content": "how about:  power rail popper.  a set of decreasing width traces? to see how much power they can really handle compared to what the simulator says",
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      "content": "I always wanted to try a project like that\u2026 a way to test all the things that could go wrong. DRC violations (so long as they don\u2019t violate MR), wrong voltages going to a bunch of devices, chips that could self-destruct (charge pumps?), ESD-unprotected stuff\u2026 what else?",
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      "content": "@algofoogle (Anton Maurovic) - https://github.com/egorxe/gf180_efuse_compiler",
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      "content": "Oh that\u2019s interesting. Thanks Tim \ud83d\ude42 I wonder how reliable the array was on GFMPW0/1. Efabless was always worried about how to produce a safe/reliable eFuse solution for Sky130. I remember fears about things either not popping, or doing so too violently (rupturing laminations or leading to shorts elsewhere)",
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      "content": "I'm sending an email to enquire about the status",
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      "content": "I don't think it ended up being taped out because the efuses require an extra mask layer or something",
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      "content": "Looking good guys, keep up the fantastic work!",
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      "content": "From the developer of the Efuse Compiler:\n```\nHere is a history of this Efuse compiler:\n1. Originally the compiler was made in haste for the GFMPW-0 run. My chip with a 9 kBit Efuse block was accepted by Efabless, but unfortunately there was no full chip LVS available in Efabless tapeout flow at the time. So I've missed a critical flaw in this chip - VDD & GND stripes in Efuse blocks were not connected to top level power stripes. The only missing thing were vias connecting stripes on Metal5 to stripes on Metal4.\n2. After discovering the power issue I thought there would be no hope to verify the Efuse block in this chip so when the chips arrived I tested mostly other parts of the chip. Efuse was dead as expected, but Caravel and some of my digital test structures worked flawlessly with VDD in range from 3 to 8 Volts which amazed me. GF180MCU seems to be a really robust process :).\n3. For the GFMPW-1 I've submitted a chip with fixed power connections problem and introduced several small improvements in Efuse macro, but my chip was not selected for the run.\n4. As missing top metal vias was the only thing standing between my curiosity and testing Efuse on GFMPW-0 chips, I thought that maybe it's possible to create vias on finished chips somehow. Some time ago I've got a contact of guys from chip testing industry from a friend, and they agreed to create a couple of vias for me.\n5. After chip decap and vias creation on two of Efuse subblocks these subblocks miraculously just worked. I had no single write (one time obviously) or read error on all efuse bytes that were powered during several days I've tested this chip.\n6. As I thought that accessible GF180 runs would never happen again I kinda lost the motivation in improving the compiler, but now if there is such a possibility I would like to make it useful.\n```",
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      "content": "@digshadow",
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      "content": "@digshadow - Should I ask the guy to send us some spare parts for you to look at / play with? \n\n(BTW Feel to respond to this next week after your conference.)",
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      "content": "Yes, I don't really want to think about this right now, but in general I'm up for a lab day next week if you want to image some things",
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      "content": "Very cool \ud83d\ude42 thanks for following up",
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      "content": "I started documenting my understanding around the GF's 180nm process technologies @ https://bit.ly/ws-gf180",
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          "description": "GlobalFoundries 180nm Technologies bit.ly/ws-gf180  GlobalFoundries offers a wide range of different 180nm based technologies. These 180nm technologies are very configurable and offer; Multiple options in the number of metal layers. Different thickness for the top metal layer. A large number of \"...",
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