============================================================== Guild: wafer.space Community Channel: Information / general Topic: Welcome to [wafer.space](https://wafer.space/) - documentation at [wafer.space github](https://github.com/wafer-space) - buy at [buy.wafer.space](https://buy.wafer.space) - archives at [discord.wafer.space](https://discord.wafer.space/) After: 09/30/2025 23:59 Before: 11/01/2025 00:00 ============================================================== [10/01/2025 18:58] mithro_ @Leo Moser (mole99) - I think I made you a mod which should allow you to create channels. {Reactions} 👍 [10/02/2025 14:23] mithro_ This live stream starts in a few hours! [10/02/2025 14:32] 246tnt Oh ... in the message it said 3rd october so I noted it for tomorrow 😅 [10/02/2025 14:32] 246tnt (I know it also said Thursday so I should have noted the discrepency but I didn't) [10/02/2025 14:45] mole99 Yeah, there was a mix-up 😅 [10/02/2025 14:51] mithro_ Yes, it appears I can not work a calendar 😛 [10/02/2025 16:41] mole99 {Reactions} 🎉 [10/02/2025 16:41] mole99 Check out the update to the template! [10/02/2025 17:44] mattvenn Glad it's not just me! [10/02/2025 17:59] mithro_ I even double checked the date. [10/02/2025 18:59] mithro_ Just about to go live now @ https://www.youtube.com/watch?v=tEOmnN8IAjs {Embed} Crowd Supply https://www.youtube.com/watch?v=tEOmnN8IAjs Teardown Session 56: wafer.space with Tim Ansell & Leo Moser Join Crowd Supply's Helen Leigh for a conversation with Tim Ansell about wafer.space, a new way for chip designers to easily turn a design into real, working chips. *About Our Guests* Tim “mithro” Ansell builds the bridges that make open silicon real. At Google, he helped release the SkyWater SKY130 open-source PDK and launched the Open MPW... 2025-10_media/maxresdefault_live-743AB.jpg {Reactions} 👌 [10/02/2025 20:38] urish Started a thread. [10/02/2025 21:55] mithro_ Please reshare https://www.linkedin.com/feed/update/urn:li:activity:7379634646847979520/ {Embed} https://www.linkedin.com/feed/update/urn:li:activity:7379634646847979520/ #gf180mcu | wafer.space Tim Ansell is happy to announce that the first GF180MCU open silicon run from wafer.space is now available for purchase through Crowd Supply at https://buy.wafer.space! For $7,000 USD you get 1,000 bare die of ~20mm² GF180MCU open source silicon. There is also an option of purchasing chip-on-board wire bonded and full undiced wafers. The fina... 2025-10_media/1759442005157-F61B1 {Reactions} 👍 [10/02/2025 22:12] mithro_ Appreciate upvotes on hackernews - https://news.ycombinator.com/item?id=45456229 {Embed} mithro https://news.ycombinator.com/item?id=45456229 Wafer.space – $7k USD for 1k custom chips Hacker News {Reactions} 👍 [10/02/2025 22:28] mithro_ Started a thread. [10/02/2025 22:30] mithro_ I'd appreciate upvotes if you are part of the reddit communities in the thread https://discord.com/channels/1361349522684510449/1361349523724570941/1423436537994940456 {Reactions} 👍 [10/03/2025 04:52] hardwall Great live session yesterday. I was looking at what fits in the size / node you have , and I saw this paper. https://sbmicro.org.br/sforum-eventos/sforum2021/Design%20of%20Steel%20ASIC,%20a%20RISC-V%20processor.pdf They say they used 15mm2 for the STEEL core at 180nm. Not a silicon guy, the nosey embedded SW eng from the live stream here. So excuse my naivete. Anyways that looks quite large ish? Is it true that you need that much die area for a simple RISC-V core? Using Claude to get ballpark estimates, I was wondering if I can fit an IBEX in the area you have and the IBEX is larger than the STEEL. Can I eyeball what fits with some gates/mm2 formula? [10/03/2025 04:57] urish IIRC tim mentioned about 1.2m gates in the wafer space area {Reactions} 👍 [10/03/2025 08:18] rebelmike You can see from the image in that paper that the logic is only using a small fraction of the area. IBEX would fit easily. For a chip focused on reasonable performance, most of the area would likely be taken up with SRAM for memory and cache. {Reactions} 👆 [10/03/2025 08:32] 246tnt It'll be interesting to see how the campaign progresses. I would actually expect it to stay very low until the very end: * There is no mentions of any limited space / number of slots on the campaign page * There is no incentives for early birds * Unlike other crowdsupply campaign, the user is actually expected to do something, so I would expect most of them to hold off paying until they actually got something to submit, especially given the two items above, there is no benefit to buying early, only risks if you can't finish what you want to do in time. {Reactions} 👍 (2) [10/03/2025 08:56] mole99 All good points @Tim 'mithro' Ansell {Reactions} 🎉 👍 [10/03/2025 10:26] hardwall I noticed that as well, but I wasn't sure what die size that was. [10/03/2025 10:49] rebelmike I think what I would do, if I was trying to create a custom Risc-V for wafer space would be: - 8kB internal RAM - QSPI flash chip and QSPI PSRAM chip on separate interfaces - 4kB cache for each of the PSRAM and flash - Hazard3 Risc-V core in a similar config to RP2350, but single core That should leave a decent amount of space (maybe 1/3 of the area) for peripherals and custom logic, but enough cache and RAM to give OK performance. I'd target 3v3 so that it was easy to interface with standard QSPI chips, and hope to get it running at 30MHz. [10/03/2025 12:55] hardwall You can't have flash on chip, can you? [10/03/2025 13:01] 246tnt No [10/03/2025 15:29] mithro_ There was one attempt at flash on gf180mcu mpw-0 but it was never tested. [10/03/2025 15:48] 246tnt @Tim 'mithro' Ansell How ? There are no such device in the PDK ? I saw some floating gate experiment on sky130 that doesn't use sonos, but that was pretty big AFAIR. [10/03/2025 15:53] 246tnt (That's the paper for what I'm talking about in sky130 https://woset-workshop.github.io/PDFs/2021/a11.pdf ) [10/03/2025 16:13] mithro_ https://docs.google.com/document/d/1I3UOSdVONUD_IXYKU4gYSDF-LOz3-B1a-wXXivrkCnw/edit?tab=t.0#heading=h.ol6cxbt7gxt {Embed} https://docs.google.com/document/d/1I3UOSdVONUD_IXYKU4gYSDF-LOz3-B1a-wXXivrkCnw/edit?tab=t.0 GF180MCU Single-Poly "Flash-Like" Memory (UMich / OpenFASoC / Mehdi) GF180MCU Single-Poly "Flash-Like" Memory (created by UMich / OpenFASoC / Mehdi) Original source document created by Tapeout Information This design was taped out on GF180MCU as part of the Google GFMPW-0 run. The IC was designed to be wire bonded / probed directly, however GFMPW-0 only retur... 2025-10_media/AHkbwyIztVLvj9VgoCeNMk8D_vTjqAyT3BfGKixzgL-C45F1 {Reactions} 👍 (2) [10/03/2025 16:30] mithro_ No idea if that is viable or not and as I said it was never tested due to them needing bare die and only getting packaged (and then getting busy with other stuff). [10/03/2025 16:37] 246tnt Seems to be a similar approach to what was on sky130, just leave some poly floating connected to several transistors and some of them are used for reading and other for tunneling charge in/out of the gate. But of course the devil is in the detail so that cell could work or not ... [10/03/2025 16:44] hardwall Hah, could work or not.. precisely what you don't want to hear about your memory. Not a big problem I think, but I was just curious about the constraint. It would probably use quite a bit of the die anyway,. [10/03/2025 16:46] hardwall I'm wondering why you recommend the hazard3 instead of the Ibex. I was under the impression ibex is better tested. [10/03/2025 16:47] hardwall Hazard3 is actually in commercial products though, so I guess that's worth for something. [10/03/2025 16:48] 246tnt yes, flash is huge and probably a good waste of real estate ... the cells are not small and then you need a ton of periphery circuitry to drive it ( to generate all the high bias voltages and switch them around for instance ). [10/03/2025 16:53] rebelmike Ibex looks like it would be a good choice too, but personally I think it would be cool to use the same core that’s in the RP2350. Mainly I was trying to give an example of the kind of system that would make sense. [10/03/2025 16:54] mithro_ Why not both! 😛 [10/03/2025 16:55] mithro_ {Attachments} 2025-10_media/why-not-both-why-not-53866.gif [10/03/2025 21:50] rtimothyedwards_19428 @tnt : Workable nonvolatile memory would still be very useful for setting some number of configuration bits that can be read at startup. It doesn't have to be a kilobyte memory block to be useful. [10/03/2025 21:54] rtimothyedwards_19428 Efabless got the Hazard-3 core to tapeout on Sky130 on the "Frigate" chip, but unfortunately it never got through manufacture. I would like to revive the Frigate architecture; didn't have time to do it for the Cadence tapeout, and don't have the analog IP for the GF180MCU tapeout. I'm considering a Chipalooza-like contest to get analog IP for GF180MCU, with the general goal of having something like Frigate on the process. {Reactions} 💯 [10/03/2025 22:03] mithro_ @Tim Edwards - Have you seen the OpenFASoC design done on MPW18H1? https://siliconpr0n.org/archive/doku.php?id=mcmaster:efabless:gf180mcu-mpw18h1-18100004 {Attachments} 2025-10_media/Rapid-Prototyping-of-Laser-Induced-Graphen-D6CBA.pdf [10/03/2025 22:09] mithro_ I did also send Luke Wren an email about Hazard-3 core on GF180MCU and he was talking about the launch @ https://types.pl/@wren6991/115267726230458487 {Embed} Luke Wren (@wren6991@types.pl) https://types.pl/@wren6991/115267726230458487 $7000 for a 20 mm^2 GF180 MPW tapeout, you get 1000 unpackaged chips 🤔 maybe I should try that PDK [crowdsupply.com/wafer-space/gf…](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1) Upside\: you get to do your own padring\! Downside\: you have to do your own padring\! \(and ESD\) types.pl [10/03/2025 22:10] mithro_ Also did you see the efuse stuff - http://bit.ly/ws-gf180mcu-efuses ? They could be used for configuration bits too. {Embed} http://bit.ly/ws-gf180mcu-efuses wafer.space - GF180MCU eFuse Information - bit.ly/ws-gf180mcu-efuses wafer.space - GF180MCU eFuse Information https://bit.ly/ws-gf180mcu-efuses Current Status Egorxe has created an efure compiler @ https://github.com/egorxe/gf180_efuse_compiler These efuses were taped out on the Google GFMPW-0 free shuttle in slot-030 / Position E6. An issue with missing via's m... 2025-10_media/AHkbwyLzAIwf8jqbBEsoOjAQ0HNC3ZjtCLaqLAS73P-F2160 [10/03/2025 22:20] rtimothyedwards_19428 @Tim 'mithro' Ansell This set of process options includes efuses? I have done eFuse arrays in the past (when I was working at MutiGiG). [10/03/2025 22:21] mithro_ @Tim Edwards - ***If*** I understand correctly, we do **not** have the foundry provided efuses stuff which uses an extra mask layer. This done was done without needing that in some way? [10/03/2025 22:29] rtimothyedwards_19428 Making a working eFuse device is not trivial. Without a passivation window over the device, you will just melt the material in place and it will re-solidify in place. [Warning: misinformation. Corrected in the discussion with Egor Lukyanchenko, below. Passivation windows are for laser-trimmed fuses.] [10/03/2025 22:32] mithro_ @Tim Edwards - There are claims it works but it is nontrivial to test due to missing metal connections in the test chip. I recently sent Andrew Zonenberg a couple of the parts that @Egor Lukyanchenko sent me to look at. [10/03/2025 22:38] mithro_ Also, I'm very interested in sourcing known-good-die for SPI flash parts that we can then wire bond to the custom silicon. [10/03/2025 22:44] rebelmike Feels like it would fairly simple just to assemble a flash chip onto the CoB PCB? [10/03/2025 23:19] mithro_ True, I guess. Was just hoping to reduce the cost by avoiding packaging. [10/03/2025 23:33] mithro_ BTW I'll be travelling most of next week from Sunday (going Chicago->Singapore->Adelaide). {Reactions} 😯 [10/04/2025 04:03] mithro_ I'm currently tracking a few other metrics like number of subscribers and such. It will be interesting to see what happens when we have a submission platform up and running. If if people submit designs to be verified without having purchased a slot or not. {Reactions} 👌 [10/04/2025 04:05] mithro_ Seems reasonable to me. Why not give it a go? 🙂 [10/04/2025 05:13] hardwall I think he was advising me how a reasonable risc-v would look like. I've been probing around the idea. [10/04/2025 07:12] egorxe Hi, @Tim Edwards and everyone else here! Why do you think a passivation window is required above the fuse? Fuse material is not melted per se but is “moved” by electromigration after all. I'm not by any means an expert in technology myself, but the only requirement that is present in open source DRM is that there should be no metal1 and metal2 above the fuse. I understand that the opensource DRM and DRC rules could be incomplete in rarely used aspects like eFuse, but during OpenMPW-GF0 my chip with the eFuse block adhering to these rules was accepted and manufactured, so I guess it passed an official factory DRC with Calibre or something. Unfortunately that chip had a fatal flaw with the power supply for eFuse which I missed due to device level LVS being absent from the tapeout script for GF180 at that time, and the fixed chip was not accepted for the GF1 run. The only way to test the eFuse on the GF0 chip was by decapping it and restoring eFuse power one way or another. I’ve sent @Tim 'mithro' Ansell some of my GF0 chips and described this powering and testing procedure in detail [here](https://docs.google.com/document/d/1O9qWxHJzb4RIqjDzd3Dr9FddIsH_DiyjSaHewqEm0X4/edit?tab=t.0#heading=h.oi68oexfhjcr). {Embed} https://docs.google.com/document/d/1O9qWxHJzb4RIqjDzd3Dr9FddIsH_DiyjSaHewqEm0X4/edit?tab=t.0 GFMPW-0 E6 chip eFuse patching GFMPW-0 E6 chip eFuse patching General chip description Similar to all OpenMPW chips, E6 consists of a Caravel test harness (MCU + padring) and a user area. The user area contains two parts: simple FPGA fabric organised as 14 logic blocks with 8 LUT4 in each of them (left part on fig.1) and eFus... 2025-10_media/AHkbwyINja4c71CC6jw4-QlbASD9Rpr4h8dhKZMxw0-9C6EA [10/04/2025 07:12] egorxe As far as I know one of the chips was decapped but the eFuse powering was not attempted, probably Tim knows more about it. But I’ve personally tested a single chip patched this way earlier. If I remember correctly, there were 128 bits of eFuse powered, around half of which I’ve blown writing something semi-random. I had only about a day to test the chip remotely, but during this whole time period (apart from several power downs to ensure nonvolatility) eFuse was constantly being read from Caravel in cycles and all the bits kept their state. 128 bits and one day is a tiny sample for sure, but due to constant reading each bit was sensed around a billion times which is quite a lot for a eFuse and there were 0 read errors. I understand that unless someone repeats this patching procedure, there is only my word about this short testing to trust here, but personally I am sure that it works to some extent. Fuses definitely do not solidify back in place, at least most of them do not as none of my ~64 programmed ones did. A couple of days ago I was contacted by Jonas Svennebring who is planning to lead the effort of creating a chip for testing several IPs to be launched on the first wafer.space run. We agreed to work on putting several eFuse memory blocks created with my updated eFuse compiler to characterize eFuse performance and reliability. So hopefully we’ll have more reliable information about eFuse after the first wafer.space chips arrive. If anyone has some knowledge which could help to make eFuse more reliable or could help in any other way I would be very grateful. [10/04/2025 07:31] egorxe Regarding the eFuse mask, some fuse masks are listed as optional [here](https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_04_3.html). But probably these are some other fuses, cause layer numbers do not match eFuse ones and it mentions "Top plate of MIM capacitors". As my chip was manufactured during GF0 I assumed that the mask (masks?) necessary for eFuse was present during the run, not sure if it was ordered separately or was included by default. @Tim 'mithro' Ansell do you have a way to check with GF if eFuse masks will be available during planned wafer.space run? Cause if not, there is no reason for me and Jonas to work on putting eFuse on the test chip. [10/04/2025 08:53] egorxe As for using eFuse as a MCU ROM or something similar, I think it could be done. Although an eFuse cell has a limited number of read cycles (~10^7-10^9 depending on technology and a testing methodology based on open info) which makes it unsuitable for such tasks directly, it's quite easy to create an eFuse-SRAM hybrid. By copying whole eFuse contents to SRAM after powerup and reading only from SRAM afterwards it's possible to mitigate this limitation for read-heavy uses. Drawbacks are obvious: higher power, startup delay and ~1.5x lower density than a raw eFuse. But I estimate that it's still possible to achieve a density of ~6 kbits/mm^2 which makes small MCU ROMs feasible. Especially because if I'm not mistaken it's currently the only option for post-fabrication programmable ROM. [10/04/2025 13:56] rebelmike I would be up for helping create some kind of template that had a rough shape like this - with the aim of giving people a decent Risc-V SoC to add custom logic to. Though not for this shuttle as I don't have much free time before the deadline and I'm already aiming to get a version of TinyQV using the SRAM block on to the Tiny Tapeout submission, and also a different Risc-V SoC on the next sky130 TT shuttle. [10/04/2025 14:00] rebelmike I think if I were to do something towards this in the timeframe of this shuttle it would be to create a cache + QSPI controller and get it into a TT slot. I think there's an efabless project that @Leo Moser (mole99) used in Greyhound that would make a reasonable starting point. [10/04/2025 14:07] rebelmike Also these projects are a hobby for me, so the price is way out of range, and I also wouldn't want 1000 chips! So would need to either find 20+ people to split the cost and chips with Tiny Tapeout style, or for this to be sponsored on the basis that creating and proving a template like this would be useful. [10/04/2025 14:25] tholin I think its totally feasible for me to develop an Arduino-like single-board solution for my AS2650-2 MCU, including being able to update its flash over USB. [10/04/2025 14:26] tholin I'll be looking into that this weekend because I have so many of those chips and nothing to use them for as-is. [10/04/2025 15:46] tholin I believe its also totally possible to do so with my RISC-V core, but I don't have too many of those chips, so I'll wait until I get a wire bonder so I can use the raw dies for this instead, of which I have plenty. [10/04/2025 18:29] rtimothyedwards_19428 @Egor Lukyanchenko : I apologize, you are correct. I have worked with laser trim fuses and efuses (in the long past---around 2007 or so), and I was conflating the two. Laser trim fuses require a passivation window over the device, because the laser evaporates the material, which must have somewhere to go or it just melts and resolidifies, as I said. But yes, eFuses involve the electromigration of the salicide off the top of the poly and are a different mechanism entirely. The GF manual, as usual, is very difficult to read and does not help things at all by variously referring to the "eFuse", the "polyfuse", metal fuses, and OTP. I still have not figured out what they mean by OTP. However, by looking at the device/layer truth table, it looks to me like "polyfuse" and metal fuses both require a window and therefore one extra mask, whereas I don't see that the eFuse requires any additional mask, and is simply defined by a number of marker layers. {Reactions} 👍 [10/04/2025 18:32] urish OTP = One time programable [10/04/2025 18:32] rtimothyedwards_19428 The N+ poly fuse is apparently a laser trimmed fuse, I guess? Also the GF manual further confuses things by referring to the MiM cap layer as "fuse top", which is a mystery to me (maybe a layer number reassignment that nobody cleanly fixed in the documentation?). Anyway, the proof is that you have a working circuit, and as far as I know this was done on the Google/Efabless GF180MCU run without any additional masks. [10/04/2025 18:33] rtimothyedwards_19428 @urish : I know that OTP means "one-time programmable". What I don't know is what OTP _device_ is being indicated by the OTP marker. It doesn't seem to relate to anything else in the documentation. {Reactions} 👍 [10/04/2025 18:34] rtimothyedwards_19428 It does not seem to refer to either the eFuse or polyfuse devices, either of which could be referred to as OTP. Reading it over again, I think it _might_ be referring to the metal (laser trim) fuse. [10/04/2025 18:59] mithro_ @Tim Edwards / @Egor Lukyanchenko - I can take a look at the mask ordering form and see if I can figure out more info it that is useful. {Reactions} 👍 [10/04/2025 23:48] mithro_ Anyone able to figure out how to get the PDF linked from https://ieeexplore.ieee.org/document/11185233 ? (Which seems to be connected to a GitHub repo @ https://github.com/SJTU-YONGFU-RESEARCH-GRP/PDB-Physical-Design-Database/tree/main/layout/gf180 ). {Embed} https://github.com/SJTU-YONGFU-RESEARCH-GRP/PDB-Physical-Design-Database/tree/main/layout/gf180 PDB-Physical-Design-Database/layout/gf180 at main · SJTU-YONGFU-RE... This repository presents the Physical Layout Database (PDB), a comprehensive collection of physical layouts encompassing diverse benchmark circuits and various layout dimensions. The layouts are me... 2025-10_media/PDB-Physical-Design-Database-C1203 [10/05/2025 02:03] egorxe Yeah, there are a lot of confusing terms in DRM, at least regarding OTP cells. To make things even more interesting there are some mentions of [MTP](https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_10_13.html) and [NeoEE](https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_10_15.html) cells. NeoEE seems to be a specific proprietary type of EEPROM, but MTP could refer to a number of things and I'm not sure if it's possible to devise a working MTP cell just from these geometry limitations in DRM. [10/05/2025 02:17] egorxe It's downloadable from [here](https://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=10677474) probably cause it's early access. [10/05/2025 05:33] mithro_ I still don't seem to be able to download a PDF from there? That second page just seems to take me back to the first page? [10/05/2025 05:37] egorxe For me it worked from that page. Here is the pdf. {Attachments} 2025-10_media/Descriptor_Physical_Design_Database_PDB-11771.pdf [10/05/2025 05:38] mithro_ Maybe IEEE is just blocking me for some reason or something... [10/05/2025 05:42] egorxe It's an open access article, so should be available to everyone. May be [direct PDF link](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11185233) will work for you? [10/05/2025 05:43] mithro_ That one works! {Reactions} 👍 [10/05/2025 20:56] dshadoff Mithro, you had said somewhere that buying a 1,000 chip run could be broken down to 100 for first pass, 100 for validation, and then something like 500 for actual products (or something like that). On the CrowdSupply livestream, you mentioned how it could scale up (and cost down), but how would it work for test/validaiton iterations (without forcing $7K per attempt) ? [10/05/2025 21:01] 246tnt I think he meant for the full product, not for the chip alone. Like you make 1000 asic. Then you build 100 of your product using that chip for the first pass. But you can't revise the chip, only what you put around it. [10/05/2025 21:07] dshadoff Well, fully-digital designs can be validate in FPGA, but mixed-signal would be much more complicated [10/05/2025 21:07] dshadoff So I think it's reasonable to assume that initial design would need modifications. [10/05/2025 21:11] 246tnt Yes, I would expect so. But NRE on making 1k chips are still the bulk of the price vs the per wafers cost, so you won't get any real price cut by making only 100. [10/05/2025 21:12] dshadoff Don't get me wrong - I'm not complaining about $7K being a lot of money for a working design. It's just a lot of money if the design doesn't work. [10/05/2025 21:12] 246tnt Testing sub-modules on real silicon at lower cost is a good use of Tiny Tapeout if you can make your IP fit its constraints. [10/05/2025 21:13] 246tnt That at least could allow to check it's not DOA and shows signs of life, even if you can't necessarely do full caracterization. [10/05/2025 21:14] dshadoff I could pull $7K out of my own pocket, but 3 iterations ... not so much. So I'd be looking for a small team of like-minded people. [10/05/2025 21:14] dshadoff Anyway, I'm only asking because the comment itself piqued my interest. If it was misunderstood, then mea culpa. [10/06/2025 00:15] algofoogle There will always be people (including me) who are on the lookout for sharing the cost and who only need a smaller number of parts. I (and many others here) have helped assemble single chips that contain multiple designs that share the majority of available pins. TT is the extreme of this and a great way to do it at super low cost/risk, but if you need more like 10%-25% of the total area and more like 30+ signal pins, then (say) $2000 has the potential to get you much greater value on this sort of platform than it does on TT… it’s just a higher barrier to entry in terms of integrating, and higher risk that your design could break the chip for everyone else [10/06/2025 00:34] dshadoff Thanks, this is helpful [10/06/2025 00:37] algofoogle @Tim 'mithro' Ansell maybe a dedicated “space sharing” channel would be in demand, unless that erodes your revenue potential. Anyone embarking on this should be prepared to accept the risk, btw, and be aware that someone will spend long hours just trying to make sure everyone’s projects cooperate… lots of cat-herding unless you know the others involved well [10/06/2025 00:39] algofoogle I was lucky to have great parties to the GFMPW-1 chip I integrated and had fabbed, but I’ve seen others who clashed/struggled and some on other chips who didn’t pull their weight… or simply weren’t available at the right times to answer questions about their design, etc. [10/06/2025 03:07] mithro_ That is why I'm excited about the work with Tiny Tapeouts, gives you an even cheaper way to test out ideas and verify things before you make the larger commitment. [10/06/2025 03:09] mithro_ As Anton also mentioned, getting you back a large number of parts allows you to share a slot with other people and still get back a useful number of parts. [10/06/2025 03:13] mithro_ You can also probably mitigate a bunch of risks by having multiple pad frames on one chip. [10/06/2025 03:15] mithro_ I'm also at the airport, so probably won't be responding for the next day or so. {Reactions} 👍 (3) [10/06/2025 08:25] algofoogle For people needing bonding (i.e. most customers??) it seems going with the “standard” pad placement (that is, the one that would be used by TT) might be the affordable way to go, if it means the engineering is already done and the chip-on-board provider is set up for it within the $8500 price. Otherwise, having each design’s own padrings (for shared submissions) is probably a good idea. One idea to reduce the bonding cost in that case MIGHT be to have a quarter-size padring which is symmetrical in such a way that it is placed within each quadrant and the whole die can be rotated 0, 90, 180, and 270 degrees and the pads will end up in exactly the same place. [10/06/2025 08:42] mole99 (pinned) By the end of this week, I would like to send a test reticle to GF in order to receive feedback on the sealring, the filler generation and the reticle itself. If anyone has a project ready with the [gf180mcu-project-template](https://github.com/wafer-space/gf180mcu-project-template), I can include it in this "virtual tapeout". This way, you can also get early feedback on whether your design is manufacturable or if the open source DRC deck missed an issue. @Tholin, if I remember correctly, you were planning to have something ready? I'll improve the filler generation this week, but you can already use the template and update it on Friday to get the latest changes. [10/06/2025 09:06] mithro_ Pinned a message. [10/06/2025 12:43] tholin Ah, I was busy fixing DRC errors in my SCL [10/06/2025 12:43] tholin Which should be done now, actually. [10/06/2025 12:43] tholin I even had errors inside the cells themselves, which only showed in KLayout. [10/06/2025 12:44] tholin Most if not all of the DRC errors should now be gone. [10/06/2025 15:16] tholin I’m not sure if I have enough time now. I’ve been focusing on other things. I’ll try. [10/06/2025 15:28] tholin I’m also kinda waiting for the template to become usable in iic-osic-tools, which it currently isn’t. I work on my designs on both my PC and my Laptop and need a portable setup for all the tools without a fuss, and iic-osci-tools gives me that. [10/06/2025 18:23] mole99 No worries, if you have something ready by then, just let me know. [10/06/2025 18:23] mole99 It will still be a while until all of the changes have been upstreamed to both LibreLane and the PDK, and then you'll need to wait for a new release of the IIC-OSIC-TOOLS. I would highly recommend using Nix, as it gives you a much better control over your tools. I also started out with OpenLane 1 using Docker, however, once I switched to Nix for OpenLane 2 and now LibreLane, I never looked back. It's much easier to change the version of individual tools, you can create an environment that is reproducible, and you get the best performance :) Please consider giving it a try: https://librelane.readthedocs.io/en/latest/getting_started/common/nix_installation/index.html [10/06/2025 18:26] tholin I guess I'll have to [10/06/2025 18:30] tholin I prefer docker images because they're easy to set up and easy to remove [10/07/2025 14:05] tholin Adding more cells to my 3.3v SCL again finally. [10/07/2025 14:06] tholin Its just gonna be a big heap of AOI and OAI parts for the next few days. [10/08/2025 00:22] mithro_ The whole AOI/OAI/etc cells seems like ripe for some type of automation. [10/08/2025 09:41] tholin I don't see how. Implementing that would just take longer than me doing it myself. [10/08/2025 09:47] tholin If you want cells of perfect performance and density, I don't believe there is a way to get that through computer code. Not without more effort than its worth, since every PDK has its own rules and quirks and so you'll need to update the entire codebase for each new one. [10/08/2025 10:10] algofoogle Is automated generation of standard cell layouts something @htamas worked on, experimentally? https://github.com/htfab/cell-tester {Embed} https://github.com/htfab/cell-tester GitHub - htfab/cell-tester Contribute to htfab/cell-tester development by creating an account on GitHub. 2025-10_media/cell-tester-2A6B9 [10/08/2025 10:10] 246tnt C4M has some code to generate cells automatically based on rule set, but I agree with @Tholin that this won't yield the best layout possible. It's all a trade-off ... I'll be interesting to see the delta. [10/08/2025 13:10] mithro_ If you are in Australia, there is now a FOSSi Foundation event -> https://fossi-foundation.org/downunderflow/2026 {Embed} https://fossi-foundation.org/downunderflow/2026 Down Underflow 2026: February 28, 2026 in Sydney, Australia The Down Underflow conference is a weekend of presentations and networking dedicated to free and open source silicon. It's an event for the open source semiconductor community, and is run by volunteers from the FOSSi Foundation. Down Underflow 2026 is on Saturday February 28, 2026 in Sydney, Australia. {Reactions} 🎉 (3) [10/09/2025 11:44] mithro_ About to give a talk in Singapore at Hackware -> https://engineers.sg/organization/hackware--111 {Embed} https://engineers.sg/organization/hackware--111 Organization: Hackware - Engineers.SG Hackware is a monthly meetup for hardware developers and enthusiasts to share hacks and developments in the hardware scene, promote hardware development and to build a community of hardware developers. Our talks typically include projects by speakers on electronics, embedded system, radio communications, internet of things and much more! 2025-10_media/square-cover-9ABFC.jpg {Reactions} 💜 [10/09/2025 12:43] tholin I’m having troubles with the template. Its been stuck on "Filler Generation" for almost an hour, I think, and that’s probably because half of its memory usage is in Swap by now. [10/09/2025 12:44] 246tnt I never tried on GF180 but on IHP, fill takes a while and yeah, needs a _lot_ of ram. If you don't have the physical ram for it, you can forget it. Use a VM on some cloud provider or that'll never finish. [10/09/2025 12:45] tholin What does this step even do? [10/09/2025 12:45] 246tnt It add small rectangles all over the place to meet the density requirements of each layer, making sure all those dummy rectangle don't interfere with the rest of the circuit ... [10/09/2025 12:48] tholin Ah yes, minimum density requirements [10/09/2025 12:48] tholin I think I ran into that before, but on PCB layouts. Its weird. [10/09/2025 12:49] tholin JLC has some obscure minimum density rules, you’re just unlikely to run into them in 99% of cases. [10/09/2025 12:53] 246tnt The density here to meet doesn't seem too bad ( 30% ) but there rules are a bit unusual vs sky130 because you have minimum distance between dummy metals and the metals from the layer above and below which is not the case in sk130/ihp. [10/09/2025 13:00] tholin I don’t remember a Filler Generation step being required during GFMPW [10/09/2025 13:01] 246tnt It was done by the foundry or efabless. [10/09/2025 13:02] 246tnt Same for seal ring AFAIK. [10/09/2025 16:22] mole99 Filler generation runs in tiled mode, meaning that KLayout assigns each CPU thread a part of the layout to work on. The size of the tile and the maximum number of threads in use define the RAM usage. These can be changed in `gf180mcu/gf180mcuD/libs.tech/klayout/tech/drc/filler_generation/`: `tile_size` is defined individually in each script, and `$threads` is defined in `fill_all.rb`. [10/09/2025 16:22] tholin Its pinning all my CPU threads at 100%, so this is definitely working. [10/09/2025 16:23] tholin The flow completed after 2 hours of runtime. [10/09/2025 16:23] mole99 I'll add some proper variables to LibreLane. You should already be able to limit the threads directly in LibreLane, however that would also mean you limit the threads for detailed routing etc. [10/09/2025 16:24] mole99 If you're swapping memory, then filler generation will take much longer than necessary. [10/09/2025 16:25] mole99 Yes, sealring and filler cells were added by GF for the GFMPW runs [10/09/2025 16:25] 246tnt @Leo Moser (mole99) Does the filling respect all those rules across metal layers ? I had never seen those before. [10/09/2025 16:26] 246tnt Things like `DM.4` ( https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_13_3.html ) [10/09/2025 16:27] mole99 The issue with the DRC rules with the layers above and below the dummy fill is that, since all standard cells contain poly2, you cannot insert any Metal1 fill. That's why, for now, I'm ignoring those rules... I'll see how far I get with that. [10/09/2025 16:27] 246tnt You really shouldn't need any M1 fill though, the standard cells should provide enough metal inside themselves ? [10/09/2025 16:28] mole99 That might be true. However, if you have dense routing on any layer, that would also prevent you from generating any fill the layers above and below it. [10/09/2025 16:29] mole99 I would like to know what is the reasoning behind this rule, maybe GF can asnwer me that once I submit the first reticle. Capacitive coupling perhaps? Or manufacturing reasons? 🤷‍♂️ [10/09/2025 16:30] 246tnt My guess would be capacitive coupling. [10/09/2025 16:37] mole99 Which might be important to consider for sensitive analog designs, but not so much for digital. At least on sky130 and ihp-sg13g2 we didn't care much ^^ [10/09/2025 23:23] mbalestrini I took some photos of a GFMPW-1 chip @Tim 'mithro' Ansell sent me. It's the A8, LeoSoC project: https://mbalestrini.github.io/chip_images/GFMPW-1-LeoSoc.html [10/09/2025 23:31] mbalestrini {Attachments} 2025-10_media/gfmpw1-LeoSoC-20251009_143310-DSC02918-0BCD8.jpg 2025-10_media/gfmpw1-LeoSoC-20251005_200650-DSC02901-60FC6.jpg 2025-10_media/gfmpw1-LeoSoC-20251005_185755-DSC02884-F8F7B.jpg 2025-10_media/gfmpw1-LeoSoC-20251005_193852-DSC02897-729AB.jpg {Reactions} 🤤 (3) [10/10/2025 02:02] algofoogle So good, Maximo! {Reactions} ❤️ [10/10/2025 06:21] mole99 Beautiful photos! Thank you for taking them, Maximo 🙌 {Reactions} ❤️ [10/10/2025 06:26] 246tnt What's you setup for taking those ? [10/10/2025 10:38] tholin @Leo Moser (mole99) I think I do have a GDSII for you for the virtual tapeout. I don’t like having standard cells in my top-level layout and prefer the efabless user project area setup where its just placing and connecting macros. So I replicated that and I can give the GDSII for that for checking. [10/10/2025 12:53] mole99 @Tholin, that would be great! That's fine, as long as you're using the project template. The reason is, the project template prepares the GDS with everything needed for tapeout, including sealring and filler cells. It also adds a QR code in the bottom left corner of the die, which will be replaced by the precheck with the actual ID. I might do some more changes on the filler generation before sending it out, so I might need to regenerate your project locally. Please create a fork of the project template repository, customise it to your needs and share it with me. [10/10/2025 13:06] tholin Running the precheck locally is kinda difficult right now, btw, because `nix-shell` starts building stuff from source. [10/10/2025 13:52] mole99 There's no need to run the precheck now. I'll do some more work on it after the virtual tapeout. Simply building the design using the project template is fine. However, there OpenROAD also needs to be build when calling `nix-shell`. This is because we're currently using a branch of LibreLane and therefore not all binaries are cached. This will improve once most of the changes have been upstreamed. [10/10/2025 14:07] mbalestrini This time I used a Sony A7C2 Most of the photos were taken with this 50mm 1.8 Sony lens and some 3d printed extension tubes (the problem is that I can't control focus or aperture with that lens and the extensions) I also use an old Minolta macro lens which gives me more control, but I think is not that sharp For lightning I mostly use a led flashlight and in a couple of these direct sunlight {Attachments} 2025-10_media/PXL_20251010_135904851-12305.jpg {Reactions} 👍 (3) [10/10/2025 14:25] 246tnt I need to get myself some extension tubes, see what I can capture wihth that. {Reactions} 🤞 [10/10/2025 23:02] tholin Here 'ya go! https://github.com/AvalonSemiconductors/ws-submission-2025 [10/10/2025 23:03] tholin Let me know if there is any problems with it, otherwise I will continue to develop this repo into a proper submission. I’ll (hopefully) have a slot in the december tapeout. [10/11/2025 03:25] storborg Do you have a process for cleaning the die before shooting? [10/11/2025 04:36] furanfuranfuran greetings [10/11/2025 07:30] mithro_ Video from my talk in Singapore is now up at https://www.youtube.com/watch?v=0nqV9Eo17wA {Embed} Engineers.SG https://www.youtube.com/watch?v=0nqV9Eo17wA Open source silicon and wafer.space - $7k for 1,000 custom ICs - Ha... Speaker: Tim Ansel Event Page: https://www.facebook.com/events/759331036899554 Produced by Engineers.SG 2025-10_media/maxresdefault-DD65E.jpg {Reactions} 👍 (4) 🔥 (2) [10/11/2025 08:08] mole99 Started a thread. [10/11/2025 14:01] mbalestrini No, I have to find one. These one were decently clean so I took the photos before trying to clean them [10/11/2025 15:40] polyfractal just finished the Amp Hour episode, really interesting! Was fun to hear some more of the backstory and general thoughts on the project 🙂 {Reactions} 💜 [10/11/2025 15:51] anfroholic :bitmap: [10/11/2025 15:51] anfroholic :bitmap: [10/11/2025 15:53] anfroholic :waferspace: {Reactions} waferspace [10/11/2025 15:54] anfroholic :waferspace: [10/11/2025 15:55] anfroholic Didn't realize it posted things. Anyways.. New Emoji!! {Reactions} waferspace (8) [10/12/2025 03:30] mithro_ At some point I'm going to have to do an animated version of that logo. [10/12/2025 03:31] anfroholic That would be sweet!! [10/12/2025 07:32] urish Yes please [10/14/2025 17:48] hardwall I'm curious if you tried reaching out to other open source silicon initiatives like ZeroRisc? There seems to be some movement in that direction from other people as well. [10/15/2025 01:10] mithro_ I was in contact with the OpenTitan team when I was at Google but haven't really been following them since the first round of Google layoffs hit them. I did talk to someone from LowRISC at LatchUp. [10/15/2025 01:11] mithro_ Feel free to forward things their way if you have contacts [10/17/2025 08:44] always_ff_rohan can we get a full 4k wallpaper version? [10/17/2025 13:11] mbalestrini On the web you can download the full camera resolution version: https://mbalestrini.github.io/chip_images {Reactions} 👍 [10/17/2025 13:12] mbalestrini Some are cropped so they have less pixels [10/18/2025 03:52] anfroholic @mbalestrini These are really wonderful. Would you mind if we posted these other places? [10/18/2025 13:09] mbalestrini You can use them! All the photos I upload to that page have a Creative Commons CC0 license {Reactions} 💜 (2) [10/18/2025 13:10] anfroholic Thank you!! [10/18/2025 13:12] mbalestrini You can get the photos from the repo also: https://github.com/mbalestrini/chip_images {Embed} https://github.com/mbalestrini/chip_images GitHub - mbalestrini/chip_images: Collection of photos and videos r... Collection of photos and videos related to the Google's sponsored Open MPW Shuttle Program - mbalestrini/chip_images 2025-10_media/chip_images-2D357 {Reactions} 💜 [10/26/2025 06:20] mithro_ BTW Bits of https://platform.wafer.space could use testing, checking the login works for you. Check the upload flow works, etc. {Embed} https://platform.wafer.space/ Welcome to wafer.space … Platform for wafer.space low cost silicon manufacturing. [10/26/2025 07:35] anfroholic I created an account using Github and it all seemed to work well for me [10/26/2025 13:53] tholin Same [10/26/2025 13:54] tholin How is this platform site being developed? Is there a GitHub repo for it? [10/26/2025 14:23] anfroholic Afaik @Tim 'mithro' Ansell is doing most of the development. I don't believe it's open. [10/26/2025 14:25] tholin Ah. I was going to offer some help. I do have almost 6 years of professional web dev experience, even though its not my favorite thing. {Reactions} 💜 [10/27/2025 02:39] mithro_ I do plan to have the platform public under an Apache 2.0 license. [10/27/2025 02:39] mithro_ Mostly developed myself with Claude Code. [10/27/2025 02:54] mithro_ @Tholin - I think it makes more sense for you to concentrate on doing more cool silicon stuff rather than boring webdev work. [10/27/2025 12:00] tholin Webdev isn’t necessarily boring - especially when its about ensuring people’s cool silicon project files make it to the fab safe and sound. [10/27/2025 13:37] mole99 Started a thread. [10/27/2025 13:45] tholin Thrown together in two hours: python script that automatically generates a padout diagram that is *roughly* to-scale from a librelane config. https://github.com/AvalonSemiconductors/ws-submission-2025/blob/main/padout_gen.py {Reactions} 👍 (2) [10/27/2025 13:45] tholin {Attachments} 2025-10_media/padout-BB965.png [10/27/2025 15:35] anfroholic This is awesome!! Tim has been asking me about creating a second option for a standard padring/cob. Do you have any requests/ recommendations/ insights? [10/27/2025 15:38] tholin The current padring in the template is incompatible with DIP-40 ceramic carriers as there is no VDD pad aligned with Pin 40 and no VSS pad aligned with Pin 20. [10/27/2025 15:38] tholin Although the latter is less severe [10/27/2025 15:38] tholin That is my only complaint {Reactions} 💜 [10/27/2025 15:39] tholin I guess you can also put the VDD and VSS on other pins, but that’d be going against the de facto convention. [10/27/2025 15:48] anfroholic So you're looking to bond the die directly to a carrier like this? Or you're wanting a pcb that has a matching pinout (like what you have drawn before?) > I guess you can also put the VDD and VSS on other pins, but that’d be going against the de facto convention. There really are no real standards yet, and that's what I'm trying to get to the bottom of. Even within the 74pad standard we're already seeing variations like @peterkinget and his students here: https://discord.com/channels/1361349522684510449/1429068742108909638/1429520076536811622 I guess that I'm just missing some vital information, which really needs to come from the wirebonders and their needs/ desires. Thank you {Attachments} 2025-10_media/Untitled-E3E7D.jpg [10/27/2025 15:53] tholin I do mean one of those carriers [10/27/2025 15:57] tholin Generally, VDD is in the top-right corner and VSS in the bottom-left corner of most DIP chips. [10/27/2025 15:59] tholin For my multi-project die, I have fully customized the padring at this point. I have three designs on there that can go into DIP-40 packages, with the added difficulty that each has to have the clock pin in a different place. So I had to get a bit creative with placement of the clock pad so bond wires can reach it from all those possible pins. [10/27/2025 16:01] tholin NOT to scale {Attachments} 2025-10_media/pads-CD341.png [10/27/2025 16:11] tholin It’ll probably be a while until I can get my hands on any DIP carriers. Sometimes some show up on ebay randomly, but the actual source only has "Request Quote" on the website with mandatory "Company Information" fields. Typical. [10/27/2025 16:11] tholin Whenever I see that, I just choose to interpret that as "Too expensive to bother anyways" [10/27/2025 16:12] tholin But it’d be fun to experiment with if I ever manage to source some. [10/27/2025 16:12] tholin Would look so cool on a demo board. {Reactions} 💜 [10/27/2025 17:16] markemer 8.5 bucks a chip with wirebonding or 7 bucks without is tempting as hell. I think I could sell them (provided I ship a design that works) - just gotta get that cash together. {Reactions} 💜 [10/27/2025 17:17] markemer Has anyone ever done packaging as an OEM. I did package design at IBM and wirebonding in gradschool, but never actually got like a DIP or QFN made [10/27/2025 17:17] markemer are their vendors for that that won't cost more than the damn chip manufacturing? [10/27/2025 17:29] anfroholic You can join the discussion in #cob where we're talking about packaging as a chip-on-board. Currently it seems the frontrunner is to have a 74pad die wirebonded to a breakout attached to a 70pin mezzanine connector. {Reactions} ❤️ [10/27/2025 19:21] anfroholic New update just dropped: ## Professional Design Support: Your Options for GF180MCU Success read it [here](https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/getting-help) {Embed} https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/getting-help Professional Design Support: Your Options for GF180MCU Success Professional paid engineering services are available if you want to accelerate your timeline, get expert review, or have someone handle parts (or all) of your design. 2025-10_media/wafer-space-getting-help_png_open-graph-600AB.jpg [10/27/2025 19:23] tholin Since I have the most experience with GF180MCU, I do wonder if there is any knowledge I could pass on in the form of guides. I just don’t know what that would be. [10/27/2025 19:25] tholin I wonder if it'd be worth mentioning that tons of reference designs already exist to clone and use, whether in whole or in part. I don’t license all my projects Apache 2.0 for nothing. [10/27/2025 19:27] anfroholic For sure! I think @Tim 'mithro' Ansell is still looking for a few more topics for updates. I had floated the idea of edit:*[features of]* TinyTapeout and MosBius but would love to add some of yours as well!! [10/27/2025 19:28] tholin The only thing I have that I am proud of that is ready to use would be the components of the AS2650v2 microcontroller. [10/27/2025 19:28] anfroholic Sweet!! [10/27/2025 19:28] tholin Its fully verified [10/27/2025 19:28] tholin And uses the fab SRAM macros [10/27/2025 19:28] tholin I think very people managed to figure out how to even use those [10/27/2025 19:29] tholin If anyone ever asks about the fab SRAM, I just direct them to my repo: https://github.com/AvalonSemiconductors/AS2650 {Reactions} 💜 (2) [10/27/2025 19:30] anfroholic This is ready for GF180MCU? [10/27/2025 19:31] anfroholic I've added this in his stuff, Thank you!! [10/27/2025 19:32] tholin Yeah. I taped this out @ GFMPW-1 and Tim has samples of it. Though keep in mind that the repo was thus made with the efabless caravel user project. [10/27/2025 19:32] tholin I could port it to the wafer.space template if demand exists. {Reactions} 💜 (2) [10/27/2025 19:32] anfroholic Up to Tim really. I like the sound of it though! [10/28/2025 03:25] mithro_ @Tholin / @Leo Moser (mole99) - I just made the repo public [10/28/2025 14:11] tholin Okay, so, this multi-project die is going to contain replicas of old retro chips and some of those are actually clocked on the negative clock edge. I wish to be cycle-accurate, so I am wanting to preserve that behavior. But LibreLane kinda doesn’t like it if I use negedge. {Reactions} 💜 (2) [10/28/2025 14:11] tholin I believe its still constraining the top-level module output ports to the positive clock edge. [10/28/2025 18:03] rebelmike You'll need to tweak the sdc - something like this: https://github.com/TinyTapeout/ttsky25a-tinyQV/blob/main/src/base.sdc#L25-L26 [10/30/2025 19:00] anfroholic A really cool talk from @bunnie from Teardown where's he's talking about getting back into silicon was just uploaded. Thanks for doing this talk bunnie, it was super cool. Love the computer architecture and your inter-processor network, so cool! Also a small namedrop for wafer.space at 29:21 https://www.youtube.com/watch?v=pxQCApAAT0s {Embed} Crowd Supply https://www.youtube.com/watch?v=pxQCApAAT0s Teardown 2025 - bunnie - Trusting Hardware Noted hacker, designer, product creator, and author (Precursor, Novena, "The Essential Guide to Electronics in Shenzen") bunnie Huang shares his experiences researching how to establish trust in hardware. *About the Speaker* bunnie is best known for his work hacking the Microsoft Xbox, as well as for his efforts designing, manufacturing and wr... 2025-10_media/maxresdefault-E02E5.jpg {Reactions} 💚 ❤️ (4) ============================================================== Exported 231 message(s) ==============================================================