wafer.space Community

And finally, here are the docs for my multi-project die. There is a LOT on this one, so I’m sorry it took me a while. https://avalonsemiconductors.github.io/WS2025/index.html

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Btw if anyone wants an excuse to come to Australia, check out https://fossi-foundation.org/downunderflow/2026

Down Underflow 2026: February 28, 2026 in Sydney, Australia

The Down Underflow conference is a weekend of presentations and networking dedicated to free and open source silicon. It's an event for the open source semiconductor community, and is run by volunteers from the FOSSi Foundation. Down Underflow 2026 is on Saturday February 28, 2026 in Sydney, Australia.

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The AS2650v2 consumes exactly 1W of power at 40MHz

Tholin

The AS2650v2 consumes exactly 1W of power at 40MHz

what does the power report for it say? that seems odd.

I don’t know

4:19 p.m.

I designed this over a year ago

Leo Moser (mole99)

We stitched the reticle and sent it to GF on Monday. However, we received a number of violations. The next step is to sort through them, to see which ones can be waived, and which ones need to be fixed. Due to the holidays, things are moving a bit slowly at the moment, though :)

Any update on this? Happy new year by the way

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I was just wondering the same

9:34 a.m.

But then maybe the fact we didn't hear anything is good news ...

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it's all been a very elaborate scam and Tim has absconded with the money

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Thorben

Any update on this? Happy new year by the way

Happy New Year, everyone! Yes, there are updates: There were some issues with missing metal slots in some designs, mostly on the logos. The project authors have been notified and asked to review the updated layouts with the generated metal slots. I submitted the updated reticle yesterday evening, so GF had it first thing on Monday morning. We'll let you know as soon as we hear back from GF.

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Assuming this goes well, how's the production timeline affected?

urish

Assuming this goes well, how's the production timeline affected?

I'm not sure, that's for @Tim 'mithro' Ansell to say. It depends on how the deadlines are spaced on GF's side.

I should have a new timelime published in the next week or so.

9:11 p.m.

Will post an announcement in #announcements when we have clarity on that.

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https://www.zerotoasiccourse.com/post/year_update_2025/#best-of-2025

Review of 2025 and goals for 2026

For the first time, open silicon wasn’t just a niche experiment in 2025 - it was a real ecosystem spanning three fabs and thousands of designs. And then one company collapsed and hundreds of chips effectively disappeared overnight. Efabless going out of business at the end of February hit the community like a hammer. They weren’t just an MPW...

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Hello fams Happy new year I hope everyone doing very well Is there anyone looking for skilled senior full stack AI/ML engineer?

Hi. No

7:24 p.m.

Does full stack mean you design the TPUs?

Hi everyone! Still awaiting a timeline from GF. When I get that I'll post an announcement.

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@Leo Moser (mole99) any progress on an image of the whole reticle?

Matt Venn

@Leo Moser (mole99) any progress on an image of the whole reticle?

Yes, but I'm also waiting for the final confirmation before I publish the image and reticle with the open source projects.

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Someone was asking about OpenROAD design tuning or something? https://antmicro.com/blog/2026/01/multi-objective-optimization-for-autotuner-in-openroad ( @BreakingTaps was that you?)

Multi-objective optimization in AutoTuner for efficient ASIC design...

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12:09 a.m.

Someone else was asking about power consumption? https://antmicro.com/blog/2025/07/power-estimation-in-openroad-using-saif-in-verilator (edited)

Power estimation in OpenROAD using SAIF in Verilator

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Hi there Who needs developer?

TG

Hi there Who needs developer?

We don’t need developers; we have AI!

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asic destroyer

We don’t need developers; we have AI!

we don't need AI either.

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Lofty

we don't need AI either.

We don’t need compilers or toolchains either, old-school dudes just hardwiring everything from scratch.

asic destroyer

We don’t need compilers or toolchains either, old-school dudes just hardwiring everything from scratch.

but compilers and toolchains are not AI.

Lofty

but compilers and toolchains are not AI.

but tools like AI (edited)

asic destroyer

but tools like AI (edited)

but AI is not a tool

Then what?

With AI you're the tool ...

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asic destroyer

We don’t need developers; we have AI!

Sarcasm, btw. I thought it was a spam message, and that was just my kind of humor in responding to it. (edited)

Hi

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@Tim 'mithro' Ansell @Leo Moser (mole99) So any news on the timeline by any chance ?

tnt

@Tim 'mithro' Ansell @Leo Moser (mole99) So any news on the timeline by any chance ?

They apparently have received the first three reticles but have not yet got be a wafer fab out date yet.

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Why does GF require COMP and N+ or P+ layers? Would you ever use P+/N+ without it being an active region?

BreakingTaps

Why does GF require COMP and N+ or P+ layers? Would you ever use P+/N+ without it being an active region?

@BreakingTaps Not sure what you're asking. COMP, N+, P+ are separate mask layers. Are you suggesting just using N+ and P+ and calculating the COMP mask layer from those?

sorry, poorly worded. My understanding is that you need COMP + [N+ or P] to define an active region. COMP by itself doesn't do anything, and I don't understand what N+ / P+ would equal if it wasn't also sitting on top of COMP. Basically my question is why have COMP as a layer at all

2:09 a.m.

oh I see, they are actual physical mask layers. Implementation detail leaking to the user

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Tim 'mithro' Ansell

They apparently have received the first three reticles but have not yet got be a wafer fab out date yet.

3?

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Masks is what I think they mean.

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@BreakingTaps The N+/P+ region extend beyond COMP because those masks/process are not as precise.

6:43 a.m.

So AFAIU COMP will define the STI region and the the implantation is done later and not as precise as the STI etch and so needs to extend beyond the active region to make sure it's covered and uniform and all that.

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@Tim 'mithro' Ansell are there any left over masks sill in the states that I can get ahold of to hang on the wall at PS1?

@carlfk - that is a complicated question best not answered on the public channel

After the tapeout, would anyone be interested in a casual video call to celebrate and chat?

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For those who haven't been reading between the lines. GF has created the reticle, already has a number of masks and production has begun!! waferspace

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tnt

So AFAIU COMP will define the STI region and the the implantation is done later and not as precise as the STI etch and so needs to extend beyond the active region to make sure it's covered and uniform and all that.

gotcha, makes sense, thanks! Still seems like an implementation detail they could hide from the user

BreakingTaps

gotcha, makes sense, thanks! Still seems like an implementation detail they could hide from the user

The N+/P+ has to enclose COMP by a certain amount but also they have to be a minimal distance from each other. So if you draw PCOMP and NCOMP only you need to generate the N+/P+ out of it with the right sizing plus filling of small spaces. This become quite complicated and even pretty difficult for two corner that are diagonallly too closo to each other. I prefer that PDKs allow me to draw COMP and N+/P+ separately and decide myself which N+/P+ regions to join into one.

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ahh ok I see. cheers for the extra details

asic destroyer started a thread. 2026-01-21 5:38 p.m.

Sorry for spammer all.

Moving this to general: @CatIsFluffy: Why does one of them have a padring inside the normal padring?

Leo Moser (mole99)

Moving this to general: @CatIsFluffy: Why does one of them have a padring inside the normal padring?

It's a re-tapeout of a Chipathon 2025 design, see here for more: https://github.com/AutoMOS-project/AutoMOS-chipathon2025/tree/update-for-ws

Leo Moser (mole99)

Moving this to general: @CatIsFluffy: Why does one of them have a padring inside the normal padring?

(Sorry, I didn't notice what channel that was in.)

CatIsFluffy

(Sorry, I didn't notice what channel that was in.)

No worries! We have yet to disable normal posts there :)

Andrew Wingate

Click to see original message

Did I get the time right?

Tim 'mithro' Ansell

Did I get the time right?

Yes, it's the time and date that Hirosh had suggested.

For people in the US, I highly recommend https://www.crowdsupply.com/teardown/portland-2025/updates/teardown-2026-dates-tickets-and-cfp

Teardown 2026: dates, tickets and CFP

Announcing Teardown 2026: dates, tickets, call for participation, volunteering opportunities, and more!

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Reminder of WSRUN1 - Video Call Celebration https://discord.com/events/1361349522684510449/1464021932084170875 We will all be joining in the voice channel on this server here: https://discord.com/channels/1361349522684510449/1467064723265818635

Howdy all. Is anyone talking in the event? I hear Discord audio, but can't hear anybody speaking, or see any cameras.

algofoogle (Anton Maurovic)

Howdy all. Is anyone talking in the event? I hear Discord audio, but can't hear anybody speaking, or see any cameras.

Multiple people are talking and @Leo Moser (mole99) is presenting

Cheers Tim. Sorted out my audio after a while

@Tim Edwards - Could you add your new 3v3 SRAM into the spreadsheet @ https://docs.google.com/spreadsheets/d/1fW5ecBsLSec4hXBMaOjMUHQGslm4y-QUILgrxqS8MpA/edit ?

GF180MCU SRAM Sizing

10:22 p.m.

@BreakingTaps - It would be great to add the stuff you did around DFFRAM too.

Thank you all for taking part in today's call! I'm looking forward to seeing the actual chips working

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