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Between 02/28/2026 23:59 and 04/01/2026 00:00
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Tim 'mithro' Ansell 03/01/2026 22:19
@Leo Moser (mole99) - I like to describe wafer.space as a "Low volume silicon manufacturing." rather than a "MPW service" -- MPW has a bunch of ideas / connotations associated with it that I would like to get away from.
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Tim 'mithro' Ansell 03/01/2026 22:27
I really would like people to stop thinking of wafer.space for "prototyping" and think of it more as "I need 1,000 chips manufactured"
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waferspace 1
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Tim 'mithro' Ansell
@Leo Moser (mole99) - I like to describe wafer.space as a "Low volume silicon manufacturing." rather than a "MPW service" -- MPW has a bunch of ideas / connotations associated with it that I would like to get away from.
Leo Moser (mole99) 03/02/2026 08:38
Alright, I'll keep that in mind!
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tnt 03/02/2026 19:17
Any admin to ban this clown ?
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tannewt 03/03/2026 00:09
👋
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Tim 'mithro' Ansell
Just gave the following presentation at Down Underflow 2026 at https://wafer.space/du26
Tholin 03/05/2026 16:04
So I get to see soon what my dies look like? Many more weeks before I get to find out if they work, but seeing what they look like on the wafer will be exciting already.
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Jason Yang 03/06/2026 04:52
hello!
Leo Moser (mole99) started a thread. 03/06/2026 09:21
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Tim 'mithro' Ansell
I really would like people to stop thinking of wafer.space for "prototyping" and think of it more as "I need 1,000 chips manufactured"
carlfk 03/06/2026 16:59
it is the only sensible way to get qty:1000 right?
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Jason Yang 03/06/2026 19:33
hmm is there no way to use Verilator when simulating sram with foundry provided sram IPs?
19:34
19:34
looking at this rn.
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Tim 'mithro' Ansell 03/09/2026 03:03
New video from @BreakingTaps - https://www.youtube.com/watch?v=y_SEZJPieWc
Breaking Taps
Channel Update: Custom Silicon and Cubesats
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BreakingTaps 03/09/2026 16:43
more to come once the chips are here! stoked to dive deep into all the details 🙂
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Tholin 03/12/2026 09:15
I used a custom padframe. Does that mean I get to submit my own gerber of a COB breakout? I have one prepared. The component placement is the exact same, just the routing is different.
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BreakingTaps
more to come once the chips are here! stoked to dive deep into all the details 🙂
Tim 'mithro' Ansell 03/12/2026 23:08
Hopefully things arrive before the end of April, so you haven't got that long to wait!
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Tholin
I used a custom padframe. Does that mean I get to submit my own gerber of a COB breakout? I have one prepared. The component placement is the exact same, just the routing is different.
Tim 'mithro' Ansell 03/12/2026 23:09
For the first shuttle we can probably make this happen, can you add a note with this information to the Google Form submission?
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Tim 'mithro' Ansell
Hopefully things arrive before the end of April, so you haven't got that long to wait!
BreakingTaps 03/12/2026 23:10
sooner than I was expecting! figured we still had a while 🙂 Regarding the form, if I select n number of bare die is it assumed the rest will be COB mounted?
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Tim 'mithro' Ansell
For the first shuttle we can probably make this happen, can you add a note with this information to the Google Form submission?
Tholin 03/12/2026 23:20
Done
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BreakingTaps
sooner than I was expecting! figured we still had a while 🙂 Regarding the form, if I select n number of bare die is it assumed the rest will be COB mounted?
Tim 'mithro' Ansell 03/12/2026 23:22
You should be able to select options in both columns?
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BreakingTaps 03/12/2026 23:23
I can, they just don't add up to 1000 so I wasn't sure which took precedence 🙂
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Tim 'mithro' Ansell 03/14/2026 22:08
@Tholin / @Tim Edwards - Anything interesting in the paper @ https://ieeexplore.ieee.org/abstract/document/11420759/ for potentially generating new standard cell libraries for gf180mcu?
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Tholin 03/14/2026 22:16
Why would I generate standard cell layouts? Why would I skip the fun part?
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22:16
Its everything else after that that I’m trying to automate. I want to set up a whole CI pipeline for characterization and liberty file generation.
22:17
I already have one for generating all the other output formats from the .mags
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Tholin
Why would I generate standard cell layouts? Why would I skip the fun part?
Lofty 03/14/2026 23:40
To me at least, while it's certainly fun to make cell layouts, it'd ease the bootstrapping of "having an initial cell library to then improve on". Even when hand-drawing cells I ended up macroing the living daylights out of it anyway for exactly the reason of "trying to have something now" ^^;
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Tim 'mithro' Ansell 03/18/2026 01:38
I asked Claude.ai to look at the ws-run1 reticle and examine the various standard cell / transistor densities -- this is what it came up with https://github.com/wafer-space/ws-run1/blob/density-report/reticle_density_report.md which seems somewhat plausible. The raw data it calculated is found at https://github.com/wafer-space/ws-run1/tree/density-report Would love some independent verification if it got things totally wrong. I tried to make it include all it's sources and methodology.
ws-run1/reticle_density_report.md at density-report · wafer-space/...
wafer.space GF180MCU Run 1. Contribute to wafer-space/ws-run1 development by creating an account on GitHub.
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GitHub - wafer-space/ws-run1 at density-report
wafer.space GF180MCU Run 1. Contribute to wafer-space/ws-run1 development by creating an account on GitHub.
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Tim 'mithro' Ansell 03/18/2026 02:12
If anyone has time, I could also use some help reviewing the update to the wafer.space website - https://preview.wafer.space/pr-78/ -- It's a pretty big update and I'm not sure I haven't missed something silly.
wafer.space - Budget silicon manufacturing.
Create integrated circuits without breaking the bank!
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Pazzy 03/19/2026 21:53
4$ per chip on such a low volume seems so crazy (in a good way!)
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21:53
Very impressive
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Brian Swetland 03/19/2026 22:06
The $4K half-size options are tempting (starting to fall inside my budget for "big hobby project / experiment"). Makes me want to find some time to play with the PDK and get a feel for the tools and maybe start exploring a project for the next run.
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Pazzy 03/19/2026 22:11
My analog prof has been looking for an excuse to try out GF180MCU for some analog projects. That might be the little push / excuse to try it out for him 😄
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Tim 'mithro' Ansell 03/20/2026 09:53
For the bit serial fans -> https://arxiv.org/pdf/2603.14988
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Pazzy
4$ per chip on such a low volume seems so crazy (in a good way!)
Tim 'mithro' Ansell 03/20/2026 09:54
My goal is to figure out how to get to ~$1 USD per die packaged -- still a long way to go.
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Tholin 03/20/2026 10:09
Ah, this reminds me I wanted to start work on my automatic multi-project die configurator
Tholin started a thread. 03/20/2026 11:54
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Tholin 03/20/2026 12:25
I also really want to create a bidir IO pad that is fast at 3.3V so I can finally make use of my custom SCL
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Tim Edwards 03/20/2026 13:46
@Tholin : I will be able to get measured results from my dual-voltage pads, and your standard cells, from my chips on the first run. What speed are you hoping to achieve?
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Tholin 03/20/2026 13:46
The 5V pads max out before 15MHz when ran at 3.3V, so anything faster is an improvement.
13:47
I measured rise and fall times equivalent to 12.5MHz, I think
13:48
The 5V standard cells can actually go quite fast at 3.3V. Caravel had no problem running at 40MHz. The IO pads are the bottleneck.
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Tim Edwards 03/20/2026 13:48
@Pazzy : I am also interested in analog on GF180MCU. I am currently working on a shared-project frame and infrastructure for IHP, and would like to do the same for GF180MCU. How many projects would your professor expect to put on a chip? The frame I'm doing for IHP is similar to the one I did for sky130, which has room for about 12 to 14 projects, each with its own power supply and biases.
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Tholin 03/20/2026 13:49
(If the 5V cells with their big transistors can hit 50MHz, I am so excited to find out what my 3.3V cells can achieve)
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Tim Edwards 03/20/2026 13:51
@Tholin : My pads should be much faster than 5V pads running at 3.3V, although the external voltage will still be 5V. I may need to tweak the level shifter design for better speed; I didn't spend a lot of time analyzing it because at the time I was rather busy with the 3.3V SRAM layouts. Maybe for the next run I can do a set of all-3.3V pads, but if you're planning to do it, that frees me up for other useful things, like analog..
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Tholin 03/20/2026 13:52
Can you try getting me numbers on how your pads perform with the IO voltage also being 3.3V?
13:52
I actually really don’t want to have to make 3.3V pads myself, since I also want to make other useful things, like analog
13:53
I want to create a pad that has my digital-to-analog converter built in. 12 digital lines go in, one analog voltage appears on the pad.
13:54
I think I can make it fit
13:57
Making a 3.3V digital GPIO pad might be good practice, though
13:59
Actually, since you’ve created a custom GPIO pad, do you have a template for a blank pad structure? One that has just the upper metal layers, pad, transistors beneath the pad and ESD protection diodes, ready to have the specific circuitry for the pad’s function drawn in?
14:02
If you can get me that, I’ll make the rest of the 3.3V GPIO pad (I can adjust the transistors beneath the pad myself too)
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tnt 03/20/2026 14:52
AFAIK Tim modified the existing pads, he didn't start from scratch.
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Tim Edwards 03/20/2026 15:15
Yes, that's right. I just disassembled the schematic and layout, separated out the core-facing buffers in each direction, and replaced them with level shifters. It required a bit of layout re-work but it is still largely the same layout as the original. The problem with converting the pad cells to all 3.3V is that the ESD devices and the clamps are all designed for 5V and will have to be carefully redesigned, and like all such things, they can only really be validated by zap testing.
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Tholin 03/20/2026 15:18
I tried looking at the GF IO library files and its apparent to me that making those usable will require a bunch of re-work, yeah
15:18
Which is what I’ve actually been dreading
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Tim Edwards 03/20/2026 15:20
I can take a stab at it. These days most board-level systems run at 3.3V and it's getting harder to find 5V-compatible components, so I think a pure 3.3V I/O cell set would be very welcome.
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Tholin 03/20/2026 15:31
I’d still appreciate a blank template for me to build my DAC pad, thought I am slowly realizing I can probably create it myself from your pad layouts.
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tnt 03/20/2026 17:31
Quick spice sim of @Tim Edwards pad show the bi24_t toggling decently at 50 MHz at 3.3V.
17:33
~3.3 ns rise time ( 10-90% ) at 30 pF load. That's better than the sky130 pads do 😅 (edited)
17:37
( and for comparison about ~2.5 ns rise time at 5V )
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tnt 03/20/2026 18:08
Mmm, I wasn't using the latest stuff for gf180 but using the latest stuff I can't sim, I get an error 😅
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Tim Edwards 03/20/2026 19:17
See my message on fossi-chat; there's an error in the schematic for the bi_24t cell.
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tnt 03/20/2026 21:23
Results using the latest stuff : 3.3V : t_rise = 2.522358e-09 t_fall = 1.960298e-09 tdo_rise = 3.608585e-09 tdo_fall = 3.675327e-09 tdi_rise = 1.191578e-09 tdi_fall = 1.932958e-09 5V t_rise = 1.748877e-09 t_fall = 1.473875e-09 tdo_rise = 2.758279e-09 tdo_fall = 2.741741e-09 tdi_rise = 6.098016e-10 tdi_fall = 1.364941e-09
  • t_{rise,fall} are the rise/fall time at the output to a 30 pF load, measured 10-90%
  • tdo_{rise,fall} are the output delay ( from A input crossing 50% to PAD output crossing 50%
  • tdi_{rise_fall} are the input delay ( from PAD crossing 50% to Y ouptut crossing 50%
 (edited)
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tnt 03/20/2026 21:34
The 700 ps asymmetry on rising / falling edge on the input path is a bit surprising. But other than that, I think it's pretty good.
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J-Lo 03/20/2026 23:17
is this an accurate representation of the die size?
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J-Lo
is this an accurate representation of the die size?
Tim 'mithro' Ansell 03/21/2026 02:23
https://mbalestrini.github.io/chip_images/ might help?
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chasak 03/21/2026 05:04
looking at comparison, there is one difference that i observe. gf180 has a much larger pad frame than sky 130, can anyone tell me why
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tnt 03/21/2026 05:59
Sky130 is a smaller node and the sky130 pad are also quite packed. They also have "stuff" underneath the bond pad itself which gf180mcu doesn't.
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tnt 03/21/2026 08:09
@Tholin I'm curious how your measurements of the IO were made. I'm assuming on GFMPW-1 chips ? Looking at the caravel they're using the programmable drive pads and they are by default configured to the weakest 4 mA drive. I also looked at your multi project gfmpw-1 repo on github and you seem to be using the same as the caravel defaults so IO also configured for weakest drive.
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tnt 03/21/2026 08:34
Ran some simulation using the bi_t pads with min drive strength and I can reproduce (within +- 5%) the results from htamas measurement on gfmpw-1. I think at the time, we also didn't realize the programmable strength and left it at default too. Changing the drive strength from min to max goes from 9 ns rise time down to less than 2 ns in sim ...
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tnt 03/22/2026 07:31
FWIW, @htamas made new measurement and confirmed that at max drive strength, you get fall/rise time of 2.3~3.3 ns ( and this is measured with a 100 MHz scope so the bw limit of the scope is non negligible and we're probably in the <2 ns range of the sim ).
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Tim 'mithro' Ansell 03/23/2026 03:19
BTW @bunnie has some interesting thoughts about the RPi PIO and how an open source implementation should work at https://www.crowdsupply.com/baochip/dabao/updates/bio-the-bao-i-o-co-processor I would love to see what a bio might look like on GF180MCU where a bunch of the tradeoffs are different.
BIO - The Bao I/O Co-Processor
BIO is the I/O co-processor in the Baochip-1x. In this update, I’ll talk about the origins of the BIO, starting by working through a detailed study of the Raspberry Pi PIO as a reference before diving into the architecture of the BIO.
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Tim 'mithro' Ansell
BTW @bunnie has some interesting thoughts about the RPi PIO and how an open source implementation should work at https://www.crowdsupply.com/baochip/dabao/updates/bio-the-bao-i-o-co-processor I would love to see what a bio might look like on GF180MCU where a bunch of the tradeoffs are different.
Tim 'mithro' Ansell 03/23/2026 03:20
@RebelMike / @clever - I'd be interested in your thoughts.
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clever 03/23/2026 03:21
i do have some comments on how to RE PIO better
03:22
basically, if you set the state machine divisor really high, and hit the clockdiv reset bit, it will execute 1 PIO opcode, and then wait a large number of clocks, allowing you to turn execution off
03:22
with that, you can single-step the PIO
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Tim 'mithro' Ansell
BTW @bunnie has some interesting thoughts about the RPi PIO and how an open source implementation should work at https://www.crowdsupply.com/baochip/dabao/updates/bio-the-bao-i-o-co-processor I would love to see what a bio might look like on GF180MCU where a bunch of the tradeoffs are different.
Tim 'mithro' Ansell 03/23/2026 03:22
@Greg - Think that a serv based BIO might make sense for very low resource (but slow) version? What @bunnie did with the special registers fifo stuff might make sense for a multi-serv design?
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clever 03/23/2026 03:23
then there is a debug register, that tells you what direction/level PIO wants the pin to be in, even if you didnt pinmux it right so you can query the output as you single-step
03:23
and if you mux a pin as gpio out, you can drive it, and then PIO input will sense that level
03:23
so you can feed it dummy inputs, as you single-step
03:24
and i think the execute register, will force-execute an opcode on write, even if its disabled so you can force it to push x/y to the fifo and such
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clever
i do have some comments on how to RE PIO better
Tim 'mithro' Ansell 03/23/2026 03:24
I've had Claude working on https://github.com/mithro/rpi5-rp1-pio-bench -- I'm not super happy with the somewhat random mess it has made but it is at least more than I would have been able to do myself given current time constraints.
GitHub - mithro/rpi5-rp1-pio-bench: RP1 PIO benchmarking tool for R...
RP1 PIO benchmarking tool for Raspberry Pi 5 host-to-PIO data transfer performance - mithro/rpi5-rp1-pio-bench
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clever 03/23/2026 03:24
combine all of those together, and you can run some sample code on a real pico, playback a series of pin inputs, and record the pin/fifo outputs
03:25
then you have testcase data, that you can apply to verilog simulators
03:26
but its late here and i need to get to bed, ping me tomorrow and we can chat more
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Tim 'mithro' Ansell 03/23/2026 03:28
@clever - Sure! I'm somewhat more interested in an open standard like what bunnie is proposing, but given that the PIO blocks are out there, understanding them well is probably a worthwhile task.
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clever 03/23/2026 03:28
i can also see value in making some configurable verilog, so you can change anything you want
03:28
make X have more bits, or add more opcode slots
03:29
but i can also see how it might right into copyright issues? if your able to run PIO code un-altered
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bunnie 03/23/2026 04:32
I think if you can spend more effort on back-end and timing closure you could go with a more performant RV32 core. The PicoRV32 was chosen because i had basically one pass through the backend to meet timing at 700MHz or the project would be cut - I didn't want to take any risk on timing closure on the design side. This means you pay a high price in terms of CPI. Even a modest amount of pipelining would improve the CPI by several-fold, which can compensate for reduced frequency in GF180, plus if you have control over the back-end and can do multiple passes of optimization to improve the critical path...
04:33
The core-count is something you can directly scale based on how much area you have, i.e. there's still lots of useful things you can do with one or two BIO cores.
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RebelMike 03/23/2026 09:05
I think BIO looks great! Using RV32E + high registers for access to GPIOs and FIFOs is genius. As bunnie says it would be good to get higher CPI, and I think including the B extension would make sense given the kind of work the core will be doing. I might start from FemtoRV, the smallest version can do 2 CPI for most instructions - though I suspect PicoRV has a higher fmax. If I was doing an implementation for gf180, I’d use two SRAM blocks for instruction memory, to give 16 bit access per clock, matching 2 CPI - I already have a wrapper around FemtoRV that does this for my RV4028 project. Only 13 registers are needed (gp and tp can be dropped like TinyQV does) so those can be implemented in latches.
09:07
Would be cool to make a SoC with 2 or 4 of those plus maybe Hazard3 as the big core!
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RebelMike 03/23/2026 13:06
Does BIO use the top of the instruction memory for the processors stack? Regardless, I think that would make sense for this implementation, and would mean ra and sp could be restricted width as they only need to address that small RAM block (and they should always be word aligned). That still leaves 11 general purpose registers and should keep C compatibility.
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bunnie
I think if you can spend more effort on back-end and timing closure you could go with a more performant RV32 core. The PicoRV32 was chosen because i had basically one pass through the backend to meet timing at 700MHz or the project would be cut - I didn't want to take any risk on timing closure on the design side. This means you pay a high price in terms of CPI. Even a modest amount of pipelining would improve the CPI by several-fold, which can compensate for reduced frequency in GF180, plus if you have control over the back-end and can do multiple passes of optimization to improve the critical path...
clever 03/23/2026 20:51
i think the main design goal of PIO was to get 1 clock/instruction, and no delays due to loads, so it could emit a bit on every clock, at full 400mhz
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clever 03/23/2026 21:15
and also low gate count
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nmz787 03/24/2026 04:35
@Tim 'mithro' Ansell so for a whole undiced wafer on crowdsupply I need to select full slot?
04:35
Also is passing DRC strictly required to tapeout? Is there any waiver system? (For example making smaller than design rule pad sizes)
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nmz787
@Tim 'mithro' Ansell so for a whole undiced wafer on crowdsupply I need to select full slot?
Tim 'mithro' Ansell 03/24/2026 04:35
You need to have a slot on the run. The wafer has your design plus everyone elses design. Not just your own design.
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Tim 'mithro' Ansell
You need to have a slot on the run. The wafer has your design plus everyone elses design. Not just your own design.
nmz787 03/24/2026 04:37
Yes, so is it $7000 now (early bird bare dies) plus $2000 later?
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nmz787
Yes, so is it $7000 now (early bird bare dies) plus $2000 later?
Tim 'mithro' Ansell 03/24/2026 04:58
@nmz787 - You can purchase any slot size, a half slot would be fine -- just have to have something on the wafer. The per-wafer price is up front too.
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nmz787
Yes, so is it $7000 now (early bird bare dies) plus $2000 later?
Tim 'mithro' Ansell 03/24/2026 04:59
Oh - It seems you are pointing out that the wafers are not listed on the crowd supply site?
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nmz787 03/24/2026 04:59
Ok,i don't see the wafer option on crowdsupply purchase option drop downs (edited)
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nmz787
Ok,i don't see the wafer option on crowdsupply purchase option drop downs (edited)
Tim 'mithro' Ansell 03/24/2026 05:01
Yeap, it seems that forgot to be added and nobody noticed in review 🙂
05:02
@nmz787 - I expect it will either be added in the next hour or tomorrow morning US/Pacific time (The person who can change that info is in US/Pacific timezone).
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RebelMike
Does BIO use the top of the instruction memory for the processors stack? Regardless, I think that would make sense for this implementation, and would mean ra and sp could be restricted width as they only need to address that small RAM block (and they should always be word aligned). That still leaves 11 general purpose registers and should keep C compatibility.
bunnie 03/24/2026 05:03
yes, the stack is typically at the top of instruction memory. It's whereever you want to place the SP, but by convention that's where it goes.
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nmz787
Also is passing DRC strictly required to tapeout? Is there any waiver system? (For example making smaller than design rule pad sizes)
nmz787 03/24/2026 05:03
This is also of great interest, since my aim is to post process and reducing capacitance of analog inputs is a big goal.
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bunnie
yes, the stack is typically at the top of instruction memory. It's whereever you want to place the SP, but by convention that's where it goes.
Tim 'mithro' Ansell 03/24/2026 05:12
@RebelMike - You thinking TinyQV-BIO? 😛
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Tim 'mithro' Ansell
@RebelMike - You thinking TinyQV-BIO? 😛
RebelMike 03/24/2026 08:09
Not really - I think BIO makes most sense at low clocks per instruction so shouldn’t have a bit serial core. But I’m applying tricks from TinyQV to make it as small as possible, basically cutting down RV32E to the absolute minimum required for C support. Potentially as a test on Tiny Tapeout I might use TinyQV as the host, but the SoC would make more sense with a faster core.
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Lofty 03/24/2026 11:05
I need to work on my RV core more >.<
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tnt 03/24/2026 14:21
spam ...
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tnt
spam ...
Leo Moser (mole99) 03/24/2026 14:38
Thanks!
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Tim 'mithro' Ansell 03/25/2026 19:23
I'm off to Singapore today to manage the delivery, dicing and chip on board mounting of Run #1 silicon.
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waferspace 1
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RebelMike
Not really - I think BIO makes most sense at low clocks per instruction so shouldn’t have a bit serial core. But I’m applying tricks from TinyQV to make it as small as possible, basically cutting down RV32E to the absolute minimum required for C support. Potentially as a test on Tiny Tapeout I might use TinyQV as the host, but the SoC would make more sense with a faster core.
Tim 'mithro' Ansell 03/25/2026 19:40
I feel like the "real" interesting thing is more the register based synchronisation / queue stuff?
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Tim 'mithro' Ansell
I'm off to Singapore today to manage the delivery, dicing and chip on board mounting of Run #1 silicon.
nmz787 03/25/2026 20:59
isn't GF in upstate New York?
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tnt 03/25/2026 21:00
GF is a little bit everywhere.
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nmz787 03/25/2026 21:00
I guess that's the G
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tnt 03/25/2026 21:01
Yup. Here it's fab 3/5 I think.
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Tim 'mithro' Ansell 03/25/2026 21:09
They have fabs in Germany, Singapore and the US.
21:11
Each fab has a different set of process technologies and there is no process technology which can be manufactured at all locations - there are a very limited number of process techs that can be manufactured at two different locations.
21:13
Plane is taxiing! Talk to everyone later!
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BreakingTaps 03/25/2026 21:18
amusingly I've lived next to two different GF facilities (the one north of Troy, NY, and the one in Essex, VT)
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Tim 'mithro' Ansell
I'm off to Singapore today to manage the delivery, dicing and chip on board mounting of Run #1 silicon.
BreakingTaps 03/25/2026 21:18
Safe journey! Take lots of photos for us (if you can) 🙂
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Tim 'mithro' Ansell
I feel like the "real" interesting thing is more the register based synchronisation / queue stuff?
RebelMike 03/25/2026 22:06
True - but on the assumption this is running small programs that can fit in on chip SRAM, being limited to 8 or 16 clocks per instruction would be a shame (whereas when you're running direct from flash it's roughly on parity with the memory bandwidth). So I think it would be more interesting to focus on something that works well with that. I was thinking about the quantum stall. I think it would be better to choose the quantum (clock or triggered on a GPIO state/edge) on the basis of the value written to the register - a wide enough range of values can be generated with a single add immediate instruction so this wouldn't cost any instructions, and would make the trigger be defined in the program (and potentially could vary throughout the program) instead of having to be configured by the host
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RebelMike
True - but on the assumption this is running small programs that can fit in on chip SRAM, being limited to 8 or 16 clocks per instruction would be a shame (whereas when you're running direct from flash it's roughly on parity with the memory bandwidth). So I think it would be more interesting to focus on something that works well with that. I was thinking about the quantum stall. I think it would be better to choose the quantum (clock or triggered on a GPIO state/edge) on the basis of the value written to the register - a wide enough range of values can be generated with a single add immediate instruction so this wouldn't cost any instructions, and would make the trigger be defined in the program (and potentially could vary throughout the program) instead of having to be configured by the host
Tim 'mithro' Ansell 03/26/2026 03:01
Given a limited set of time, I think that sounds reasonable 🙂
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