Guild icon
wafer.space Community
Information / general
Welcome to wafer.space - documentation at wafer.space github - buy at buy.wafer.space - archives at discord.wafer.space
Between 03/31/2026 23:59 and 05/01/2026 00:00
Avatar
Tim 'mithro' Ansell 04/01/2026 00:41
Avatar
Tim Edwards 04/01/2026 13:54
@Tim 'mithro' Ansell : I noticed that the "Technical specifications" of the GF180MCU process on the wafer.space web page claim that the process has "MIM & PIP" capacitors. That is not true. A PIP capacitor (poly-insulator-poly) by definition requires two layers of poly. There are processes out there with double poly layers (particularly good for floating-gate devices, and yes, they do make good linear capacitors). GF180MCU is not one of them.
Image attachment
Avatar
Jason Yang 04/02/2026 01:21
Is anyone currently, or was able to utilize litedram for their project involving off-chip DRAMs? I'm currently working with it for a project I'm taping out here. So far I got some results, but it doesn't seem to be designed for working with ASICs. Neither does litex in general.
GitHub - enjoy-digital/litedram: Small footprint and configurable D...
Small footprint and configurable DRAM core. Contribute to enjoy-digital/litedram development by creating an account on GitHub.
Thumbnail
Avatar
Avatar
Tim Edwards
@Tim 'mithro' Ansell : I noticed that the "Technical specifications" of the GF180MCU process on the wafer.space web page claim that the process has "MIM & PIP" capacitors. That is not true. A PIP capacitor (poly-insulator-poly) by definition requires two layers of poly. There are processes out there with double poly layers (particularly good for floating-gate devices, and yes, they do make good linear capacitors). GF180MCU is not one of them.
Tim 'mithro' Ansell 04/02/2026 03:10
I think I thought Poly-Insulator-Poly was side-by-side?
Avatar
Avatar
Jason Yang
Is anyone currently, or was able to utilize litedram for their project involving off-chip DRAMs? I'm currently working with it for a project I'm taping out here. So far I got some results, but it doesn't seem to be designed for working with ASICs. Neither does litex in general.
Tim 'mithro' Ansell 04/02/2026 03:11
LiteX & LiteDRAM was/is definitely designed primarily for FPGAs (edited)
Avatar
Tim Edwards 04/02/2026 13:25
@Tim 'mithro' Ansell : No, you don't do poly side-by-side. Poly is very thin and has practically no sidewall. It's also sitting right on top of the substrate, so you'd end up with parasitic capacitance dominating. Double poly caps are quite nice, although MiM caps still have the advantage that you can still put transistors and other components underneath them.
Avatar
Tim 'mithro' Ansell 04/02/2026 13:30
Will fix that tomorrow, poke me if I forget
Avatar
Tholin 04/02/2026 15:07
I don’t think I’m gonna do much for this next shuttle. I want to tape out a RISC-V core with my custom SCL for sure, but only since I already have proven RTL for that. Probably a good idea to not expect another completely crammed die from me, I’m afraid. I will, however, do some long-needed maintenance on my SCL and get some more silicon art in the pipeline.
15:08
I do have ideas for custom silicon projects, but they are so big at this point, 90 days is not enough time to finish even one of them, I believe.
Avatar
Tim 'mithro' Ansell 04/03/2026 00:30
The video from my talk at Hackware here in Singapore is up on YouTube @ https://www.youtube.com/watch?v=t6Z0_Krhshc
Engineers.SG
wafer.space: Silicon now $4 USD, get inspired from Run #1! - Hackwa...
👍 5
Avatar
m_w 04/03/2026 20:20
Is there a guide for the minimum system requirements for generating gds?
20:22
At the scale of complexity of a high utilization full chip
20:23
I remember that @tnt had to have a fairly high end machine when he was working on pyfive
20:24
Raw per core horsepower and lots of ram
20:30
If I were to buy a build machine to make a chip, what kind of machine would I want?
20:33
Also do we have similar hardware specs for an emulator of a similar design complexity?
Avatar
Avatar
m_w
If I were to buy a build machine to make a chip, what kind of machine would I want?
BreakingTaps 04/03/2026 21:21
highest single-threaded performance possible (unfortunately). A lot of the steps are multithreaded and will take advantage of having a lot of cores, a few steps can be reasonably memory-heavy (30-60gb for a bigger design), but the bottleneck is usually DRC which has a lot of single-threaded sections. So the best single core performance you can get is most useful. I rented a "gaming server" from OVH with a Ryzen 9950x3d. My avg build time was 2-3hrs Tim put together a cloud comparison here (was a few months ago so possibly a bit out of date): https://claude.ai/public/artifacts/44717da0-d032-4bb2-9763-87dcfbb66a8a
Best Dedicated Servers for EDA Workloads 2024 - DRC Performance Guide
Compare 25+ dedicated servers optimized for single-threaded EDA workloads like KLayout/Magic DRC. Find the best price/performance under $100/month.
Thumbnail
21:23
on the upside, since most builds are bottlenecked on single core sections, you can kick off many parallel builds that each have slightly different setting tweaks when optimizing.
21:23
(or use a cheaper machine for non-DRC part of the pipeline)
Avatar
Avatar
Tim Edwards
@Tim 'mithro' Ansell : No, you don't do poly side-by-side. Poly is very thin and has practically no sidewall. It's also sitting right on top of the substrate, so you'd end up with parasitic capacitance dominating. Double poly caps are quite nice, although MiM caps still have the advantage that you can still put transistors and other components underneath them.
Tim 'mithro' Ansell 04/04/2026 00:56
I believe the website should be fixed now?
👍 1
Avatar
Tholin 04/04/2026 01:18
My multi-project die contains both a RISC-V core and analog (DACs)
01:18
Small correction
Avatar
Tim 'mithro' Ansell 04/04/2026 03:00
I also E-Test data provided by GF can be found @ https://docs.google.com/spreadsheets/d/10zQF_L-KsV-n5zMISB8C67llsldodtbSALWoNdpY17Y/edit?gid=1771808804#gid=1771808804 -- anyone see anything interesting?
wafer.space - WSRUN-1 - FAB3_ETEST_3SHE07245.1
Thumbnail
Avatar
Avatar
m_w
Is there a guide for the minimum system requirements for generating gds?
nmz787 04/04/2026 04:44
The template completed in 4 hours on my intel Lenovo t16 with 40GB RAM
04:44
Actually just generating GDS should be trivial on any system of the last 2 decades
Avatar
Avatar
Tim 'mithro' Ansell
I also E-Test data provided by GF can be found @ https://docs.google.com/spreadsheets/d/10zQF_L-KsV-n5zMISB8C67llsldodtbSALWoNdpY17Y/edit?gid=1771808804#gid=1771808804 -- anyone see anything interesting?
nmz787 04/04/2026 04:45
And you said at this price point there's no testing!
04:47
Having a lookup table for the test names to description would be helpful to make sense of things aside from guessing and looking at standard deviations of the values for a given unit of measure
Avatar
Avatar
nmz787
Actually just generating GDS should be trivial on any system of the last 2 decades
m_w 04/04/2026 05:12
yeah I guess the big thing is being able to run DRC in a reasonable amount of time without running out of RAM (edited)
Avatar
m_w 04/04/2026 05:26
so it is looks like I am looking at around ~$3K if I bought something off the shelf; ram being a big part of the cost
Avatar
m_w 04/04/2026 05:40
my laptop is probably not going to cut it, only has 16GB of RAM
Avatar
tnt 04/04/2026 06:13
There are data for 25 wafers, I though you had only run half a lot.
06:18
Very nice to get the ETest data though. Doing a few spot check vs the PDK values, it's pretty close to typical.
Avatar
tnt 04/04/2026 06:55
@Tim 'mithro' Ansell One thing that bugs me though is the name of the test "TM5L9K" ... I though we were using the 11K top metal thickness option. ( I rechecked https://discord.com/channels/1361349522684510449/1423053988210675852/1423076158219489300 )
06:59
Something else a bit weird is the MiM cap data. SPEC is between 1.7 fF/um^2 and 2.3 fF/um^2 but the pdk lists nominal at 1.5 fF/um^2. ( Although I guess they might be compensating for some measurement setup thing ... ) (edited)
Avatar
Avatar
m_w
yeah I guess the big thing is being able to run DRC in a reasonable amount of time without running out of RAM (edited)
nmz787 04/04/2026 08:15
There's always disk swapping :/
08:17
I'd suggest trying to run the template through to completion, to benchmark. $3k sounds a bit crazy if you're doing this for the first time and haven't done any benchmarking first
08:17
Even renting a cloud host for a few hours or days will be massively cheaper
Avatar
Avatar
nmz787
I'd suggest trying to run the template through to completion, to benchmark. $3k sounds a bit crazy if you're doing this for the first time and haven't done any benchmarking first
m_w 04/04/2026 16:06
Well this isn't exactly the first time I tried the tools.
16:07
I have run it on my laptop and it was fine for smaller benchmarks.
16:13
I was part of the pyfive team and was building most of the work that tnt did. By the end I had a borrowed machine with more ram.
Avatar
nmz787 04/04/2026 16:14
Ah
Avatar
m_w 04/04/2026 16:15
It was my project idea but tnt did all of the work.
16:16
Any funding that was raised all went to him.
Avatar
BreakingTaps 04/04/2026 16:19
i'd ++ the cloud rental route. The OVH server I rented was $200/month. I really only needed it for one month of intensive builds, two at the most. Unless you need/want the machine for other stuff it's hard to beat a cloud rental for short term usage
Avatar
tnt 04/04/2026 16:54
I think RAM is the main thing. For a full chip 64G is definitely needed I think.
16:54
I'm still using an older AM4 cpu with DDR4.
Avatar
m_w 04/04/2026 18:16
I was looking at 96GB
Avatar
tnt 04/04/2026 18:17
Should be fine. I was running DRC on 64G for the whole TT chip.
Avatar
m_w 04/04/2026 18:18
Looking at this like I am starting a company and want to see what it would cost to have basic infrastructure.
18:19
What do you guys use to run the checks for the shuttles?
Avatar
tnt 04/04/2026 18:21
github actions 😅
Avatar
urish 04/04/2026 18:25
We did hit the memory limits there a few times, but eventually we engineer our ways around it
Avatar
Tholin 04/05/2026 14:24
I got by with as little as 16GiB RAM on my laptop for my multi-project die, including running the prechecks locally. Memory usage really improved a ton during the last few days before tapeout deadline. (edited)
14:25
It just takes forever on a laptop
14:26
Would recommend having one PC with a CPU that scores high single-core perf to run the prechecks.
14:32
Also, re. 22:55 in the presentation: 480 LUTs doesn’t sound like a lot for an FPGA, but that is actually twice the amount of the 240 LUT MAX II CPLDs I have a big pile of because they keep coming in handy in projects (and I fit a whole DDR2 controller in one of those once!). And they would be even more useful to me if they were 5V tolerant. So, actually, I’d REALLY love to get my hands on a bunch of the Fabulous FPGA for whatever 5V systems I still build sometimes.
💯 2
Avatar
dshadoff 04/05/2026 16:13
The value of 5V compatibility shouldn't be underestimated
Avatar
Avatar
Tholin
Would recommend having one PC with a CPU that scores high single-core perf to run the prechecks.
m_w 04/05/2026 22:38
Yeah apparently now is a bad time to buy a new PC.
Avatar
m_w 04/05/2026 22:52
One thing to consider would be a libre silicon compute infrastructure. Timeshared remote systems for a structured development environments and infrastructure for the drc/lvs grind on the way the shuttles.
22:56
Guessing that there is no money for such a thing but it would be nice.
Avatar
Avatar
m_w
It was my project idea but tnt did all of the work.
Tim 'mithro' Ansell 04/06/2026 08:15
You can also run the DRC checks through https://platform.wafer.space
Welcome to wafer.space …
Platform for wafer.space low cost silicon manufacturing.
👍 1
Avatar
Avatar
Tholin
Also, re. 22:55 in the presentation: 480 LUTs doesn’t sound like a lot for an FPGA, but that is actually twice the amount of the 240 LUT MAX II CPLDs I have a big pile of because they keep coming in handy in projects (and I fit a whole DDR2 controller in one of those once!). And they would be even more useful to me if they were 5V tolerant. So, actually, I’d REALLY love to get my hands on a bunch of the Fabulous FPGA for whatever 5V systems I still build sometimes.
Tim 'mithro' Ansell 04/06/2026 08:20
Looks like @Leo Moser (mole99) has some competition -> https://github.com/MidstallSoftware/aegis and https://news.ycombinator.com/item?id=47646472
GitHub - MidstallSoftware/aegis: Open source FPGA silicon
Open source FPGA silicon. Contribute to MidstallSoftware/aegis development by creating an account on GitHub.
Thumbnail
rosscomputerguy
Aegis – open-source FPGA silicon
Footer icon Hacker News • 04/05/2026 05:50
08:21
They are claiming 2880 LUT4's
Avatar
Avatar
m_w
One thing to consider would be a libre silicon compute infrastructure. Timeshared remote systems for a structured development environments and infrastructure for the drc/lvs grind on the way the shuttles.
Tim 'mithro' Ansell 04/06/2026 09:34
If compute infrastructure is what is blocking you, I'm sure we can find someone who is willing to lend you time on some hardware.
Avatar
Avatar
Tim 'mithro' Ansell
Looks like @Leo Moser (mole99) has some competition -> https://github.com/MidstallSoftware/aegis and https://news.ycombinator.com/item?id=47646472
The Computer Guy 04/06/2026 14:15
Hi Tim
Avatar
Avatar
The Computer Guy
Hi Tim
Tim 'mithro' Ansell 04/06/2026 14:16
Hi!
Avatar
The Computer Guy 04/06/2026 14:16
Great to see you share the project
Avatar
Tim 'mithro' Ansell 04/06/2026 14:18
Are you planning on taping out on run #2?
Avatar
The Computer Guy 04/06/2026 14:19
Idk yet but I do want to do tapeout
14:19
I'm currently doing some improvements to the tapeout workflow. I got it down from over 6 hours to just 3.
Avatar
Leo Moser (mole99) 04/06/2026 14:24
Hi @The Computer Guy, impressive project! Especially hitting 2,880 LUT4's on GF180MCU using the default standard cell library. I've tried increasing the LUT count in my FPGA, but it would require simplifying the switch matrix of the tiles, which would impact the complexity of the designs that could be implemented. I'm wondering if you have tried implementing some real-world designs that make use of most of the 2,880 LUTs?
Avatar
Avatar
Leo Moser (mole99)
Hi @The Computer Guy, impressive project! Especially hitting 2,880 LUT4's on GF180MCU using the default standard cell library. I've tried increasing the LUT count in my FPGA, but it would require simplifying the switch matrix of the tiles, which would impact the complexity of the designs that could be implemented. I'm wondering if you have tried implementing some real-world designs that make use of most of the 2,880 LUTs?
The Computer Guy 04/06/2026 14:25
Hey so I do plan on trying a RISC-V core on it at some point. Or it would be Fourth.
Avatar
Avatar
The Computer Guy
Hey so I do plan on trying a RISC-V core on it at some point. Or it would be Fourth.
Leo Moser (mole99) 04/06/2026 14:27
That would make a great benchmark. Besides the blinky in your repository, have you tried implementing any other designs yet?
Avatar
The Computer Guy 04/06/2026 14:28
Not yet, it's mainly blinky and the test suite
Avatar
Tim 'mithro' Ansell 04/06/2026 14:53
@The Computer Guy / @Leo Moser (mole99) - Have you considered putting a serv core in spare space around SRAM tiles? 😛
Avatar
The Computer Guy 04/06/2026 14:54
No lol
Avatar
Leo Moser (mole99) 04/06/2026 14:54
I did so in a previous chip, not exactly SERV though: https://github.com/mole99/greyhound-ihp
Avatar
Tim 'mithro' Ansell 04/06/2026 15:04
@Leo Moser (mole99) / @The Computer Guy - You should also get a corescore.store for your parts 🙂
Avatar
Avatar
Tim 'mithro' Ansell
@Leo Moser (mole99) / @The Computer Guy - You should also get a corescore.store for your parts 🙂
Leo Moser (mole99) 04/06/2026 15:10
True! Greyhound has a core score of at least 1 😀
Avatar
Avatar
Tim 'mithro' Ansell
@Leo Moser (mole99) / @The Computer Guy - You should also get a corescore.store for your parts 🙂
The Computer Guy 04/06/2026 15:21
Lol, how would I do that?
Avatar
Avatar
The Computer Guy
Lol, how would I do that?
Tim 'mithro' Ansell 04/06/2026 15:21
https://github.com/olofk/corescore?tab=readme-ov-file#quick-start
GitHub - olofk/corescore: CoreScore
CoreScore. Contribute to olofk/corescore development by creating an account on GitHub.
Thumbnail
Avatar
The Computer Guy 04/06/2026 15:22
Ah
Avatar
Leo Moser (mole99) 04/06/2026 15:22
However, I think you need silicon first.
Avatar
The Computer Guy 04/06/2026 15:23
I'm not too worried about Aegis Terra 1's performance since it's meant to be a starting point lol
Avatar
Avatar
Leo Moser (mole99)
However, I think you need silicon first.
The Computer Guy 04/06/2026 15:23
It kinda seems like it, I don't think it would be too happy with the simulator.
Avatar
Avatar
Tim 'mithro' Ansell
If compute infrastructure is what is blocking you, I'm sure we can find someone who is willing to lend you time on some hardware.
m_w 04/06/2026 16:46
Right now I am in the scoping process preparing a machine to do development. Since the drc can be offloaded I might be able to use an old decommissioned gaming pc for dev.
Avatar
The Computer Guy 04/06/2026 21:59
OpenROAD is using 330GB of RAM out of my 512GB lol (edited)
Avatar
Lofty 04/06/2026 23:04
@The Computer Guy hi, I'm lofty, one of the yosys/nextpnr devs. I did have some thoughts on the FPGA architecture side of things.
Avatar
The Computer Guy 04/06/2026 23:04
Oh cool
23:05
I've definitely had thoughts about yosys and nextpnr being more optimized for systems like Ampere. I daily drive Arm hardware so it would be nice if yosys and nextpnr could take advantage of my 128 cores. I wish OpenROAD could as well heh.
Avatar
Lofty 04/06/2026 23:06
multithreading is something we're working on to one extent or another; neither codebase is ideal for such things (Yosys's RTLIL core representation is not thread-safe, and nextpnr achieves local threading by layering over the arch API)
Avatar
The Computer Guy 04/06/2026 23:07
Yeah, I've seen some of the issues and code. I know in general this is hard to get multithreaded.
Avatar
Lofty 04/06/2026 23:07
I will ask: are you using router1 or router2?
Avatar
The Computer Guy 04/06/2026 23:08
I've been using viaduct with nextpnr
23:08
https://github.com/MidstallSoftware/aegis/tree/master/nextpnr-aegis
Avatar
Lofty 04/06/2026 23:08
yes. I saw.
23:09
after all, I was the one who proposed viaduct :p
Avatar
The Computer Guy 04/06/2026 23:09
Ah
Avatar
Lofty 04/06/2026 23:09
when nextpnr-aegis runs, does it use router1 or router2
Avatar
The Computer Guy 04/06/2026 23:10
Lemme run it and see
23:10
It would be cool for the Aegis backend to be upstreamed into nextpnr so I don't have to do the overlay
Avatar
Lofty 04/06/2026 23:11
we are relatively flexible with accepting such architectures, but you would likely need to port your code to himbaechel instead of viaduct
Avatar
The Computer Guy 04/06/2026 23:11
Ah
23:12
I think I remember seeing both and wasn't sure which to use
Avatar
Lofty 04/06/2026 23:12
use himbaechel.
Avatar
The Computer Guy 04/06/2026 23:13
Ok, after the tapeout improvements I'll do that
Avatar
Lofty 04/06/2026 23:14
(since the joke is likely lost: viaduct is called such because it a bridge API for small arch(itectur)es. himbaechel is a bridge API based on viaduct for large architectures)
Avatar
The Computer Guy 04/06/2026 23:14
Gotcha
23:15
Himbaechel is a better fit for Aegis?
23:15
I don't see anything from nextpnr which indicates if its router1 or router2
Avatar
Avatar
The Computer Guy
Himbaechel is a better fit for Aegis?
Lofty 04/06/2026 23:16
Viaduct won't see any future improvements that Himbaechel receives from our own work on it
Avatar
The Computer Guy 04/06/2026 23:16
Ah, that makes sense
Avatar
Lofty 04/06/2026 23:17
for the scale of your FPGA, Viaduct is fine, but I think you'll appreciate having to build the architecture database once at build time rather than on every run
Avatar
The Computer Guy 04/06/2026 23:17
Ah
23:18
Ig that's a good time to also make things a bit more streamlined. I made it where the parameters for the design is just passed in. When switching to Himbaechel, I could use the descriptor JSON for the chip.
Avatar
Avatar
The Computer Guy
I don't see anything from nextpnr which indicates if its router1 or router2
Lofty 04/06/2026 23:19
there are messages such as this one
Avatar
The Computer Guy 04/06/2026 23:19
Ok, yeah I see that
Avatar
Lofty 04/06/2026 23:19
also if the router output has |s, it's router1, if it has =s, it's router2
Avatar
The Computer Guy 04/06/2026 23:19
Ah, so it is router1
23:20
What's the difference between router1 and router2?
Avatar
Lofty 04/06/2026 23:20
try running again with --router router2
Avatar
Avatar
The Computer Guy
What's the difference between router1 and router2?
Lofty 04/06/2026 23:20
r1, when properly tuned, produces higher Fmax results. r2 produces worse Fmax results, but requires very little tuning and runs much faster.
Avatar
The Computer Guy 04/06/2026 23:21
Ah
Avatar
Lofty 04/06/2026 23:21
also r2 is multithreaded-ish and r1 is not.
Avatar
The Computer Guy 04/06/2026 23:23
Gotcha, with r1 it did say it ran for 0.11s for the blinky example
23:24
Oh, r2 did it in 0.02s
Avatar
Lofty 04/06/2026 23:25
https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/018-attosoc see if you can get this one to synth. that should begin to differentiate the two.
Avatar
The Computer Guy 04/06/2026 23:25
Ah
Avatar
Lofty 04/06/2026 23:30
also, on a personal note:
Existing open-source FPGA efforts either reverse-engineer proprietary architectures (Project IceStorm, Apicula) or build tooling around closed silicon (Yosys, nextpnr)
I think it's perhaps worth pointing out Cologne Chip GateMate as a half-proprietary architecture. it's true the HDL is closed, but we're their official toolchain, and we can publish information from their confidential docs as long as it's not verbatim.
23:30
e.g. this
Avatar
The Computer Guy 04/06/2026 23:30
Oh cool
23:33
If I can get the nextpnr support upstreamed, it would be cool to do that with yosys as well. A synth_aegis command would be cool, it would only really need the JSON descriptor I think.
Avatar
Lofty 04/06/2026 23:34
you would be expected to provide tests and maintain it to some degree though
Avatar
The Computer Guy 04/06/2026 23:34
Oh
23:34
Fair
Avatar
Lofty 04/06/2026 23:35
nextpnr's standards for architectures are a bit lower than yosys'.
Avatar
The Computer Guy 04/06/2026 23:36
I was thinking both would have high standards
Avatar
Avatar
The Computer Guy
I've definitely had thoughts about yosys and nextpnr being more optimized for systems like Ampere. I daily drive Arm hardware so it would be nice if yosys and nextpnr could take advantage of my 128 cores. I wish OpenROAD could as well heh.
Tim 'mithro' Ansell 04/07/2026 01:52
I think everyone, including the OpenROAD devs would love to figure out how to take advantage of many-core systems. Almost all the existing research and effort has been focused on trying to produce the best solutions when measured by number of cpu cycles / instructions (mainly due to the perverse incentives when you license your software per CPU core) rather than solutions which might consume overall more CPU in the end but have a shorter wall run time. Most software people at Google were very interested in trying to figure out how we could do something more map-reduce style which allowed the expensive steps complete in minutes but we where never quite able to get the resources needed to do that effort when still being behind on other functionality.
01:53
@The Computer Guy - BTW I would love to know more about your SERDES. Have you seen my talk @ https://bit.ly/open-pipe-talk at all?
[External Access] SERDES, PIPE and protocols - Pathway to fully ope...
SERDES, PIPE and protocols Pathway to fully open source implementations... Presenters Tim ‘mithro’ Ansell <tansell@google.com> bit.ly/open-pipe-talk
Thumbnail
Avatar
The Computer Guy 04/07/2026 01:56
I haven't seen your talk on serdes lol
02:01
Alright lol
Avatar
Tim 'mithro' Ansell 04/07/2026 02:01
@The Computer Guy - If you are procrastinating, I have plenty of reading material (much which is out of date) at https://bit.ly/tim-silicon-2024 I have a very old presentation at http://bit.ly/goog-fpga-22q3 which has a bunch of your "competition".
Tim's Silicon Presentations - bit.ly/tim-silicon-2024
Tim's Silicon Presentations bit.ly/tim-silicon-2024
Open source (embedded) FPGA generators state - 2022Q3
Open source (e)FPGA generators Why they are included by default in Google’s programs? Presenter Tim ‘mithro’ Ansell <tansell@google.com>
Thumbnail
02:02
There was someone else on this server that was working on SERDES type things too....
02:04
02:04
@The Computer Guy - This seems to be that discussion. (poke @EmbeddedKen). (edited)
Avatar
The Computer Guy 04/07/2026 02:04
Huh
Avatar
Avatar
Lofty
also, on a personal note:
Existing open-source FPGA efforts either reverse-engineer proprietary architectures (Project IceStorm, Apicula) or build tooling around closed silicon (Yosys, nextpnr)
I think it's perhaps worth pointing out Cologne Chip GateMate as a half-proprietary architecture. it's true the HDL is closed, but we're their official toolchain, and we can publish information from their confidential docs as long as it's not verbatim.
The Computer Guy 04/07/2026 03:39
https://github.com/MidstallSoftware/aegis/pull/8
chore(readme): clarify other projects by RossComputerGuy · Pull Re...
Thumbnail
Avatar
Avatar
The Computer Guy
https://github.com/MidstallSoftware/aegis/pull/8
Lofty 04/07/2026 03:41
Yeah this seems much fairer
Avatar
The Computer Guy 04/07/2026 03:42
Great
03:43
Gonna work on an architecture documentation while I wait for the tapeout workflow to finish
Avatar
BreakingTaps 04/07/2026 03:45
speaking of multi-threading, last weekend I realized that there are some threading knobs left at 1 when running librelane/project template. most notably the resizing steps. gave me a 2-3x speedup going from 1 to 16 cores (presumably a lot of synchronization losses keeping it from linear) I also started to play around with implementing nvidia's INSTA idea (https://ieeexplore.ieee.org/document/11132858) and it was 2-5x faster although the QoR wasn't always comparable. Worked well to get to TNS = 0, but didn't really like pushing positive slack margins for some reason, probably just my bad code
Avatar
The Computer Guy 04/07/2026 03:47
Oh cool, you're here lol. I remember seeing you followed me on Twitter a bit ago which was funny because that was after I saw one of your videos.
😁 1
Avatar
BreakingTaps 04/07/2026 03:48
hi hi! yes I was excited to see you pop into my twitter feed, folks working on silicon and fpgas are rare 🙂 try to follow whenever a good project pops up!
Avatar
The Computer Guy 04/07/2026 03:49
Awesome, yeah I've got some even cooler projects in the pipeline after Aegis
🥳 1
03:52
Ik I'm one of the few people doing this stuff on NixOS, I'm even doing it all on Arm lol
Leo Moser (mole99) started a thread. 04/07/2026 07:09
Avatar
The Computer Guy 04/07/2026 21:29
Woah https://x.com/i/status/2041619342647754787
adafruit industries (@adafruit)
Aegis: a fully open-source FPGA, from the silicon up https://t.co/8MiDBkSsy3
Image
Footer icon X • 04/07/2026 20:49
Avatar
The Computer Guy 04/08/2026 02:08
Is there a way to make OpenROAD not take 6 hours for detailed routing & placement?
Avatar
htamas 04/08/2026 02:23
  • Make your design less congested
    • Decrease the density (allow more area for the same amount of logic)
    • Decrease your target clock frequency (increase the clock period)
    (even if you will eventually push for area or clock speed, you can relax them while you are iterating on your design to make the hardening faster)
  • Make sure you have enough RAM, otherwise you may end up using swap / virtual memory which is substantially slower
Avatar
The Computer Guy 04/08/2026 02:24
I have 512GB of RAM
👍 1
02:24
Turns out apparently you can tell OpenROAD to use multiple threads, it's only been using 1 of my 128 cores
😮 1
Avatar
htamas 04/08/2026 02:25
  • Make your design modular, harden smaller parts and use them as macros at the top level
Avatar
The Computer Guy 04/08/2026 02:25
I do a macro based tapeout
👍 1
02:26
I don't think I can decrease things without decreasing the tiles I have. Which I kinda need those because they define the capability of the FPGA.
Avatar
Avatar
The Computer Guy
Turns out apparently you can tell OpenROAD to use multiple threads, it's only been using 1 of my 128 cores
htamas 04/08/2026 02:29
Are you calling OpenROAD directly? If you use librelane, detailed routing should already run with DRT_THREADS set to the number of machine threads, and many other parts of the flow are single-threaded.
Avatar
The Computer Guy 04/08/2026 02:30
I'm calling it directly
👍 1
02:31
I'll try -threads $NIX_BUILD_CORES
02:36
Huh, all of my small tiles went from 2 minutes to 20 seconds
👍 1
02:37
The SerDes and "tile" tiles still take a good chunk of time
Avatar
Tholin 04/08/2026 12:39
I know it gets mentioned a lot during talks, but what actually is the story behind PCB manufacturing becoming accessible? When I first got deep enough into EE to want to make my own PCBs, JLCPCB was already a thing, so I missed the beginning part of all that.
12:40
I keep hearing there is parallels between that story and the direction open source silicon is going in, but I have no context to get it. (edited)
Avatar
Tim 'mithro' Ansell 04/08/2026 12:44
@Tholin - I don't know if there is any official history.
12:45
@Tholin - The first ever PCB that I ever got made commercially was in University and the PCB house only allowed me to submit a design because they did other work for the university. They definately had a "Call us for a sales call and set up an account" type setup.
12:46
@Tholin - The big change was then OHS Park which was then followed by Dirty PCB. They where services which would pool together designs and then them to the PCB house and such.
12:47
At that point I could get PCBs made for the same cost of shipping to Australia, the turn around time was like maybe 6 weeks however as they designs only went to the PCB house like every couple of weeks and shipping to Australia was aweful 🙂
12:48
Dirty PCB was cheaper because you didn't get things like solder mask or silk screen or anything, OHS PCB was better but more expensive. Neither group would hold your hand or help you fix DRCs or stuff. They manufactured what you sent them and if it wasn't correct it was your own fault.
12:48
Then a bunch of the Chinese PCB houses like JLC, Seeed and PCB Way started offering services to the rest of the world.
12:49
And that is my short story of my own experiences, don't know what is was like for others.
Avatar
Tholin 04/08/2026 12:51
Huh
Avatar
Tim 'mithro' Ansell 04/08/2026 12:53
The big thing that OHS Park and Dirty PCB did was they accepted design file upload and a credit card via the web.
Avatar
Avatar
Tholin
I keep hearing there is parallels between that story and the direction open source silicon is going in, but I have no context to get it. (edited)
htamas 04/08/2026 13:26
You might be interested in this video with Tim: https://www.siliconimist.com/p/waferspace-tim-mithro-ansell
wafer.space - Tim 'mithro' Ansell
Open Silicon Access From an Innovative Business Model
Thumbnail
❤️ 3
Avatar
dshadoff 04/08/2026 15:30
It's likely (at least mildly) related to new features added to the manufacturers' software which allowed them to panelize disparate designs more easily.
Avatar
tnt 04/08/2026 15:41
I still have emails from 2011 when it wasn't osh park yet and you were just emailing "pcb-order@laen.org" to get added to a panel and you were manually sending paying through paypal transfer ...
💯 1
👍 1
Avatar
The Computer Guy 04/08/2026 19:07
Dang, Aegis Terra 1 is way too big from the sound of it for wafer.space. I did plan on eventually starting another family of FPGA's. Good time to do Aegis Luna 1. The Luna series is meant to be small scale while Terra is meant to be the leading series. If I do 19 x 19, 2 tracks, 2 DSP column iteration, 1 BRAM column iteration, and 1 SerDes then I fill up the die by like 80% - 90%.
😮 1
Avatar
Avatar
The Computer Guy
Turns out apparently you can tell OpenROAD to use multiple threads, it's only been using 1 of my 128 cores
asic destroyer 04/08/2026 21:48
What kind of machine do you have? I’m a little bit jealous.
Avatar
Avatar
asic destroyer
What kind of machine do you have? I’m a little bit jealous.
The Computer Guy 04/08/2026 21:48
Ampere Altra M128-26 with 512GB of RAM
😮 1
Avatar
asic destroyer 04/08/2026 21:54
I bought an i9 14700K because Yosys and nextpnr care more about single core performance.
Avatar
The Computer Guy 04/08/2026 21:56
Huh, yosys and nextpnr are still pretty fast for me
21:58
I mainly went to Ampere because I switched from a power hungry gaming laptop to an M1 Pro running NixOS a few years back. The problem with the M1 is not enough RAM for compilation, I was using it to maintain LLVM in nixpkgs and the 16GB was just not enough. Also, you had to compile things like Mesa for NixOS Asahi. I was told about Ampere and switched my desktop over. It's very good when I have like 20k ninja or make jobs to run lol.
😮 1
Avatar
Leo Moser (mole99) 04/09/2026 06:08
@The Computer Guy Maybe you could move your posts to #digital or start a thread?
👍 1
Avatar
Tim 'mithro' Ansell 04/09/2026 09:04
Interesting interview with Julia Desmazes on the Amp Hour - https://theamphour.com/721-chip-design-for-fun-and-waffles-with-julia-desmazes/
#721 – Chip Design for Fun (and Waffles) with Julia Desmazes | Th...
Julia Desmazes joins Chris to discuss designing chips for fun and getting an entire design done in 2 weeks to make a tapeout deadline. Julia built accerlators and has continued to dive deeper into on and off chip tooling for greater visibility into the silicon she gets back from the fab.
👍 2
🚀 1
🎉 1
Avatar
Matt Venn 04/09/2026 09:24
@Essen ^^
😅 1
Avatar
Avatar
Matt Venn
@Essen ^^
Essen 04/09/2026 15:49
Now everyone knows of my love for waffle house! 🧇
Avatar
Avatar
Essen
Now everyone knows of my love for waffle house! 🧇
nmz787 04/09/2026 16:00
I see typo in what should be accelerators
16:01
Not sure where the discord summary comes from, must be some hidden element
🤣 1
Avatar
Avatar
nmz787
I see typo in what should be accelerators
Essen 04/09/2026 16:06
It's my trap to make other people think I am normal.
Avatar
Tim 'mithro' Ansell 04/10/2026 09:35
I want to get wafer.space branded Stroopwafel swag 😛
👀 1
🧇 2
Avatar
Tim 'mithro' Ansell 04/11/2026 03:19
Things are progressing here in Singapore!
Image attachment
👍 8
❤️ 4
🥳 6
waferspace 5
😍 1
🔥 1
Avatar
BreakingTaps 04/11/2026 17:35
exciting!
Avatar
Tholin 04/13/2026 22:41
Just yesterday, I gave a long presentation called "3½ years of open-source-silicon: a retrospective, and why you should care" to a general audience. It just goes over my personal views and experience with open source before I give a introduction on what it is that I actually do as a chip designer. The video still has to be edited and processed to be uploaded to the YouTube channel, but luckily for ya’ll, I got a hold of the raw recording for your viewing pleasure. Unfortunately, I had some slight microphone issues that were only pointed out to me until after I was done. Sorry for that. I also had to rush towards the end as a scheduling mishap left me low on time, so there will certainly be a part 2 to this at some point where I go into more depth, so look forward to that! https://www.dropbox.com/scl/fi/dqd3k0f2vvihynpw3gv26/Tholin-s-IC-Panel.mp4?rlkey=dhxsf5dm97i549e0z3kyvf20g&st=em4kqi1n&dl=0
Tholin's IC Panel.mp4
Shared with Dropbox
Thumbnail
22:41
Let me know if there are any facts I got wrong, I can get corrections inserted into the youtube upload.
Avatar
Tim 'mithro' Ansell 04/14/2026 02:15
@Tholin - Cool!
Avatar
Tim 'mithro' Ansell 04/14/2026 02:26
People might find @bunnie talking about his Baochip with Hackster.io at https://www.youtube.com/watch?v=dBod87GMk6Y interesting.
Hackster.io, an Avnet community
Building Secure Hardware with Dabao, by bunnie // Hackster Café
💚 2
Avatar
The Computer Guy 04/14/2026 02:26
I've got something which should fit on wafer.space. I'm running verification on it.
Image attachment
💯 1
💜 1
Avatar
Avatar
Tim 'mithro' Ansell
People might find @bunnie talking about his Baochip with Hackster.io at https://www.youtube.com/watch?v=dBod87GMk6Y interesting.
The Computer Guy 04/14/2026 02:27
Good timing, I was needing something new to watch while I start dinner lol
Avatar
Avatar
The Computer Guy
I've got something which should fit on wafer.space. I'm running verification on it.
Leo Moser (mole99) 04/14/2026 06:12
40x17=680 LUTs?
Avatar
Avatar
Leo Moser (mole99)
40x17=680 LUTs?
The Computer Guy 04/14/2026 06:13
40 x 19
06:13
It's 760 LUTs
Avatar
Leo Moser (mole99) 04/14/2026 06:14
I thought the previous chip you shared with 2,880 LUTs was targeting wafer.space?
Avatar
Avatar
Leo Moser (mole99)
I thought the previous chip you shared with 2,880 LUTs was targeting wafer.space?
The Computer Guy 04/14/2026 06:16
I couldn't get Terra 1 to fit
06:16
So Luna 1 was made
Avatar
Leo Moser (mole99) 04/14/2026 06:21
Then I misunderstood. I thought you had already fitted your previous design into the wafers.space template.
Avatar
The Computer Guy 04/14/2026 06:22
No because I didn't know of that until I was working on improving the tapeout
Avatar
futaris [AU] 04/14/2026 22:18
Great interview @Essen . I did some work on Cirrus Logic MaverickCrunch gcc compilers about 20 years ago. I think their HQ is/was in Austin, TX. Listened to the pod cast whilst driving and doing other errands. Your bfloat16 implementation and blog posts are great for someone who has a deep understanding of the software and not so much of the hardware implementation of floating point. (edited)
22:20
https://youtu.be/L-QVgbdt_qg Is another gem on floating point, for anyone interested in how the Intel 8087 was designed.
Turing Awardee Clips
Kahan on the 8087 and designing Intel's floating point
Avatar
namibj 04/14/2026 23:57
[Run] Evaluating: WP_C=0.81, WP_D=0.88, WN_MAIN=1.81, WN_CC=0.42, WN_TAIL=5.51, LP_C=0.20, LP_D=0.42, LN_MAIN=0.15, LN_CC=0.15, LN_TAIL=0.15, V3=0.00 --> Success: Freq = 4.982 GHz, V_pp = 2.141 V
sky130; no reactive elements; xschem (no layout parasitics accounted for yet); not really tuned yet though. Search algo is ongoing at the task of figuring out the relevant area of physically possible parameter space (like, from manufacturable transistor sizes down to those that result in oscillations).
Avatar
Tim 'mithro' Ansell 04/15/2026 06:13
Hi everyone, could people bug me about getting announcements out about Run 1 and Run 2? I've been really slack and keep getting distracted.
Avatar
Leo Moser (mole99) 04/15/2026 12:04
For all you FPGA enthusiasts here, I've brought up the FPGA of Greyhound: https://www.linkedin.com/posts/leo-moser_fpga-asic-opensource-activity-7450118975205593088-17B8 I'm looking forward to testing my FPGA on wafer.space run #1! 👏
#fpga #asic #opensource | Leo Moser
Greyhound is alive! 🐶 Finally, I had everything I needed to do the bring-up of the chip. I was a bit surprised when it just... worked! Greyhound is an open-source RISC-V SoC with tightly coupled eFPGA. The chip was designed using LibreLane (https://librelane.org/) and FABulous (https://lnkd.in/gkhEg66j), and the FPGA toolchain uses Yosys an...
Thumbnail
🎉 6
Avatar
dshadoff 04/15/2026 13:29
Will anybody be going to (or presenting at ?) the Latch-Up conference in Waterloo Ontario (Canada) in a couple of weeks ? (edited)
Avatar
Avatar
dshadoff
Will anybody be going to (or presenting at ?) the Latch-Up conference in Waterloo Ontario (Canada) in a couple of weeks ? (edited)
Tim 'mithro' Ansell 04/15/2026 14:44
I was hoping to make it but I don't think I will end up doing so
Avatar
The Computer Guy 04/15/2026 20:12
I didn't know about that conference until just now lol.
Avatar
Dory 04/16/2026 10:47
Hello! I was wondering if I could get a hand with setting up my workflow to design the chip for this process? Rn I managed to get most of the template set up, but on runnng my code Yosys is throwing 130 check errors at me, and I can't find what they actually are?
Avatar
Avatar
Dory
Hello! I was wondering if I could get a hand with setting up my workflow to design the chip for this process? Rn I managed to get most of the template set up, but on runnng my code Yosys is throwing 130 check errors at me, and I can't find what they actually are?
Lofty 04/16/2026 10:50
Did you look in the runs directory?
Avatar
Dory 04/16/2026 10:51
yep, but the log just says 130 Yosys check errors found
Avatar
Lofty 04/16/2026 10:52
The librelane log will say that, but in the runs directory will be the actual Yosys output
Avatar
Dory 04/16/2026 10:52
Not really, the step only contains a config.json and state_in.json
10:53
I am very new to LibreLane so I'm not quite the best at knowing where to find stuff tho xd
Avatar
Tholin 04/16/2026 12:26
So many PCBs for my bring-ups...
Image attachment
Avatar
Dory 04/16/2026 13:08
Fixed the issues I had with Yosys (I think) but now I get ERROR add_global_connections failed to make any connections for 'rst_n_pad/DVDD' to VDD. (edited)
Avatar
Dory 04/16/2026 13:30
For some reason it canot connect power to the rst pad huh...
13:30
Weird...
Leo Moser (mole99) started a thread. 04/16/2026 13:47
Avatar
Dory 04/16/2026 14:49
Some feedback: On the template on the github it would be neat if setting any pad count to 0 would disable the generation code for that pad type, which should be doable with an if block
Leo Moser (mole99) started a thread. 04/16/2026 15:07
Avatar
Avatar
Tim 'mithro' Ansell
Bunnie was suggesting exploring silicon capacitors -> https://docs.google.com/document/d/1ahoCTmPvKExYtk3qqxvjMpnq5XOcIQvVWMF84zgi82k/edit?tab=t.0#heading=h.90mbdw45v39k
Christopher 04/18/2026 11:11
Bit of a bump, is this something that could be played with on a TT or similar? If it's not a decent task for a motivated beginner then it's not for me, but it would be pretty cool to learn
Avatar
Avatar
Christopher
Bit of a bump, is this something that could be played with on a TT or similar? If it's not a decent task for a motivated beginner then it's not for me, but it would be pretty cool to learn
nmz787 04/18/2026 19:44
Isn't tt much much smaller usable area? Silicon capacitors are nothing new, the PDK parasitics models should include capacitance already. I'm not sure what the mention of "AI" in the google doc is about
Avatar
Avatar
nmz787
Isn't tt much much smaller usable area? Silicon capacitors are nothing new, the PDK parasitics models should include capacitance already. I'm not sure what the mention of "AI" in the google doc is about
Christopher 04/18/2026 19:48
there's probably some best-fit model that exists for a given capacitance, or if you can accept some other higher parasitics. The idea for trying it out on TT is to test out a few caps without going broke though heh.
Avatar
namibj 04/18/2026 22:56
deep trench
from the linked muRata datasheet. Sounds like it's based on DRAM storage capacitor manufacturing technology; we don't have that in gf180mcu.
XBSC_UBSC_BBSC_ULSC_DS.pdf
1.66 MB
Avatar
Avatar
Christopher
there's probably some best-fit model that exists for a given capacitance, or if you can accept some other higher parasitics. The idea for trying it out on TT is to test out a few caps without going broke though heh.
namibj 04/18/2026 22:57
TT doesn't have the structures that are used for these highly linear capacitors
Avatar
Avatar
namibj
TT doesn't have the structures that are used for these highly linear capacitors
Christopher 04/18/2026 22:58
High aspect ratio caps are something completely different
22:58
They dont use standard processes
Avatar
namibj 04/18/2026 22:58
(Also lacking the packaging but that's just a non-selected process option (WLCSP bumping) that could probably be taken for wafer.space based on a cost tradeoff if the process had access to the deep trench capacitor structures needed.)
Avatar
Avatar
Christopher
They dont use standard processes
namibj 04/18/2026 22:59
well, look at the linked muRata datasheet first page 1st prose paragraph
23:00
err, 1st body paragraph
Avatar
Avatar
namibj
well, look at the linked muRata datasheet first page 1st prose paragraph
Christopher 04/18/2026 23:00
I know what you're getting at, I don't know how that's at all relevant
Avatar
namibj 04/18/2026 23:00
hese deep trench silicon capacitors have been developed with a semiconductor MOS process. They provide very high reliability and capacitance stability over voltage (0.1%/V) and temperature (60 ppm/K).
Avatar
Christopher 04/18/2026 23:00
What does this have to do with testing capacitors on the gf process
Avatar
namibj 04/18/2026 23:02
The reason these silicon capacitors are worth something on the market of passive SMD parts is because their dielectric is afaik grown silicon dioxide on a surface area enhancing trench structure. That dielectric is awesome electrically. That structure patterning provides suffiiciently low parasitics to be worth the cost of semiconductor patterning for a mere SMD capacitor, considering the electrical awesomness of the SiO2
Avatar
Avatar
namibj
The reason these silicon capacitors are worth something on the market of passive SMD parts is because their dielectric is afaik grown silicon dioxide on a surface area enhancing trench structure. That dielectric is awesome electrically. That structure patterning provides suffiiciently low parasitics to be worth the cost of semiconductor patterning for a mere SMD capacitor, considering the electrical awesomness of the SiO2
Christopher 04/18/2026 23:03
Yes, and they use ALD & SoI to achieve their aspect ratios, but that doesn't mean you can't test MiM caps on gf180
Avatar
namibj 04/18/2026 23:04
ok buy a slot have some externally contacted quite shitty MIM caps?
23:04
wafer.space doesn't give you WLCSP.
23:05
Without that the packaging parasitics make these practically useless, also MIM caps are not really that good comparatively.
23:05
(Use non-litho manufacturing instead....)
23:06
The MIM are good... if you need on-die caps that don't eat active area and are pretty linear. Yeah.
Avatar
Christopher 04/18/2026 23:12
I'll hold off for someone else's opinion. Noted.
Avatar
Avatar
namibj
The reason these silicon capacitors are worth something on the market of passive SMD parts is because their dielectric is afaik grown silicon dioxide on a surface area enhancing trench structure. That dielectric is awesome electrically. That structure patterning provides suffiiciently low parasitics to be worth the cost of semiconductor patterning for a mere SMD capacitor, considering the electrical awesomness of the SiO2
Tim 'mithro' Ansell 04/19/2026 01:16
@bunnie was explaining the reason silicon caps are useful is because of how thin they can be.
Avatar
Avatar
Christopher
I'll hold off for someone else's opinion. Noted.
Tim 'mithro' Ansell 04/19/2026 01:17
The idea would be to build structures on all of the silicon layers, metal layers and mim layers which try to produce the highest possible capacitance.
👍 1
01:19
It's basically an optimization problem.
Avatar
Avatar
Tim 'mithro' Ansell
The idea would be to build structures on all of the silicon layers, metal layers and mim layers which try to produce the highest possible capacitance.
Christopher 04/19/2026 01:19
Yeah, I figured part of the challenge is finding a way to do the inverse problem solving
01:24
The other benefit I could see would be the ability to generate proven caps for other purposes
Avatar
Avatar
Christopher
The other benefit I could see would be the ability to generate proven caps for other purposes
Tim 'mithro' Ansell 04/19/2026 01:40
Correct
Avatar
Avatar
Christopher
Yeah, I figured part of the challenge is finding a way to do the inverse problem solving
Tim 'mithro' Ansell 04/19/2026 01:41
GDSFactory has a bunch of modes which have been used for silicon photonics optimization in a similar manner
Avatar
azonenberg 04/19/2026 03:17
yeah i remember reading recently about some of these advanced packages for chiplet interconnects
03:17
apparently they have trench caps in them for decoupling on the interposer
03:18
Also, finally (after waaaay too long) managed to install the PDK
03:18
and i have some of the library cells open in klayout and.... wow these look weird lol
03:19
the fine metal features and huge poly just seem so bizarre
03:19
i'm used to looking at poly that is like double patterned or something and is pushing litho limits and metal is enormous by comparison
03:22
so seeing signal lines on M1 that are like half the size of the poly is just confusing to me lol
03:27
buuut i need to not get nerdsniped too much on this until i get some chores done :p
😂 2
03:30
for reference if anybody is curious... this is a nand2 on UMC 180nm
Image attachment
03:31
the chip had 3.3V compatible IOs and a 1.8V core, this particular cell is from a closeup image that I don't have any context for so unsure if in the IO area or core
03:31
(i took the photo in 2014 and have no notes from it)
03:35
it had a lot of custom layout so this isnt part of a standard cell
Avatar
Christopher 04/19/2026 04:26
very bouba
Avatar
azonenberg 04/19/2026 04:43
no matter how kiki your layout is, after litho and etch it's gonna turn out bouba if it's a min-sized feature :p
Avatar
Brian Swetland 04/19/2026 04:48
straight lines and 90 degree angles are lies perpetuated by big geometry
😆 2
Avatar
Avatar
azonenberg
so seeing signal lines on M1 that are like half the size of the poly is just confusing to me lol
namibj 04/19/2026 20:51
huh.... I thought you said you're not gonna look until you get 1.8V oxide 😄
Avatar
Avatar
Brian Swetland
straight lines and 90 degree angles are lies perpetuated by big geometry
namibj 04/19/2026 20:52
embrace ring shaped ring oscillators
Avatar
Avatar
namibj
huh.... I thought you said you're not gonna look until you get 1.8V oxide 😄
Tim 'mithro' Ansell 04/20/2026 06:36
Shhhhhhh....
Avatar
Avatar
azonenberg
(i took the photo in 2014 and have no notes from it)
Tim 'mithro' Ansell 04/20/2026 06:36
I would love to get SEM imaging of various GF180MCU stuff. I think at some point I sent you some samples. I have a lot more potential samples now.
06:38
@azonenberg - I'm actually talking to Lattice about getting known good die of Lattice FPGAs to offer co-packaged/wire bonded GF180MCU parts with cheap open source supported FPGAs. That might be a gateway option for exploring PCIe type things further.
Avatar
azonenberg 04/20/2026 06:40
Interesting. But my goal here is not so much "I want to build an asic on gf180 with pcie" as it is pathfinding for future gen e.g. pcie gen3/4/5 on $FAB 90/65/45
06:40
my realistic "I think we can actually do this" near term goal is to build a pcie "gen 0.5" PHY on gf180mcu
06:40
something that is protocol compatible with gen1 but underclocked to 1/2 or 1/4 or 1/8 rate
06:41
and can talk to an fpga transceiver running in sub rate mode
06:41
but the idea being that the same circuit would hopefully lay the groundwork for a faster one on a more modern node
06:43
so while i'm sure there might be other projects that could benefit from such a copackaged design with fpga + asic, it doesn't fill my goal here where development of the phy/protocol IP itself is the point
Avatar
Avatar
Tim 'mithro' Ansell
I would love to get SEM imaging of various GF180MCU stuff. I think at some point I sent you some samples. I have a lot more potential samples now.
azonenberg 04/20/2026 06:44
I think i have some samples from you in my microscope food bin from skywater but i need to see what might be gf180. i've been too busy to get to them so far
06:44
I'd need work's signoff to image them in their lab, alternatively if my friends across town get any of their sems working i can use theirs with no issue
06:44
i can definitely image optically on my home setup on the labsmore X1
Avatar
Avatar
azonenberg
Interesting. But my goal here is not so much "I want to build an asic on gf180 with pcie" as it is pathfinding for future gen e.g. pcie gen3/4/5 on $FAB 90/65/45
Tim 'mithro' Ansell 04/20/2026 06:45
I was thinking of it as a way to experiment with different parts of the system split between ASIC and FPGA side - like what I describe in https://bit.ly/open-pipe-talk
[External Access] SERDES, PIPE and protocols - Pathway to fully ope...
SERDES, PIPE and protocols Pathway to fully open source implementations... Presenters Tim ‘mithro’ Ansell <tansell@google.com> bit.ly/open-pipe-talk
Thumbnail
Avatar
azonenberg 04/20/2026 06:46
Fair, that is definitely a possibility and i absolutely like the idea
06:46
also for zynq-style cooperation flows
Avatar
tnt 04/20/2026 06:47
Well SGMII would be nice 🙂
Avatar
azonenberg 04/20/2026 06:47
e.g. maybe you could run something like 16-bit APB/AHB between the asic and fpga die or something
Avatar
Avatar
tnt
Well SGMII would be nice 🙂
azonenberg 04/20/2026 06:48
yeah i think even sgmii is going to be hard, from what i have seen from you and other folks, without the 1.8v fets. with them, it's probably doable
06:48
i think 1/4 rate pcie as a sandbox is likely doable though
06:48
try to build out a full flow with VCO, CDR, equalizers, etc
06:49
i.e. 625 Mbps instead of 2.5 Gbps
06:49
that's just barely around Fmin of xilinx GTP/GTXs
Avatar
tnt 04/20/2026 06:49
I wouldn't necessarily based anything on my results ... I'm a novice analog designer 😅
Avatar
azonenberg 04/20/2026 06:49
and i have a computer science degree :p
06:49
Not an EE
06:50
i need to learn a ton of analog to be able to actually build CMOS analog that does anything
06:50
i'm reasonably confident i could build digital standard cells without a lot of trouble since i've RE'd so many of them by now
06:50
one of the things i want to do soonish, and will probably be asking for some handholding at some point, is building some 3.3V cells for gf180mcu
06:51
i know other people are doing it but i want to learn and i figure i should build an inverter before i build a VCO :p
Avatar
tnt 04/20/2026 06:54
There are some. Tholin made a library.
06:54
It's not silicon proven yet but some proto should be on WS1 run.
Avatar
azonenberg 04/20/2026 06:54
Well, i'll look after i've done a few on my own
06:55
and see how much better theirs are :p
06:55
i dont want to end up unconsciously copying, i want to start from just the design rules and see what i come up with
06:55
then compare after
Avatar
tnt 04/20/2026 06:56
Oh ... I misread the sentence ... I thought you'd be asking for someone to do it, not that you wanted to do it yourself, my bad.
Avatar
azonenberg 04/20/2026 06:56
no i want to do it as a learning exercise
06:56
and probably put it on a TT because why not
Avatar
tnt 04/20/2026 06:56
Yeah make sense.
Avatar
azonenberg 04/20/2026 06:56
and if mine end up being good enoguh other people can use the lib, great
06:56
the goal is both for practice with the tools, and to prep for eventually building a 1.8v lib if we manage to get full gf180bcd or whatever it's called one day
06:57
first step is going to be figuring out what tools i still need to set up and learning how to integrate them to do simulations etc
06:57
i've used yosys before but my copy is probably hopelessly out of date, i have klayout installed already for other reasons
06:57
i installed the gf180mcu PDK
06:58
i installed magic but the UI is so horrible i want to stick with klayout if at all possible
06:58
i do not have any extraction or P&R tools installed to my knowledge
06:58
or timing
06:58
i assume most or all of that is part of openlane which i havent set up yet
Avatar
tnt 04/20/2026 06:58
extraction is actually done with magic ...
Avatar
azonenberg 04/20/2026 06:59
ah ok, well then i'm going to have to suck it up and deal with the pain lol
Avatar
tnt 04/20/2026 06:59
klayout is starting to have basic extraction, but it's new and basic ATM, never tried it.
Avatar
azonenberg 04/20/2026 06:59
last time i poked at it i turned off some layers and couldnt figure out how to turn them back on
06:59
i tried various combinations of left/right/middle click, double click, ctrl/alt/shift on the layers window
07:00
and nothing turned them back on
07:00
but yeah basically before i do much of anything else i want to get all of the tooling installed, draw an inverter, and figure out how to simulate it. then do a ring oscillator, then some more cells
Avatar
tnt 04/20/2026 07:01
I actually like magic . The learning curve is steep but after a few hours, I end up way more productive than with point and click in klayout. (edited)
07:02
There was a "cheat sheet" around with the default keyboard short cuts.
Avatar
azonenberg 04/20/2026 07:02
I would like to see a new tool with a UI from this century and GPU accelerated rendering one day. Maybe it'll just be a frontend around magic's geometry kernels and extractions and stuff
07:02
klayout has no gpu acceleration at all afaik, magic is opengl but not as much as i would hope to see
07:02
klayout gets reeeeally slow on big gds's
07:02
years back i opened a TS28HPC+ GDS on it
07:02
it... was navigable, with difficulty
07:03
but not what i would consider acceptable performance for actually doing any kind of engineering
07:03
obviously the kinds of things we're doing on gf180mcu will have much less polygons
07:03
and not 50+ GB GDS's
Avatar
Tim 'mithro' Ansell 04/20/2026 07:04
@azonenberg - I've always thought that you could load the GDS into something like the Google Maps API 😛
Avatar
azonenberg 04/20/2026 07:05
Sooo i would actually like to see something along those lines that does tile based rendering and caches a texture for each layer as a png on disk
07:05
precomputing stuff so the drawing is ~instantaneous
07:05
i have experienec building such stuff for GIS in years back
07:06
but my long term vision for what i want to see in a next-gen layout editor/viewer is something using vulkan which seems to be the way of the future for cross platform, and the ability to use it for both rendering and compute acceleration
07:06
i want GPU LVS/DRC/extractions, field solver, etc :p
Avatar
tnt 04/20/2026 07:06
Grid is 5 nm, chip is 3x5 mm tha'ts one 600k x 1000k PNG per layer.
Avatar
azonenberg 04/20/2026 07:06
no not a single image
07:07
you do a pyramid like google maps
07:07
max zoom is say 512 x 512 5nm pixels per tile
07:07
then you'd have power of 2 or 4 reductions from that
07:07
one set of tiles per layer
07:08
And you don't have to render them all in advance. you can rough decimate and render low res of the whole chip, then as the user pans and zooms render things just off screen in anticipation of them coming into view soon
07:08
this is what I did in a GIS app years back, we'd prefetch and decompress tiles in th edirection you were panning and zooming before they got on screen
Avatar
tnt 04/20/2026 07:08
Sure but eventually you still end up with that full resolution stored on disk. Even if split. Even if you manage to compress 100:1 that's still 500 Mbytes per layer.
Avatar
azonenberg 04/20/2026 07:08
no popping and LOD delays like google maps has
07:09
Well yes, but it can be sparse. you won't be looking at every tile all the time
07:09
you can cap the cache to however many GB the user wants to allocate
07:09
and re-render tiles as needed
07:09
also realistically for ASIC design a couple GB of disk space is not an unreasonable ask
07:11
anyway, i have way too many things on my plate already and i am not attempting to replace magic or klayout any time soon
07:11
but I am tempted to try to make a gpu accelerated view-only GDS display tool as a PoC some time to feel out the idea
07:12
and if it turns out to be something we can start porting editing functionality from the other tools into, great. if not, maybe it'll just be the asic version of gerbview
Avatar
Leo Moser (mole99) 04/20/2026 07:12
There's "THE CHIPMAP™: VISUALIZING LARGE VLSI PHYSICAL DESIGN DATASETS" by Jeff Solomon, December 2002. It implements a mipmapping pyramid, as you described.
Avatar
Avatar
tnt
I actually like magic . The learning curve is steep but after a few hours, I end up way more productive than with point and click in klayout. (edited)
azonenberg 04/20/2026 07:23
i've worked with some heavily CLI/keyboard based tools and dont like them much
07:23
i like menu/mouse driven stuff that have keyobard shortcuts for common actions but it's not the main/only way to do things
Avatar
Avatar
azonenberg
something that is protocol compatible with gen1 but underclocked to 1/2 or 1/4 or 1/8 rate
namibj 04/20/2026 11:26
Are the 3.3V devices even too bad to squeeze 2.5 GBaud out of them?
Avatar
Avatar
Tim 'mithro' Ansell
@azonenberg - I'm actually talking to Lattice about getting known good die of Lattice FPGAs to offer co-packaged/wire bonded GF180MCU parts with cheap open source supported FPGAs. That might be a gateway option for exploring PCIe type things further.
namibj 04/20/2026 11:30
I'd consider asking them about what IO buffer performance you'd get with that co-packaging so you can at least try to match it with the connected ASIC pad. A fairly known wire bond has far more constrained parasitics than some "generic" PCB trace.
Avatar
Avatar
tnt
It's not silicon proven yet but some proto should be on WS1 run.
namibj 04/20/2026 11:34
Are the models for gf180mcu at least decent quality, unlike the sky130 ones?
Avatar
tnt 04/20/2026 11:36
No idea, never tried ... And the sky130 ones aren't all that bad, they're just not designed with subthreshold operation in mind because at the time they were made, nobody was doing that ...
Avatar
Avatar
azonenberg
i installed magic but the UI is so horrible i want to stick with klayout if at all possible
namibj 04/20/2026 11:38
Any reason why I shouldn't switch to klayout for my efforts before I sit myself down to watch 6 hours of tutorial(s) in hopes of getting the hang of it without really spare time to "just" dabble "playfully" until I no longer need the manual more than once every 5 minutes?
Avatar
Avatar
azonenberg
last time i poked at it i turned off some layers and couldnt figure out how to turn them back on
namibj 04/20/2026 11:40
Left/right click on the smol square button with the layer draw style "tile" on it.
Avatar
Avatar
tnt
There was a "cheat sheet" around with the default keyboard short cuts.
namibj 04/20/2026 11:41
Link before I wake up again in ~20 hours pls?
Avatar
tnt 04/20/2026 11:42
https://github.com/iic-jku/osic-multitool/blob/main/magic-cheatsheet/magic_cheatsheet.pdf
osic-multitool/magic-cheatsheet/magic_cheatsheet.pdf at main · iic...
JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130. - iic-jku/osic-multitool
Thumbnail
11:44
In magic I never use anything else than the box mode and a few time the wiring mode. Never use import from spice or the other mode .....
Avatar
Avatar
tnt
Grid is 5 nm, chip is 3x5 mm tha'ts one 600k x 1000k PNG per layer.
namibj 04/20/2026 11:44
... What is the mask pixel size, anyways? Or do they not quantize at granularity visible in e.g. standard cell design?
Avatar
tnt 04/20/2026 11:45
The manufacturing grid is 5 nm ... that's all we know. The rest is details that are not public/available/specified ...
Avatar
Avatar
azonenberg
i like menu/mouse driven stuff that have keyobard shortcuts for common actions but it's not the main/only way to do things
namibj 04/20/2026 11:45
I think we're supposed to write more TCL and use less mouse with magic
Avatar
tnt 04/20/2026 11:46
But different masks have different resolution, the poly mask is much finer than the implant mask for instance ... they only reserve the finer thing for stuff that needs it.
Avatar
Avatar
tnt
The manufacturing grid is 5 nm ... that's all we know. The rest is details that are not public/available/specified ...
namibj 04/20/2026 11:47
That's the "lossless" pixel size of handing the gds layers as bitmaps instead of their normal vector-shape-stuff?
Avatar
tnt 04/20/2026 11:47
Pretty much. All coordinates need to be aligned to the grid. (edited)
Avatar
namibj 04/20/2026 11:48
I know actual features will be larger, but alignment isn't bound by the same optical resolution laws ferrisCatOwO
Avatar
Avatar
tnt
Pretty much. All coordinates need to be aligned to the grid. (edited)
namibj 04/20/2026 11:48
(only gf180mcu or is sky130 the same/do you remember the number for it?)
Avatar
tnt 04/20/2026 11:51
Same grid for both.
11:51
And IHP too
Avatar
namibj 04/20/2026 11:57
ferrisSquee
Avatar
BreakingTaps 04/20/2026 16:26
++ the general sentiment against KLayout. Everytime I have to use it seriously it makes me angry. I know I shouldn't get mad at OSS, but it's like they looked at all the normal UI conventions and went "Ehh, what if we just change it slightly so everything is just a bit different". also yeah it bogs down fast under bigger designs
Avatar
Avatar
Tim 'mithro' Ansell
I would love to get SEM imaging of various GF180MCU stuff. I think at some point I sent you some samples. I have a lot more potential samples now.
BreakingTaps 04/20/2026 16:28
fwiw I'll be doing imaging of my chip, but not sure if or how many cross-sections. We'll see how lazy I feel. Not sure I'm skilled enough at lapping to de-layer either. Probably need @azonenberg's magic touch for that 🙂
Avatar
Avatar
BreakingTaps
fwiw I'll be doing imaging of my chip, but not sure if or how many cross-sections. We'll see how lazy I feel. Not sure I'm skilled enough at lapping to de-layer either. Probably need @azonenberg's magic touch for that 🙂
Tim 'mithro' Ansell 04/20/2026 16:29
We got some pretty nice sky130 cross sections with some fine grit sandpaper IIRC - @digshadow - Do you remember the method we used?
Avatar
namibj 04/20/2026 16:31
magic's excuse at least is "back in my day we had to use X10, because X11 wasn't invented yet" or something 🙁
Avatar
Avatar
Tim 'mithro' Ansell
We got some pretty nice sky130 cross sections with some fine grit sandpaper IIRC - @digshadow - Do you remember the method we used?
BreakingTaps 04/20/2026 16:34
we actually have a nice little lapping station here at work i'll probably use after hours. epoxy molds, full set of grits, water flushing etc. mostly a laziness problem haha 😄 i'll do at least a few, the cross-sections I did of a i486 were a huge hit on the channel a few years ago (ditto to ion etching xsections)
16:35
hoping to get some 3d surface profilometry data too
Avatar
Avatar
BreakingTaps
fwiw I'll be doing imaging of my chip, but not sure if or how many cross-sections. We'll see how lazy I feel. Not sure I'm skilled enough at lapping to de-layer either. Probably need @azonenberg's magic touch for that 🙂
namibj 04/20/2026 16:37
Have you considered trying the diamond mirror tactics on chips? If they have enough layer adhesion it should be possible to cut them with a defined edge (not just sand them off with undefined edges) without delaminating it?
Avatar
BreakingTaps 04/20/2026 16:38
oh that's a fun idea! I don't think my machine would have the accuracy needed, it's "only" +/- a few microns positioning accuracy. But I might be able to convince some diamond lathe friends to try that 🤔
16:40
will have to think about the material stack, there are some materials that diamonds don't like to cut. mostly ferrous materials so probably ok, but will need to think about the nitrides and silicides
Avatar
namibj 04/20/2026 16:40
Actually I was particularly thinking towards cross-section ability, possibly of a trench/angled nature
Avatar
BreakingTaps 04/20/2026 16:40
ahh I see, which wouldn't care about positioning at all. hmmmmm
Avatar
namibj 04/20/2026 16:41
Well, would, but that "only" should suffice
Avatar
BreakingTaps 04/20/2026 16:41
yah
Avatar
namibj 04/20/2026 16:43
For scraping off BEOL though I'd assume supervision with just a medium-power optical microscope (NA=0.3 or around) to be plenty for controlling how much more needs to go.
Avatar
BreakingTaps 04/20/2026 16:46
think so yeah. my fixturing system has a few microns of repeatability error which might cause issues if I have to pull it off the machine to check under a scope, but can probably make things work
Avatar
namibj 04/20/2026 16:46
dud chips are cheap and plenty, don't be afraid to try
Avatar
BreakingTaps 04/20/2026 16:46
hehe yes, I have a whole pile of wafers and chips to destroy as needed 😄
Avatar
namibj 04/20/2026 16:47
pull it off the machine to check under a scop
just slide it off to the side and affix the objective such that it can look at the work site without having to release the fixture
Avatar
BreakingTaps 04/20/2026 16:49
yeah was thinking something to that effect. it's a bit tricky since there's not really space to mount anything inside the machine, and you have to defeat some door interlocks if you want to run the machine with the door open and stuff hanging out. but i've done it before, just a PITA to get setup 🙂
Avatar
namibj 04/20/2026 16:58
I still have to get my handful of V2S200D soldered to try them out... they took a regular PDM asic and swapped the membrane for a probe mass.
17:00
(After I've shipped the best high speed serializer I can fit into the little space on my small sky26a 1x2 tile, so in 3 weeks.)
Avatar
Avatar
azonenberg
Sooo i would actually like to see something along those lines that does tile based rendering and caches a texture for each layer as a png on disk
Christopher 04/20/2026 17:05
Im actually looking at doing this for training a CNN for those capacitors heh
Avatar
Avatar
namibj
Are the 3.3V devices even too bad to squeeze 2.5 GBaud out of them?
azonenberg 04/20/2026 19:02
no idea. i'm gonna make it as fast as I can whenever i get to it on whatever PDK is available at that time
19:03
and if i have to downclock it by a few powers of two, it'll still let me prove out the architecture, digital protocol stuff, and learn things
Avatar
namibj 04/20/2026 19:19
hmmm
Avatar
Avatar
azonenberg
no idea. i'm gonna make it as fast as I can whenever i get to it on whatever PDK is available at that time
namibj 04/20/2026 19:21
You gonna use scripted "cells" for the differential high speed logic parts (I don't mean the output power stage, but rather the mux/latch/serializer)?
19:23
(I don't think it's wise to hand-draw the MCML for my trials, and I haven't yet found anything vaguely represenative to learn from.)
Avatar
Avatar
namibj
You gonna use scripted "cells" for the differential high speed logic parts (I don't mean the output power stage, but rather the mux/latch/serializer)?
azonenberg 04/20/2026 19:32
I have no experience doing that but should probably learn at some point
19:32
i've never done ASIC layout at all so everything is new to me :p
19:32
i've looked at a ton of other people's layout since I do silicon RE as part of $dayjob
19:33
(but entirely digital focused)
Avatar
namibj 04/20/2026 19:33
I didn't expect the tooling to be this.... obtuse
Avatar
azonenberg 04/20/2026 19:33
i've done RTL design for both FPGA and ASIC
19:33
and a lot of custom floorplanning for FPGA, plus working with physical designers on ASIC to do high level floorplanning and looking at the resulting GDS (in klayout because they didn't want to buy me a synopsys tool seat for some silly reason, not like they're expensive or anything :P)
Avatar
namibj 04/20/2026 19:34
it ehhhh... latches.....
Image attachment
Avatar
azonenberg 04/20/2026 19:34
but never actually drawn mask layer polygons by hand
Avatar
namibj 04/20/2026 19:34
nono I don't want to draw by hand
Avatar
azonenberg 04/20/2026 19:34
(or done any scripted cell generation)
19:35
also, the default colors in the techfiles are so confusing to me lol
19:35
or not sure if the color comes from techfile or if its klayout/magic prefs?
19:36
in the RE space i'm used to drawing p diffusion as dark yellow-brown, n diffusion as green, not drawing P+ or N+ explicitly, poly as red, metal1 as dark blue, other colors for higher metal layers
Avatar
namibj 04/20/2026 19:39
(Like, that's the issue..... I know I could just sit down and power through and just draw by hand or hard-code-script by hand in magic with bare rectangles on the relevant layers until I get the couple cells needed.... but there's no decent way to make that style of "cell design" undergo some nightly batch optimization for e.g. symmetrizing edges, favoring as much missmatch tolerance as needed for usable yield, and making sure logic levels are set so that symmetrized loads can provide their PSRR benefits.)
Avatar
Avatar
azonenberg
(or done any scripted cell generation)
namibj 04/20/2026 19:41
I do expect this work to be largely portable between the gf180mcu and the sky130a processes, even if some layout arrangements have to swap due to the massive transistor size difference (yet IIUC basically same metal sizes), so... yeah.
Avatar
azonenberg 04/20/2026 19:42
are the 3.3v fets any bigger?
19:42
or are you using 5v for this?
19:42
i thought the 5v fets were huge but the 3.3 were about the same size as the 1.8 just slower
19:42
but i never actually looked into it
19:43
or are the 3.3 still longer channels?
Avatar
Avatar
azonenberg
are the 3.3v fets any bigger?
namibj 04/20/2026 19:43
You mean between the two processes?
19:44
Note that the minimum gate length for 3V operation is 0.5 µm.
19:44
The 5V device has minimum gate length of 0.9 µm.
19:44
"huge" isn't the word I'd use
Avatar
Avatar
namibj
The 5V device has minimum gate length of 0.9 µm.
azonenberg 04/20/2026 19:44
900nm wow no wonder they chomnk
Avatar
namibj 04/20/2026 19:44
but 1.8V devices are 0.15 minimum
Avatar
Avatar
namibj
Note that the minimum gate length for 3V operation is 0.5 µm.
azonenberg 04/20/2026 19:44
that's still quite large lol
19:45
this is going to be a wierd process to design for with how "cheap" high density metal is compared to transistors
Avatar
Avatar
azonenberg
900nm wow no wonder they chomnk
namibj 04/20/2026 19:45
that's to get the safe operating area up to gate fully on and 5V difference between source and drain
Avatar
azonenberg 04/20/2026 19:46
are those specs for the thick oxide? we have two oxide thicknesses available right?
19:46
or is "3v operation" assuming thin oxide
Avatar
namibj 04/20/2026 19:46
e.g. 11V/16V NMOS FET
Image attachment
Avatar
azonenberg 04/20/2026 19:46
aiui there's 3 oxide thicknesses total on gf180 family and we only have the two thicker available on gf180mcu? (edited)
Avatar
Avatar
azonenberg
are those specs for the thick oxide? we have two oxide thicknesses available right?
namibj 04/20/2026 19:46
there's a 1.8 oxide and a 5.5 oxide
Avatar
azonenberg 04/20/2026 19:46
oh
19:47
i thought there were two oxides and you had the choice of 1.8 and 3.3 or 3.3 and 5
19:47
and gf180mcu was the latter
19:47
so the 3. 3 and 5v fets are the same oxide and you just draw longer channels to get 5v vds?
19:47
so vgs max is the same for either?
Avatar
Avatar
azonenberg
so the 3. 3 and 5v fets are the same oxide and you just draw longer channels to get 5v vds?
Lofty 04/20/2026 19:49
yes
Avatar
azonenberg 04/20/2026 19:49
Interesting, i must have misunderstood what i was reading on the pdk docs then
19:50
i thought we still had two thicknesses, just that our "thin" was the normal 1.8v process's "thick"
19:50
and our "thick" was extra-thiccc
19:50
well that explains some things then
19:50
i guess that means our 3.3 fets and the normal process's 3.3 fets are not the same then?
19:51
or do their 3.3 use this same thick oxide?
Avatar
namibj 04/20/2026 19:57
ok huh
19:58
apparently only 1 gate oxide but there's also a field oxide
19:58
oh sorry I thought you meant "my" (short-term) pdk situation
Avatar
Avatar
azonenberg
that's still quite large lol
namibj 04/20/2026 19:59
sorry the numbers I just quoted were sky130a
19:59
gf180mcu does have two oxide thicknesses used for different voltage devices in a single process
Avatar
azonenberg 04/20/2026 20:00
OK so i was right
Avatar
namibj 04/20/2026 20:00
(afaik only ever 2)
Avatar
azonenberg 04/20/2026 20:00
there are 3 thicknesses available and gf180mcu has the two thicker
20:00
and the 1.8v version has the thinnest plus one of the two thicker for io
Avatar
namibj 04/20/2026 20:00
dunno how exactly sky130a manages to have both 1.8V devices of IIUC quite decent performance as well as (up to) 20V FETs, but oh well
Avatar
azonenberg 04/20/2026 20:02
so how big are the 3.3 fets on gf180mcu then?
20:02
and the 5 (edited)
Avatar
namibj 04/20/2026 20:02
https://gf180mcu-pdk.readthedocs.io/en/latest/
Avatar
azonenberg 04/20/2026 20:03
i poked around there and didnt see dimensional rules for poly, got a direct link?
Avatar
namibj 04/20/2026 20:03
https://gf180mcu-pdk.readthedocs.io/en/latest/analog/model_parameters/LV/LV_1_5_1.html
20:04
0.22 0.28
20:04
W L
Avatar
azonenberg 04/20/2026 20:04
ok so 280nm channel length for the 3.3 fets
20:04
and looks like 500/600 for the 5v?
Avatar
namibj 04/20/2026 20:05
nfet 06v0 0.3 0.6 pfet 06v0 0.3 0.5 nfet_06v0_nvt 0.8 1.8
Avatar
azonenberg 04/20/2026 20:06
whats the difference between _nvt and normal nfet? is that a high vt low leakage one? or higher vds max?
Avatar
namibj 04/20/2026 20:06
Image attachment
20:06
for cascodes I think?
Avatar
Avatar
azonenberg
whats the difference between _nvt and normal nfet? is that a high vt low leakage one? or higher vds max?
namibj 04/20/2026 20:06
native threshold voltage
20:07
uses light P doping of wafer for the channel with no implants in the channel
20:07
as you can see, it's effectively a depletion-mode nmos
20:08
(i.e. gate voltages are more like a jfet than a "normal" mosfet in operation; it's still a mosfet though so the gate is floating and isolated in both polarities)
20:11
https://en.wikipedia.org/wiki/Native_transistor huh
Native transistor
For electronic semiconductor devices, a native transistor (or sometimes natural transistor) is a variety of the MOS field-effect transistor that is intermediate between enhancement and depletion modes. Most common is the n-channel native transistor. Historically, native transistors were referred to as MOSFETs without specially grown oxide, only ...
Avatar
azonenberg 04/20/2026 20:14
interesting. i'm used to just having lvt/svt/hvt implants
20:14
just to trade leakage against speed
20:15
but i know very little about anything like this which seems like what you'd use in more analog stuff
Avatar
namibj 04/20/2026 20:23
apparently they're good as current sources because you can tie the gate to source and they behave as a current source
20:24
(ofc in that case the absolute current isn't PT stable but it is fairly V stable as it obviously should)
20:25
and at times thay may have lower resistance probably due to the absurdly low threshold voltage giving insane overdrive
Avatar
Avatar
azonenberg
but i know very little about anything like this which seems like what you'd use in more analog stuff
namibj 04/20/2026 20:25
You've seen some nmos cascodes before, right?
Avatar
azonenberg 04/20/2026 20:27
i've heard the term and have probably seen them but cant remember specifics
20:27
the vast majority of what i do is just standard cell logic
Avatar
Avatar
azonenberg
i've heard the term and have probably seen them but cant remember specifics
namibj 04/20/2026 20:33
Image attachment
20:34
if the top one has convenient threshold you can apparently tie it's gate to the bottom one's gate? they say, calling that "self-cascode"... weird anyways; but yeah, should be easier to bias as you can tie it off to ground
Avatar
azonenberg 04/21/2026 04:55
@Tim 'mithro' Ansell btw looking at the wafer photos it looks like a grid of normal sized dies, then short and skinny on one side and tall and skinny on the other
04:55
then there's an ultra small spot in the corner
04:55
i didn't see that ultra small spot as an orderable option, is that foundry test or your personal projects or what?
Avatar
Brian Swetland 04/21/2026 04:55
Double Secret 0.5 x 0.5 Die
Avatar
azonenberg 04/21/2026 04:55
(or is that tinytapeout lol)
Avatar
Brian Swetland 04/21/2026 04:55
!
Avatar
Avatar
namibj
native threshold voltage
Saltypretzel 04/21/2026 04:57
Are natives supported on this process? I worked with some other fab and they had to be special requested
Avatar
Avatar
azonenberg
i didn't see that ultra small spot as an orderable option, is that foundry test or your personal projects or what?
RebelMike 04/21/2026 05:20
I guess it’s not orderable because there’s only one of them - it basically exists as a consequence of the half slots existing. The usable area is similar to the largest design you can put on Tiny Tapeout. On run 1 that has my TinyQV SoC in it as a test. I’m not sure if it’ll actually get bonded though as it would require a different setup just for that one slot.
Avatar
Leo Moser (mole99) 04/21/2026 06:24
In wsrun #2, there are actually three quarter slots, as we're adding one more horizontal cut. But yes, Tim wanted to keep those for other purposes.
Avatar
Avatar
azonenberg
@Tim 'mithro' Ansell btw looking at the wafer photos it looks like a grid of normal sized dies, then short and skinny on one side and tall and skinny on the other
Tim 'mithro' Ansell 04/21/2026 06:38
You can compare to https://github.com/wafer-space/ws-run1
GitHub - wafer-space/ws-run1: wafer.space GF180MCU Run 1
wafer.space GF180MCU Run 1. Contribute to wafer-space/ws-run1 development by creating an account on GitHub.
Thumbnail
Avatar
Avatar
Saltypretzel
Are natives supported on this process? I worked with some other fab and they had to be special requested
Tim 'mithro' Ansell 04/21/2026 06:39
I think @Leo Moser (mole99) or @Tim Edwards might know...
Avatar
tnt 04/21/2026 06:40
See https://discord.com/channels/1361349522684510449/1425483172166238410
Avatar
Tim 'mithro' Ansell 04/21/2026 06:53
Also https://mithro.github.io/gf180mcu-project-template/
❤️ 1
Avatar
Tholin 04/21/2026 23:22
I have never seen this before
Image attachment
Avatar
Tim 'mithro' Ansell 04/22/2026 03:38
@Tholin - That is weird it says "1. Shipper or Importer must provide a completed Commercial Invoice." but there was a completed Commercial Invoice uploaded to the electronic documentation and included in the fedex pouch.
Avatar
tnt 04/22/2026 06:12
Heh, I also got FedEx import trouble this morning ( unrelated shipment ), they're asking for 3 times more than I was expecting as import fee ...
Avatar
Avatar
Tim 'mithro' Ansell
@Tholin - That is weird it says "1. Shipper or Importer must provide a completed Commercial Invoice." but there was a completed Commercial Invoice uploaded to the electronic documentation and included in the fedex pouch.
Tholin 04/22/2026 16:00
I can even view the invoice. But I clicked the button and all they actually wanted was for me to agree to accept any additional fees and import charges that might come up. I just had to click a checkbox. (edited)
Avatar
Tholin 04/22/2026 16:08
It may be a while until I have my dies. Fedex is extremely unaccommodating to people who are never home during their delivery times its always a days-long back and forth that usually ends in me having to waste a PTO day just to be home for the delivery. (edited)
Avatar
Dory 04/22/2026 16:28
Yeaaah FedEx ain't the best. They sent me a letter to my house threatening legal action because I didn't pay 24€... Turns out I paid it, they just rejected it without giving any reasons and never told me to resend it... Fun...
Avatar
tnt 04/22/2026 17:36
Others are not much better. I had UPS forget the decimal point when doing a custom declaration ... requesting VAT on a value of >6000$ instead of 60.xx $ ...
Avatar
Dory 04/22/2026 17:38
GLS sending my package to their office, in the other side of the city, because "I wasn't home" (I was home)
17:39
NAtional post telling me they would deliver a package after the weekend because I "wasn't home" (I watched the mailman take a smoke break in front of my house and then leave as I got the message)
17:39
Idk why but postal services seem fucked up at some kind of base level
17:39
Worthy of a dissertation on both economy of logistics companies, and the psychology of the morons running and working for them
Avatar
namibj 04/23/2026 11:15
Longer-term the economy of actually specifically such a "high voltage" capable process with low per-die cost makes me want to go for my "MVDC-tamer" project again, getting back into it around next year it seems (looks at schedule of active projects). It's a switched capacitor converter around 13.56 MHz (or half/double; for interference mitigation reasons) with a central FPGA brain and optically isolated floating drivers that yeet out digital pre-distortion waveforms to an expected class-B "vaguely linear PA" that then actually wobbles the gate of a 10s of mm² WBG "power switch"-class transistor. The power switches are depending on native voltage rating series-connected for extra blocking voltage which necessitates extremely precise coordinated switching. Previous best opportunity was an ice40 up5k married to a Parallax Propeller 2 for a few (3~8 depending on finer details) local power switch dies undergoing individual waveforms and supervision. (Propeller 2 GPIOs have 3ns 8bit DACs at 123.75 Ohm (@3.3 V full-swing; with a resistive load to GND that gives nice 75 Ohm @2V) in each one as well as a first order Delta sigma modulator able to have it's own bitstream mirrored by a nearby GPIO; the idea was for the ice40 to take the raw bitstream and extract information on real gate voltage waveform by reconstructing the harmonics individually, and helping the processor update it's wavetable.) But a P2 is like 12$ in quantity plus the up5k and importantly not yet including the analog PA. [It has 64 GPIOs and 512 kiB of shared RAM plus 512x 32bit registers plus 2 kiB core-local addressed ram (used e.g. for DMAStreamer to feed the DACs) with 8 cores. Clocks are RP2350 tier, it's 130nm on-semi. Ofc that's fairly overkill for just feeding a gate driver and measuring the gate waveform to adjust things.] I know the sky130 process allows on-die photodiodes; if that's also on gf180mcu the optical receiver could also be on-die.
11:17
Probably the most relevant aspect to using wafer.space ASIC would be if they could be less thick, I guess.
Avatar
Leo Moser (mole99) 04/23/2026 12:28
The first bare dies have arrived! 🥳 All that hard work has paid off when you finally hold the chips in your hands ✨
Image attachment
Image attachment
Image attachment
🎉 8
Avatar
Avatar
namibj
Probably the most relevant aspect to using wafer.space ASIC would be if they could be less thick, I guess.
Tim 'mithro' Ansell 04/23/2026 13:03
The die people just received are ~250um thick.
Avatar
namibj 04/23/2026 13:05
ohhhh yeah that would be fine
Avatar
Meinhard Kissich 04/23/2026 14:18
Arrived! 🥳🎉 It’s so exciting to see the actual dies. Thanks everyone at wafer.space and everyone involved for making that possible 😊 https://github.com/meiniKi/gf180mcu-fazyrv-hachure Shuttle ID: G801 Code: CAFE Can’t wait to make some more close up photos under a better microscope and bring up the chip 😀🤞 (edited)
Image attachment
❤️ 1
Avatar
Tholin 04/23/2026 14:18
I will get home in two hours. I know my dies and a microscope I impulse-purchased are waiting for me there.
💯 2
14:19
Stay tuned!
Avatar
Avatar
Meinhard Kissich
Arrived! 🥳🎉 It’s so exciting to see the actual dies. Thanks everyone at wafer.space and everyone involved for making that possible 😊 https://github.com/meiniKi/gf180mcu-fazyrv-hachure Shuttle ID: G801 Code: CAFE Can’t wait to make some more close up photos under a better microscope and bring up the chip 😀🤞 (edited)
Tim 'mithro' Ansell 04/23/2026 14:20
Please share your project ID and links to your project on GitHub with things like photos so that we know what we are looking at! 🙂
Avatar
Avatar
Tim 'mithro' Ansell
Please share your project ID and links to your project on GitHub with things like photos so that we know what we are looking at! 🙂
Meinhard Kissich 04/23/2026 14:29
Added. Thanks for the hint 😊
Avatar
Tim 'mithro' Ansell 04/23/2026 14:30
14:32
Bed time for me, hope to wake up to more exciting photos and reports 🙂
Avatar
azonenberg 04/23/2026 14:33
Awesome to see
14:33
y'all are making it very hard for me to focus on $dayjob stuff and not drop everything to start playing with layout for one of my projects :p
Avatar
RebelMike 04/23/2026 14:56
It looks like mine (TQVA/TQVB/TQVC) have successfully been delivered to my office, but I'm away until 12th May so it'll be a while before I see them!
🥲 3
❤️ 1
Avatar
Simi 04/23/2026 16:05
Our bare die also arrived! 🎉 Such a good feeling. Thanks again! 🙌
Image attachment
💯 3
🎉 6
Avatar
Avatar
Simi
Our bare die also arrived! 🎉 Such a good feeling. Thanks again! 🙌
namibj 04/23/2026 16:26
Does this look like the pad ring is technically excessively wide, as only the immediate surroundings of the silvery pads "need" to be reserved? Like, sure, that gives space for the IO transistors associated with that pad, but that's the only "necessity", or not?
Avatar
Dory 04/23/2026 16:48
It is said somewhere on the docs that using a custom pad you can get some extra usable area
Avatar
azonenberg 04/23/2026 16:51
Yeah I mean there's ESD structures and such too. but yeah if you did custom you could probably steal a bit of additional space
16:54
But it doesnt look unreasonable from what I have seen on other 180nm nodes
16:55
see this (somewhat dirty but it was the first photo I had handy Xilinx XC2C32A on UMC 180nm
Image attachment
16:55
this is a smaller die so the padring dominates more
16:57
or the XC2C384 which is... i dont have measurements off the top of my head but probably a bit taller and ~twice as wide as a waferspace tile?
Image attachment
16:58
On most of these older nodes with less metal layers, inboard of the pad itself it's common to have a set of large multilayer metal rings for vccio, vcore, and ground. And that does eat area, so might as well put your esd diodes and pad drivers and such on the lower layers underneath
Avatar
The Computer Guy 04/23/2026 17:02
Huh that pre check repo on GH seems to do DRC better than running it through KLayout for GF180MCU. Hopefully I can get the DRC to pass this week.
Avatar
Tholin 04/23/2026 17:09
Something happened there
Image attachment
Avatar
xianglin_pu 04/23/2026 17:34
First round dies arrived for MOSbius chip. Thanks @Tim 'mithro' Ansell @Andrew Wingate Some dies are off the grid
Image attachment
❤️ 1
🎉 1
Avatar
Tholin 04/23/2026 18:00
Image attachment
Image attachment
Image attachment
🎉 11
18:05
AS03
18:05
https://github.com/AvalonSemiconductors/ws-submission-2025/
Avatar
Tholin 04/23/2026 18:15
NEED to get these to someone with a better microscope. I got some connections I can try and use for this.
Avatar
Matt Venn 04/23/2026 19:21
Amazing!
Avatar
Max Vallone 04/23/2026 19:26
The art is unreal!
Avatar
RebelMike 04/23/2026 19:29
Awesome! I wish I’d put some art on mine now!
Avatar
azonenberg 04/23/2026 21:01
If anybody wants to send me dies to image, I can run them on my Labsmore X1 CNC optical microscope at 20x easily
21:01
Since there's no decap involved it's like 5 minutes of work for me to put a bare die under the scope, focus on the corners, and let it rip
21:01
then another 5 to stitch and crop afterwards
21:06
If I get to upload the images to siliconprawn i'll do it for free, just send me a prepaid return shipping label if you want the silicon back (edited)
Avatar
Avatar
Tholin
NEED to get these to someone with a better microscope. I got some connections I can try and use for this.
azonenberg 04/23/2026 21:07
^
Avatar
Tholin 04/23/2026 21:09
You just need one die? Or two or three, in case something goes wrong?
Avatar
azonenberg 04/23/2026 21:09
I only need one, and these are big/thick enough I do not anticipate problems. If you want to send a few for insurance, that's fine though
Avatar
azonenberg 04/23/2026 21:18
Just to avoid a second shipment in case I drop one or chip a corner with tweezers or something
Avatar
Tholin 04/23/2026 21:38
Alright. Do I have to ship it far from here in the EU?
Avatar
azonenberg 04/23/2026 21:39
I'm in the US but postage for something that small/light will probably not be too bad
21:44
near Seattle if you wanted to get a rough price and decide based on that
Avatar
Avatar
azonenberg
I'm in the US but postage for something that small/light will probably not be too bad
namibj 04/23/2026 21:55
actually pretty bad because you have to go for full fedex-class shipment unless it changed in the past few months again; reason being the mandate for DDP shipping. Err, apparently private gifts up to 100$ are allowed. 16 EUR uninsured; 26.5 EUR insured, from Germany via DHL; delivery should be through USPS.
Avatar
azonenberg 04/23/2026 21:57
yeah i would expect post office, if you shipped as commercial samples or gifts, since no money is changing hands, would be the cheapest option
Avatar
Dory 04/23/2026 21:58
Huh I would just send it as a padded letter. If they're within dimensions they should not be more than 5€
Avatar
azonenberg 04/23/2026 21:58
yeah thats what I was assuming you would do
21:58
padded bubble mailer
Avatar
Dory 04/23/2026 21:58
And they also would not need to be declared afaik
Avatar
azonenberg 04/23/2026 21:58
not a box
Avatar
Avatar
Dory
And they also would not need to be declared afaik
zyp 04/23/2026 22:02
probably needs a CN22 but doesn't need to say more than e.g. «gift, semiconductor sample» and some realistic sounding value
Avatar
azonenberg 04/23/2026 22:03
yeah, decalre it as $4 or $7 or whatever the per die cost is
22:03
that should easily fit under the gift limit
Avatar
Avatar
Dory
Huh I would just send it as a padded letter. If they're within dimensions they should not be more than 5€
namibj 04/23/2026 22:03
Your country still allows goods in international letters?
Avatar
Dory 04/23/2026 22:03
Yeah lol
22:03
I used to ship stickers that way
Avatar
namibj 04/23/2026 22:04
Germany ceased in like 2018 or so
Avatar
Dory 04/23/2026 22:04
As long as it's within parameters it counts as mail, and therefore there's no legal need to declare it or any way to have it inspected unless they feta you have ricin inside or similar biohazards/radioactive samples/flammable materials
22:05
If it's not in the illegal items list and it fits, a post stamp will get the job done
Avatar
namibj 04/23/2026 22:05
ehhhh that's not true for international
22:05
because you do need customs declaration if it's goods
22:05
(this may well be "gift", but it's still declaration)
Avatar
zyp 04/23/2026 22:06
CN22 is the declaration sticker you can put on small padded envelopes (edited)
Avatar
namibj 04/23/2026 22:06
There are few exceptions to that outside of customs unions. The issue outbound from Germany e.g. is that you can't send mere letters with customs declaration on them.
22:07
The packaging literally doesn't matter beyond that some thicker parcel classes (not the small 2kg class ones I'm referring to here) mandate hard boxes to ship without surcharge; the small class allows envelope class packaging.
Avatar
azonenberg 04/23/2026 22:07
In years past I have definitely sent ordinary postal envelopes from the US in envelopes with a customs form that covered almost the whole thing
Avatar
namibj 04/23/2026 22:08
Oh you could in the past from Germany too
Avatar
azonenberg 04/23/2026 22:08
but it was allowed and not absurdly priced, single digit USD postage
22:08
i cant remember how recently i last did it
Avatar
namibj 04/23/2026 22:09
They no longer allow that with just a 1.25 EUR (20g)/1.8 EUR (50g)/3.3 EUR (500g)/6.5 EUR (1000g) stamp value though.
22:09
I don't know if the US has ceased outbound letters from having customs declarations
Avatar
Avatar
azonenberg
near Seattle if you wanted to get a rough price and decide based on that
Tholin 04/23/2026 22:10
Alright. Lemme know where to send it to and I’ll see about it tomorrow.
Avatar
azonenberg 04/23/2026 22:10
yeah the only customs changes I know about in the US the last few years were inbound
22:10
as i buy a lot more stuff from overseas than the other way around
Avatar
zyp 04/23/2026 22:10
hmm, I think this is what we're all talking about, DHL is just charging more for it than other countries:
Image attachment
Avatar
namibj 04/23/2026 22:10
also, azonenberg, it's REALLY difficult to get a return stamp from the US
Avatar
Avatar
zyp
hmm, I think this is what we're all talking about, DHL is just charging more for it than other countries:
namibj 04/23/2026 22:11
yeah that's the small parcel
Avatar
zyp 04/23/2026 22:11
in norway, roughly the same dimensions costs me half of that
Avatar
azonenberg 04/23/2026 22:11
If the shipment is that expensive it's probably better if the sample makes a one-way trip
22:11
especially if these are from the early "roughly handled you don't want to use these for real" test batch
Avatar
namibj 04/23/2026 22:12
yeah
22:12
though the other direction would be whatever USPS charges, if they still allow letters it'd be best to paypal you that return postage because usps does not sell that to foreigners
22:13
well, people in foreign
Avatar
namibj 04/23/2026 22:24
that said, for microscoping it, you could argue it's a "document" given that personally taken pictures (not commercial prints of works with royalties) are also very much "documents". Worst case they take the one chip and eat it. Send registered mail mayhaps still under 10 EUR.
Avatar
zyp 04/23/2026 22:25
«microfiche» 🙂
Avatar
namibj 04/23/2026 22:39
well, yeah
Avatar
Avatar
azonenberg
If anybody wants to send me dies to image, I can run them on my Labsmore X1 CNC optical microscope at 20x easily
Tim 'mithro' Ansell 04/23/2026 23:25
FYI - I was planning to send you and a few other people a set of die with one or two samples from every project.
Avatar
Tholin 04/23/2026 23:26
Oh. I guess that solves that
ferrisCatOwO 1
Avatar
Avatar
namibj
that said, for microscoping it, you could argue it's a "document" given that personally taken pictures (not commercial prints of works with royalties) are also very much "documents". Worst case they take the one chip and eat it. Send registered mail mayhaps still under 10 EUR.
Tim 'mithro' Ansell 04/23/2026 23:26
That is part of the reason I want people to get back 1,000 parts even if they think they only need like 20. With that many you can thrown a few in an envelope and if it gets lost, who cares?
23:27
I'm still catching up with all the activity from last night! Great to see everyone is getting chips and such.
Avatar
Avatar
namibj
Longer-term the economy of actually specifically such a "high voltage" capable process with low per-die cost makes me want to go for my "MVDC-tamer" project again, getting back into it around next year it seems (looks at schedule of active projects). It's a switched capacitor converter around 13.56 MHz (or half/double; for interference mitigation reasons) with a central FPGA brain and optically isolated floating drivers that yeet out digital pre-distortion waveforms to an expected class-B "vaguely linear PA" that then actually wobbles the gate of a 10s of mm² WBG "power switch"-class transistor. The power switches are depending on native voltage rating series-connected for extra blocking voltage which necessitates extremely precise coordinated switching. Previous best opportunity was an ice40 up5k married to a Parallax Propeller 2 for a few (3~8 depending on finer details) local power switch dies undergoing individual waveforms and supervision. (Propeller 2 GPIOs have 3ns 8bit DACs at 123.75 Ohm (@3.3 V full-swing; with a resistive load to GND that gives nice 75 Ohm @2V) in each one as well as a first order Delta sigma modulator able to have it's own bitstream mirrored by a nearby GPIO; the idea was for the ice40 to take the raw bitstream and extract information on real gate voltage waveform by reconstructing the harmonics individually, and helping the processor update it's wavetable.) But a P2 is like 12$ in quantity plus the up5k and importantly not yet including the analog PA. [It has 64 GPIOs and 512 kiB of shared RAM plus 512x 32bit registers plus 2 kiB core-local addressed ram (used e.g. for DMAStreamer to feed the DACs) with 8 cores. Clocks are RP2350 tier, it's 130nm on-semi. Ofc that's fairly overkill for just feeding a gate driver and measuring the gate waveform to adjust things.] I know the sky130 process allows on-die photodiodes; if that's also on gf180mcu the optical receiver could also be on-die.
Tim 'mithro' Ansell 04/23/2026 23:29
I would love someone to explore on-die photo diodes on GF180MCU. I don't think they are supported in any way by default but I'm sure people could find ways to make /something/ work.
Avatar
Avatar
azonenberg
y'all are making it very hard for me to focus on $dayjob stuff and not drop everything to start playing with layout for one of my projects :p
Tim 'mithro' Ansell 04/23/2026 23:29
Great to hear! 😛
Avatar
Avatar
Tim 'mithro' Ansell
I would love someone to explore on-die photo diodes on GF180MCU. I don't think they are supported in any way by default but I'm sure people could find ways to make /something/ work.
namibj 04/23/2026 23:31
well, how hard can it be 😄
23:32
take the approach/tactics from sky130's photodiode pcell, port to gf180mcu?
Avatar
Avatar
Tim 'mithro' Ansell
I would love someone to explore on-die photo diodes on GF180MCU. I don't think they are supported in any way by default but I'm sure people could find ways to make /something/ work.
azonenberg 04/23/2026 23:36
I can probably do some characterization if someone sends me a sample, i have a spectrometer i could measure various light sources against
Avatar
Avatar
Tim 'mithro' Ansell
That is part of the reason I want people to get back 1,000 parts even if they think they only need like 20. With that many you can thrown a few in an envelope and if it gets lost, who cares?
azonenberg 04/23/2026 23:36
makes sense
23:36
related: @Tim 'mithro' Ansell what percentage of the overall order cost is the mask set vs the wafer lot?
23:37
like, hypothetically if someone wanted more dies after the first order and was OK with getting everyone else's projects manufactured in higher volume too
23:37
how much would you save doing a second wafer lot on the same mask set
Avatar
namibj 04/23/2026 23:37
a lot for Run1; less lot for Run2 😄
Avatar
Avatar
azonenberg
I can probably do some characterization if someone sends me a sample, i have a spectrometer i could measure various light sources against
namibj 04/23/2026 23:40
do you happen to have any understanding of their design? There's probably some friendly Run2 users with some spare space that could fit such structures.
Avatar
Tim 'mithro' Ansell 04/24/2026 00:10
Don't know if this made it here -> https://www.linkedin.com/feed/update/urn:li:activity:7443670533818204161/ -- Would love to see if someone could figure out how to simulate the patterns we see from things like gf180mcu silicon top layers....
| Kramer Harrison
Sign in or join now to see posts like this one and more.
Thumbnail
Avatar
Avatar
Tim 'mithro' Ansell
Don't know if this made it here -> https://www.linkedin.com/feed/update/urn:li:activity:7443670533818204161/ -- Would love to see if someone could figure out how to simulate the patterns we see from things like gf180mcu silicon top layers....
namibj 04/24/2026 00:12
luxrender should probably be able to handle it, I guess. Might struggle with lateral diffractive structures though, but those aren't as much of an issue on gf180 as with smaller ones.
Avatar
namibj 04/24/2026 00:21
00:21
(progress on MCML P-Cells is going decently; next step is (after sleep) sit down and figure out how I want the routing to be organized, and then go and set that up. This obviously isn't DRC-compliant. There is no good reason why those resulting P-Cells shouldn't quite directly translate to gf180mcu, though. Biggest issue is likely metal layer starvation with that process, though; higher routing density relative to transistor channels might offer opportunities to collapse two of the local routing layers I'll plan to use, though. Without parasitics this buffer, well, two of this plus some P-MOS loads, simulated to 10.332 GHz @ 646 mV differential peak-peak (so 323 mV single-ended swing, well in excess of the required 200 mV for good action from downstream gates). When I have routing finished I'll see about resuming the optimizer loop with parasitics extraction.) (edited)
Avatar
Avatar
azonenberg
related: @Tim 'mithro' Ansell what percentage of the overall order cost is the mask set vs the wafer lot?
Tim 'mithro' Ansell 04/24/2026 01:22
About 60% to 80% is the mask cost.
😮 1
Avatar
azonenberg 04/24/2026 03:03
honeslty i'm surprised its not like 90% lol
03:03
masks are expensive
03:03
i guess not so much on 180
Avatar
azonenberg 04/24/2026 03:41
from what i've heard especially on newer nodes when you order a mask set you practically get the first wafer lot free :p
03:41
i mean you pay for it but the cost is negligible compared to the masks
Avatar
Tim 'mithro' Ansell 04/24/2026 07:24
@azonenberg - I'm buying 25 or 50 wafers
Avatar
azonenberg 04/24/2026 07:50
yeah i was mostly just curious, i dont actually plan to mass produce anything on gf180mcu any time soon
07:51
one batch would be plenty for all of my near term needs
Avatar
Lofty 04/24/2026 11:35
G801CHES. (It's a nightmare to take photos of these...)
Image attachment
Image attachment
Image attachment
💯 2
🎉 3
Avatar
Avatar
Lofty
G801CHES. (It's a nightmare to take photos of these...)
namibj 04/24/2026 15:09
pol filter to cancel specular reflections of the cover tape? "Take one out and stick it to a base that can be handled and have/provision a lid to close over it when not actively imaging"? E.g. say microscope slide and some 3d-printed lid, possibly based on another microscope slide if it should be see-through?
Avatar
Lofty 04/24/2026 15:09
first I would need access to a microscope.
Avatar
namibj 04/24/2026 15:09
Neither of those are microscope-required.
Avatar
Avatar
Tim 'mithro' Ansell
FYI - I was planning to send you and a few other people a set of die with one or two samples from every project.
namibj 04/24/2026 15:21
I'm assuming this is pending clearance (to be allowed to send these off to him) given by all your customers, at least those where the GDSII is not under a license that would allow you to do such anyways (e.g. TT's Apache2)? Though it's probably easy for ya two to just pull some stock NDA template you'd have around and just ship under conditions of not doing anything with the chips that don't release clearance, at least if you don't want to have to wait with that shipment until all customers had reasonable time to opt-in to the siliconprawn. OFC if it turns out there are no chips left that are expected to have siliconprawn-grade surface quality that you could "just" package up into a suitable tray or piece of the tape or so for shipping to him, then sure. Maybe the die sorter control scripting is easy enough to be instructed to just make a tape of round-robin-picks with as many dies of each design as you'd want to allocate to this usage, from which you could later cut continuos strips of (integer multiples of) how-many-designs-there-are to have "sample sets"?
Avatar
Avatar
azonenberg
yeah i was mostly just curious, i dont actually plan to mass produce anything on gf180mcu any time soon
Tim 'mithro' Ansell 04/25/2026 00:41
Yeap! I mean one way to think about it is that I charge $7k USD per customer and I can have ~40 customers, so my costs must be under 40*$7k == $280k USD
Avatar
Avatar
namibj
I'm assuming this is pending clearance (to be allowed to send these off to him) given by all your customers, at least those where the GDSII is not under a license that would allow you to do such anyways (e.g. TT's Apache2)? Though it's probably easy for ya two to just pull some stock NDA template you'd have around and just ship under conditions of not doing anything with the chips that don't release clearance, at least if you don't want to have to wait with that shipment until all customers had reasonable time to opt-in to the siliconprawn. OFC if it turns out there are no chips left that are expected to have siliconprawn-grade surface quality that you could "just" package up into a suitable tray or piece of the tape or so for shipping to him, then sure. Maybe the die sorter control scripting is easy enough to be instructed to just make a tape of round-robin-picks with as many dies of each design as you'd want to allocate to this usage, from which you could later cut continuos strips of (integer multiples of) how-many-designs-there-are to have "sample sets"?
Tim 'mithro' Ansell 04/25/2026 00:47
platform.wafer.space lets you set if I'm allow to share your project publically with everyone. As well, the license agreement when submitting your project generally gives wafer.space the right to use things created from your design (IE photos, the full wafer, etc) in marketing and other purposes. If you want to keep your project super secret and have NDAs and such, then wafer.space isn't the right service for you.
Avatar
Avatar
namibj
I'm assuming this is pending clearance (to be allowed to send these off to him) given by all your customers, at least those where the GDSII is not under a license that would allow you to do such anyways (e.g. TT's Apache2)? Though it's probably easy for ya two to just pull some stock NDA template you'd have around and just ship under conditions of not doing anything with the chips that don't release clearance, at least if you don't want to have to wait with that shipment until all customers had reasonable time to opt-in to the siliconprawn. OFC if it turns out there are no chips left that are expected to have siliconprawn-grade surface quality that you could "just" package up into a suitable tray or piece of the tape or so for shipping to him, then sure. Maybe the die sorter control scripting is easy enough to be instructed to just make a tape of round-robin-picks with as many dies of each design as you'd want to allocate to this usage, from which you could later cut continuos strips of (integer multiples of) how-many-designs-there-are to have "sample sets"?
Tim 'mithro' Ansell 04/25/2026 00:47
See also https://github.com/wafer-space/ws-run1
GitHub - wafer-space/ws-run1: wafer.space GF180MCU Run 1
wafer.space GF180MCU Run 1. Contribute to wafer-space/ws-run1 development by creating an account on GitHub.
Thumbnail
Avatar
Avatar
namibj
I'm assuming this is pending clearance (to be allowed to send these off to him) given by all your customers, at least those where the GDSII is not under a license that would allow you to do such anyways (e.g. TT's Apache2)? Though it's probably easy for ya two to just pull some stock NDA template you'd have around and just ship under conditions of not doing anything with the chips that don't release clearance, at least if you don't want to have to wait with that shipment until all customers had reasonable time to opt-in to the siliconprawn. OFC if it turns out there are no chips left that are expected to have siliconprawn-grade surface quality that you could "just" package up into a suitable tray or piece of the tape or so for shipping to him, then sure. Maybe the die sorter control scripting is easy enough to be instructed to just make a tape of round-robin-picks with as many dies of each design as you'd want to allocate to this usage, from which you could later cut continuos strips of (integer multiples of) how-many-designs-there-are to have "sample sets"?
Tim 'mithro' Ansell 04/25/2026 00:48
And I also only provide free silicon to people who are sharing things under open source licenses.
Avatar
Avatar
Tim 'mithro' Ansell
platform.wafer.space lets you set if I'm allow to share your project publically with everyone. As well, the license agreement when submitting your project generally gives wafer.space the right to use things created from your design (IE photos, the full wafer, etc) in marketing and other purposes. If you want to keep your project super secret and have NDAs and such, then wafer.space isn't the right service for you.
namibj 04/25/2026 00:50
ahh fair wasn't aware there's such broad license for marketing given to you; that should cover these things I think.
Avatar
The Computer Guy 04/25/2026 00:51
I've been running into a ton of DRC problems but I see there's been issues with DRC in the PDK. I cannot tell if I have real DRC issues or if they're not valid. I've been trying to search around and have seen discussions on this topic and a few issues on the buggy DRC.
Avatar
namibj 04/25/2026 00:52
(I do have good "news" to report though, in that it does seem kinda practical to vibe code custom PCells on top of gdsfactory.)
Avatar
Avatar
namibj
I'm assuming this is pending clearance (to be allowed to send these off to him) given by all your customers, at least those where the GDSII is not under a license that would allow you to do such anyways (e.g. TT's Apache2)? Though it's probably easy for ya two to just pull some stock NDA template you'd have around and just ship under conditions of not doing anything with the chips that don't release clearance, at least if you don't want to have to wait with that shipment until all customers had reasonable time to opt-in to the siliconprawn. OFC if it turns out there are no chips left that are expected to have siliconprawn-grade surface quality that you could "just" package up into a suitable tray or piece of the tape or so for shipping to him, then sure. Maybe the die sorter control scripting is easy enough to be instructed to just make a tape of round-robin-picks with as many dies of each design as you'd want to allocate to this usage, from which you could later cut continuos strips of (integer multiples of) how-many-designs-there-are to have "sample sets"?
Tim 'mithro' Ansell 04/25/2026 00:53
Yeah, @Andrew Wingate machine is pretty flexible for doing things like that and he will continue to iterate on things before Run #2.
👍 1
Avatar
Avatar
The Computer Guy
I've been running into a ton of DRC problems but I see there's been issues with DRC in the PDK. I cannot tell if I have real DRC issues or if they're not valid. I've been trying to search around and have seen discussions on this topic and a few issues on the buggy DRC.
Tim 'mithro' Ansell 04/25/2026 00:55
@The Computer Guy - BTW There are currently a few pending new DRC rules that @Leo Moser (mole99) is working on right now.
Avatar
Avatar
Tim 'mithro' Ansell
@The Computer Guy - BTW There are currently a few pending new DRC rules that @Leo Moser (mole99) is working on right now.
The Computer Guy 04/25/2026 00:56
Great, I've been trying to get 0 DRC issues but it seems no matter what I do nothing works. Hopefully those new DRC rules fixes things.
Avatar
Avatar
namibj
(I do have good "news" to report though, in that it does seem kinda practical to vibe code custom PCells on top of gdsfactory.)
Tim 'mithro' Ansell 04/25/2026 00:56
I believe that the GDSFactory team has been working pretty hard to get AI to work with their tooling as part of their proprietary "GDSFactory+" platform.
Avatar
Avatar
The Computer Guy
Great, I've been trying to get 0 DRC issues but it seems no matter what I do nothing works. Hopefully those new DRC rules fixes things.
Tim 'mithro' Ansell 04/25/2026 00:57
I think these new DRC rules will give you more new DRC errors that you didn't see before.
Avatar
The Computer Guy 04/25/2026 00:57
Oh...
Avatar
Avatar
The Computer Guy
Great, I've been trying to get 0 DRC issues but it seems no matter what I do nothing works. Hopefully those new DRC rules fixes things.
Tim 'mithro' Ansell 04/25/2026 00:57
So you should share the DRC issues you are seeing on discord and ask for help.
Avatar
Avatar
Tim 'mithro' Ansell
So you should share the DRC issues you are seeing on discord and ask for help.
The Computer Guy 04/25/2026 00:58
Cool, I'll post something in #questions here in a bit once I can commit.
Avatar
namibj 04/25/2026 00:58
clearly not DRC-compliant yet, but "correct netlist and correct general geometry/layout-topology" (from where e.g. iteratively increasing DRC minimums from 0 to actual ones to gradually push out e.g. vias to be far enough apart from each other) is almost there (forgot to move an m1-m2 via when moving the rest of the via stack; somehow cut diffusion in the GDSII under the gates (should only happen by the actual gate itself during FEOL processing 😉 )..), so.... yeah. Good chances thus for the MCML I'm hoping to get done by the ttsky26a deadline to be easily portable to WS Run2, with mostly scripted tuning to the quite different process, but somewhat manual adaption to the different stackup.
Image attachment
Avatar
Avatar
Tim 'mithro' Ansell
I believe that the GDSFactory team has been working pretty hard to get AI to work with their tooling as part of their proprietary "GDSFactory+" platform.
namibj 04/25/2026 00:58
so far only at higher levels at least as far as I've been told
Avatar
Avatar
namibj
clearly not DRC-compliant yet, but "correct netlist and correct general geometry/layout-topology" (from where e.g. iteratively increasing DRC minimums from 0 to actual ones to gradually push out e.g. vias to be far enough apart from each other) is almost there (forgot to move an m1-m2 via when moving the rest of the via stack; somehow cut diffusion in the GDSII under the gates (should only happen by the actual gate itself during FEOL processing 😉 )..), so.... yeah. Good chances thus for the MCML I'm hoping to get done by the ttsky26a deadline to be easily portable to WS Run2, with mostly scripted tuning to the quite different process, but somewhat manual adaption to the different stackup.
Tim 'mithro' Ansell 04/25/2026 00:58
Also check out glayout by the FASoC and @Mehdi
❤️ 1
Avatar
namibj 04/25/2026 00:59
I could have scripted magic Tcl but that seems like something neither I want to write nor feel like it gives functional results if vibe-coded, unlike this which gives decently sensible geometry with around 70~80% hit rate.
Avatar
Avatar
namibj
clearly not DRC-compliant yet, but "correct netlist and correct general geometry/layout-topology" (from where e.g. iteratively increasing DRC minimums from 0 to actual ones to gradually push out e.g. vias to be far enough apart from each other) is almost there (forgot to move an m1-m2 via when moving the rest of the via stack; somehow cut diffusion in the GDSII under the gates (should only happen by the actual gate itself during FEOL processing 😉 )..), so.... yeah. Good chances thus for the MCML I'm hoping to get done by the ttsky26a deadline to be easily portable to WS Run2, with mostly scripted tuning to the quite different process, but somewhat manual adaption to the different stackup.
Mehdi 04/25/2026 00:59
Look good. Is it manual layout?
Avatar
namibj 04/25/2026 01:00
No fully vibe coded pcell
01:00
(Like, Google Jules.)
Avatar
Tim 'mithro' Ansell 04/25/2026 01:00
@namibj - I have an outdated presentation about their work at https://bit.ly/goog-analog and https://bit.ly/goog-nist - I wish @Mehdi was better at advertising his work to the community.
Google + Analog Handout - Non-confidential -- https://bit.ly/goog-a...
Analog bit.ly/goog-analog
Google + NIST Handout - 1st June 2023 - https://bit.ly/goog-nist
bit.ly/goog-nist
Avatar
namibj 04/25/2026 01:00
bottom section of an MCML ring oscillator's differential delay cell
01:01
hits like 10 GHz with decent amplitude befrore layout parasitics on sky130
👍 1
Avatar
Mehdi 04/25/2026 01:01
Cool! We have building a framework called glayout that builds libs of pcells, composite cells and blocks, in hierarchical way.
👍 1
Avatar
namibj 04/25/2026 01:02
Does it have enough flexibility/low-level to handle this kind of stuff?
Avatar
Tim 'mithro' Ansell 04/25/2026 01:02
@namibj - I would say that OpenFASoC's approach is to build "auxiliary cells" which fit into the digital place and route flow (despite being analog designs). Which makes it very easy to do like 100s of different variants.
Avatar
namibj 04/25/2026 01:02
01:02
the other parallel vibe coded branch/attempt
Avatar
Tim 'mithro' Ansell 04/25/2026 01:03
@Mehdi - Do you have a more recent presentation you could share here?
Avatar
namibj 04/25/2026 01:03
I mean these are technically digital cells.... just not CMOS logic, but rather MCML.
Avatar
Tim 'mithro' Ansell 04/25/2026 01:03
@Mehdi - My presentations are from like 2022 and you have done a huge amount of work since then.
Avatar
Mehdi 04/25/2026 01:04
Yes, I am on my phone right now. But I can share one soon
Avatar
namibj 04/25/2026 01:04
don't worry about "right now", I'm not gonna get to it before I'm done sleeping.
👍 1
Avatar
Avatar
namibj
I mean these are technically digital cells.... just not CMOS logic, but rather MCML.
Mehdi 04/25/2026 01:04
Yes, that helps.
Avatar
Tim 'mithro' Ansell 04/25/2026 01:04
@namibj - The coolest thing about OpenFASoC approach is that by making it progrmatic they have taped out the same solution on old process nodes like GF180MCU/SKY130 and more modern stuff lke GF12LP/Intel 16 with very little effort.
Avatar
Avatar
Mehdi
Yes, that helps.
namibj 04/25/2026 01:05
I sorta "just" have to make enough cell library to get a PoC done in 2 weeks 😄
Avatar
Avatar
Tim 'mithro' Ansell
@namibj - The coolest thing about OpenFASoC approach is that by making it progrmatic they have taped out the same solution on old process nodes like GF180MCU/SKY130 and more modern stuff lke GF12LP/Intel 16 with very little effort.
Tim 'mithro' Ansell 04/25/2026 01:05
All with open source tools!
Avatar
namibj 04/25/2026 01:06
Well this is not possibly gonna be the same-ish on gf180mcu; the concepts stay but the cell layout is going to change substantially from the sky130 example to gf180mcu; 45nm; fin-fet
Avatar
Tim 'mithro' Ansell 04/25/2026 01:06
https://github.com/idea-fasoc/openfasoc-tapeouts
GitHub - idea-fasoc/openfasoc-tapeouts: Tapeouts done using OpenFASOC
Tapeouts done using OpenFASOC. Contribute to idea-fasoc/openfasoc-tapeouts development by creating an account on GitHub.
Avatar
Mehdi 04/25/2026 01:06
@LuighiV can you provide more help on glayout if needed.
Avatar
namibj 04/25/2026 01:07
no idea about past-fin-fet/EUV territory, things get weird there.
Avatar
Mehdi 04/25/2026 01:07
A few papers: View article https://share.google/VupFnwveCtD8YzFdi
01:08
Reinforcement Learning-Enhanced Cloud-Based Open Source Analog Circuit Generator for Standard and Cryogenic Temperatures in 130-nm and 180-nm OpenPDKs | Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design https://share.google/Ws4S9nqpX29eiGCm0
Avatar
Avatar
Mehdi
@LuighiV can you provide more help on glayout if needed.
LuighiV 04/25/2026 01:09
Sure I can help 🙌
Avatar
Avatar
namibj
clearly not DRC-compliant yet, but "correct netlist and correct general geometry/layout-topology" (from where e.g. iteratively increasing DRC minimums from 0 to actual ones to gradually push out e.g. vias to be far enough apart from each other) is almost there (forgot to move an m1-m2 via when moving the rest of the via stack; somehow cut diffusion in the GDSII under the gates (should only happen by the actual gate itself during FEOL processing 😉 )..), so.... yeah. Good chances thus for the MCML I'm hoping to get done by the ttsky26a deadline to be easily portable to WS Run2, with mostly scripted tuning to the quite different process, but somewhat manual adaption to the different stackup.
namibj 04/25/2026 01:09
5v6 is finalizing; the auto code review has confirmed it to have fixed the glaring LVS/extraction breaking fails of [the linked is 5v5]
01:12
5v6
Image attachment
Avatar
Avatar
namibj
5v6
namibj 04/25/2026 01:12
if you're curious?
mcml_nmos_block_5_v6.gds
18.64 KB
01:15
some DRC from those vias there in the center being way too close, and the poly corners underneath not being "fat", but otherwise....
Image attachment
01:20
yeah, the DRC poly.2 about min spacing was fixable by just adding a few poly boxes; the otheres are basically via pushing though, I don't do that by hand.
Avatar
Avatar
Tim 'mithro' Ansell
I believe that the GDSFactory team has been working pretty hard to get AI to work with their tooling as part of their proprietary "GDSFactory+" platform.
Christopher 04/25/2026 01:50
The biggest hurdle I can see from an optimization perspective is a differentiable DRC engine - where appropriate. I've been looking into training a DRC surrogate for the time being
Avatar
Avatar
Christopher
The biggest hurdle I can see from an optimization perspective is a differentiable DRC engine - where appropriate. I've been looking into training a DRC surrogate for the time being
namibj 04/25/2026 02:12
DRC can't be that hard to run...
02:13
Like, as in, writing a plain DRC engine.
02:15
Just swap comparisons for ReLU and add up. Write in a language with auto diff.
Avatar
Avatar
namibj
Like, as in, writing a plain DRC engine.
Tim 'mithro' Ansell 04/25/2026 02:15
It would be easier if DRC rules came from the foundry with better descriptions and examples and unit tests
Avatar
Avatar
Tim 'mithro' Ansell
It would be easier if DRC rules came from the foundry with better descriptions and examples and unit tests
namibj 04/25/2026 02:15
Oh sure.
Avatar
Tim 'mithro' Ansell 04/25/2026 02:17
I'm 100% sure that there are plenty of wrong assumptions and (software tooling) implementation specific details in all foundries current DRC decks
Avatar
namibj 04/25/2026 02:18
Actually yeah I feel it's possible an existing DRC engine could just be transcribed to a language with auto diff support and the ReLU swap done. Gradients won't be the nicest, but what else other than comparisons that aggregate to a go/no-go Boolean do they do anyways....
Avatar
Avatar
Tim 'mithro' Ansell
I'm 100% sure that there are plenty of wrong assumptions and (software tooling) implementation specific details in all foundries current DRC decks
namibj 04/25/2026 02:18
Yeah 🙁
Avatar
Avatar
namibj
Actually yeah I feel it's possible an existing DRC engine could just be transcribed to a language with auto diff support and the ReLU swap done. Gradients won't be the nicest, but what else other than comparisons that aggregate to a go/no-go Boolean do they do anyways....
namibj 04/25/2026 02:20
(this effort is for after the sky26a deadline)
Avatar
Avatar
Christopher
The biggest hurdle I can see from an optimization perspective is a differentiable DRC engine - where appropriate. I've been looking into training a DRC surrogate for the time being
namibj 04/25/2026 02:23
Actually the optimization efforts I've been doing are not differential, they're line-search; it's hard to measure oscillator performance in spice in a way that's differentiable 🙁 There definitely is optimization work that differentiates through spice though.
Avatar
namibj 04/25/2026 02:31
(I hope to maybe get a full MCML standard library into ttsky26b; probably not gonna make it in time for WS Run 2 but some testing cells should be ready in time for that.) They are of particular interest for their combination of speed and low PDN ripple. Density is not effectively comparable for a while; likely around 20~60% though vs. regular high speed CMOS logic cells.)
Avatar
The Computer Guy 04/25/2026 03:38
Is the DRC using KLayout supposed to take a few hours?
03:38
nix ps shows the klayout command has been running for 9017.5s
Avatar
Avatar
Tim 'mithro' Ansell
I believe that the GDSFactory team has been working pretty hard to get AI to work with their tooling as part of their proprietary "GDSFactory+" platform.
Thomas Pluck 2.1 04/25/2026 05:33
Hey. Honestly whatever you're seeing via AI on electrical PDKs appears to be entirely emergent from just injesting a lot of Python and chip design lingo - we also have an embedded agent in GF+ which is even better at this, but the capabilities are just they like Python and we finally cleaned up the cells, lol.
Thomas Pluck 2.1 04/25/2026 05:49
Thomas Pluck 2.1 04/25/2026 05:50
Avatar
Thomas Pluck 2.1 04/25/2026 06:06
Things like differentiable DRC are on the cards for GDSFactory+ as a part of our differentiable everything initiative - I just paid Nitro for this lol (edited)
❤️ 1
Leo Moser (mole99) started a thread. 04/25/2026 08:15
Avatar
ml_sudo 04/25/2026 08:40
Hi!
💜 1
💯 1
Avatar
Andrew Wingate 04/25/2026 09:07
I don't think I've seen these posted. Pictures from @Tim 'mithro' Ansell and @stuart in Shenzhen with some if the first COB They are beautiful!!
Image attachment
Image attachment
Image attachment
Image attachment
Image attachment
🎉 7
🤩 2
Avatar
Lofty 04/25/2026 09:27
It's becoming a cliché but I had to try.
Image attachment
🫰 1
💜 1
Avatar
namibj 04/25/2026 13:09
Do standard cell PnR ever feel like mirroring cells for more favourable routing?
Avatar
Avatar
namibj
(this effort is for after the sky26a deadline)
namibj 04/25/2026 13:30
here I say that yet I've just let the agent run loose on the klayout codebase to write planning documentation for such refactoring 😄
Avatar
namibj 04/25/2026 14:07
ok some rules are gonna be easy to differentiable DRC; some like e.g. sky130a's via.5a: via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um aren't as easy because e.g. that one seems to only blame the via's perimeter for that rule violation, despite it actually being the surrounding geometry on m1 that is too close. Sure, if the via wasn't minimum size it could be shrunk and if m1 would suffice then it would then resolve. But yeah, needs better attribution of blame to the actual vertices that are too close. @Leo Moser (mole99) your/ @Clyde Laforge 's work on the KLayout DRC refactor, does that touch the concept of attributing DRC violations to ALL the responsible source vertices, or is it orthogonal to introduction of such a concept?
Avatar
Avatar
namibj
ok some rules are gonna be easy to differentiable DRC; some like e.g. sky130a's via.5a: via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um aren't as easy because e.g. that one seems to only blame the via's perimeter for that rule violation, despite it actually being the surrounding geometry on m1 that is too close. Sure, if the via wasn't minimum size it could be shrunk and if m1 would suffice then it would then resolve. But yeah, needs better attribution of blame to the actual vertices that are too close. @Leo Moser (mole99) your/ @Clyde Laforge 's work on the KLayout DRC refactor, does that touch the concept of attributing DRC violations to ALL the responsible source vertices, or is it orthogonal to introduction of such a concept?
namibj 04/25/2026 14:41
https://gist.github.com/namibj/92be46ba3aeff8a1758669d6342f4723
Lightweight, but limited differentiable DRC proposal for KLayout
Lightweight, but limited differentiable DRC proposal for KLayout - DRC_AUTODIFF_PLAN.md
Thumbnail
14:44
Won't work effectively for e.g. via.5a with KLayout though as that just blames the edges of the via not mentioning the metal to put/extend there. Does work for e.g. m2.2 : min. m2 spacing : 0.14um though, at least the ones that are min-distance-between-EdgePair's.
Leo Moser (mole99) started a thread. 04/25/2026 14:54
Avatar
Avatar
namibj
Do standard cell PnR ever feel like mirroring cells for more favourable routing?
RebelMike 04/25/2026 17:32
Yes I’m pretty sure the librelane flow does this - there’s a log about mirrored cells from the resizer iirc
Avatar
BreakingTaps 04/25/2026 20:28
Initial photo dump from my BTAP chip! We have a nice keyence at work, but apparently no one bought the polarizer for it 🤦‍♂️ Should be able to get some nicer stitches once we get one. Ditto to a polarizer that fits my macro camera lens. Hoping to do some de-layering but not holding my breath that I'll get usable results from that
Image attachment
Image attachment
Image attachment
Image attachment
Image attachment
Image attachment
ferrisCatOwO 1
❤️ 4
💜 2
waferspace 1
20:29
echo'ing everyone else: huge thanks to the wafer.space team! Such a cool feeling to hold chips that you've designed, really appreciate all of the team's hard work to make this possible!
Avatar
Avatar
BreakingTaps
Initial photo dump from my BTAP chip! We have a nice keyence at work, but apparently no one bought the polarizer for it 🤦‍♂️ Should be able to get some nicer stitches once we get one. Ditto to a polarizer that fits my macro camera lens. Hoping to do some de-layering but not holding my breath that I'll get usable results from that
namibj 04/25/2026 20:47
What's that golden dot pattern on the top left of the last one (the central close-up one)?
Avatar
BreakingTaps 04/25/2026 20:47
slightly out of focus dummy metal fill pattern. just the stuff that get's added to satisfy the DRC metal density rules
Avatar
namibj 04/25/2026 20:47
I guess top metal but can't understand why.
20:48
Ohh fill that explains sure.
Avatar
BreakingTaps 04/25/2026 20:49
it really obscures details elsewhere 🙁 hopefully a light lapping of the top layer will remove all the fill and help show more details
Avatar
Avatar
BreakingTaps
it really obscures details elsewhere 🙁 hopefully a light lapping of the top layer will remove all the fill and help show more details
namibj 04/25/2026 20:56
I'd expect it to fairly easily come off on a nice flat grinding surface as e.g. used by over lockers in "die lapping" (post-packaging diy back grinding for improving thermals). You probably have some of the equipment options those people recommend. I think it's just float glass plus extremely fine sandpaper or dispersion-bound lapping powder/paste (c.f. optical polishing of telescope mirrors with pitch on a negative to embed the grit in). If the surface is flat you just have to balance pressure on the die along two axis to get only rid of top metal but not lower metal across the whole chip. [Edit: I initially read it as "light tapping" and was a bit confused about your plan... I only read "lapping" after hitting send.] (edited)
Avatar
Tholin 04/25/2026 21:02
Me and my two artists have been hyperanalyzing all the die shots people have been sending to try and elevate silicon art to the next level
💯 4
Avatar
Avatar
namibj
I'd expect it to fairly easily come off on a nice flat grinding surface as e.g. used by over lockers in "die lapping" (post-packaging diy back grinding for improving thermals). You probably have some of the equipment options those people recommend. I think it's just float glass plus extremely fine sandpaper or dispersion-bound lapping powder/paste (c.f. optical polishing of telescope mirrors with pitch on a negative to embed the grit in). If the surface is flat you just have to balance pressure on the die along two axis to get only rid of top metal but not lower metal across the whole chip. [Edit: I initially read it as "light tapping" and was a bit confused about your plan... I only read "lapping" after hitting send.] (edited)
BreakingTaps 04/25/2026 21:08
hehe light tap breaking 😄 We have a surface plate at work that generally gets abused for sanding/lapping so I'm thinking to grab that + some fine diamond paper? Trying to figure out the best way to fixture it to prevent rounding/tilt though. I dont have a tripod fixture, although I guess I could DIY without much hassle? Maybe just glue 3-4 chips onto a flat piece of metal and hope it's fairly planar across all of them
Avatar
Avatar
Tholin
Me and my two artists have been hyperanalyzing all the die shots people have been sending to try and elevate silicon art to the next level
BreakingTaps 04/25/2026 21:09
I've been scrolling through the siliconprawn discord IC photos, really impressed with what some of those folks can do! amazing microscope shots
Avatar
Tholin 04/25/2026 21:11
We believe that silicon art can be more than just shapes in a single metal layer
21:12
May even go as far as abusing quantum effects since we can manufacture structures smaller than wavelengths of visible light
Avatar
BreakingTaps 04/25/2026 21:15
ah yeah, could definitely engineer the features to give you diffraction patterns that you want, rather than randomly. real structural color stuff
21:15
cool idea!
Avatar
Tholin 04/25/2026 21:16
Embedded image
21:16
Look at that green glow in-between the metal5 stripes here
21:16
I wonder what the significance of that is
👍 1
21:16
What is the spacing between them?
Avatar
BreakingTaps 04/25/2026 21:17
lemme pop it into imagej, one s. i think that might just be out-of-focus aberration blur in this case, the stitching auto-focuser algorithm was preferring to focus on the middle layers it seems
21:20
1.37um ish
Image attachment
😮 1
Avatar
Tholin 04/25/2026 21:21
Is this just the horizontal stripes of the default top-level power grid?
21:22
Embedded image
21:23
Because then, it should be closer to 1µm
21:24
Which I would like to note is twice the wavelength of green light
Avatar
BreakingTaps 04/25/2026 21:25
yeah it's just the power stripes. from this region
Image attachment
❤️ 1
😮 1
Avatar
Tholin 04/25/2026 21:26
Btw, what is the difference between the photos where its all colorful and the ones where its just shades of orange?
Avatar
BreakingTaps 04/25/2026 21:27
the orange is coaxial light, and the colorful one was something closer to ring lighting + some DIY polarizer (which didn't work particularly well)
21:28
off-center lighting definitely helps make more colors pop, i assume from the thin film interferences of different layers
21:32
my evening yesterday, trying to find a good combo of lighting and settings 😂
Image attachment
😮 1
Avatar
Avatar
BreakingTaps
hehe light tap breaking 😄 We have a surface plate at work that generally gets abused for sanding/lapping so I'm thinking to grab that + some fine diamond paper? Trying to figure out the best way to fixture it to prevent rounding/tilt though. I dont have a tripod fixture, although I guess I could DIY without much hassle? Maybe just glue 3-4 chips onto a flat piece of metal and hope it's fairly planar across all of them
namibj 04/25/2026 23:38
You're not gonna round against a flat reference if you put any proper attempt into flattening the motion-force vector to be more in-plane than plane-normal, say by sticking the chip to something as simple as a microscope slide with a dab of not-too-shear-strong (so you can shear it off later to release) glue. I'd try fairly shitty superglue for that, I'd expect to be able to release that if necessary, but you probably have a better idea. The thought is to inspect the progress and adjust tilt-bias (e.g. by shifting where exactly into the chip's backing plate you introduce the friction-generating "force") as necessary. I'd just try on one by hand tbh... the skills/nuances should be fairly close to achieving a good straight bevel or even more, a straight-and-flat back, on a "simple" wood chisel. This is top metal, not some low thin layers, the flatness we target is on the order of several lambda... and pretty sure it's not that hard to hand-lap a parallel plate glass disc to sub-lambda flatness if you have a good flat reference to just copy the surface curvature from.
Avatar
Avatar
BreakingTaps
off-center lighting definitely helps make more colors pop, i assume from the thin film interferences of different layers
namibj 04/25/2026 23:45
pretty sure for proper polarizer explotation of the "specular reflections maintain polarization, if the light source is polarized you can filter the reflections out if you adjust the angles correctly" that photographers use outdoors with sunlight against e.g. water surfaces and glass panes would want the light source to also be polarized and the polarizer angle between the source and the scope to be adjusted for the illumination angle? Might need collimated illumination to work well, I haven't gotten back to the local microscope to test that theory out on actual hardware (with 3D goggles and a collimated flashlight, and a hand-held (if it doesn't by chance screw in) DSLR polarizer on the soldering microscope).
Avatar
Avatar
Tholin
Me and my two artists have been hyperanalyzing all the die shots people have been sending to try and elevate silicon art to the next level
Tim 'mithro' Ansell 04/26/2026 00:16
Excited to see that! Any thoughts on if you could simulate the behaviour with things like that optical simulation / ray tracing tooling?
Avatar
Tholin 04/26/2026 00:17
Maybe? Ray tracing has the best chances of actually simulating the effects of different light angles accurately.
Avatar
Avatar
Tholin
Maybe? Ray tracing has the best chances of actually simulating the effects of different light angles accurately.
Tim 'mithro' Ansell 04/26/2026 00:21
Did I paste this here in the end? https://www.linkedin.com/feed/update/urn:li:activity:7443670533818204161/
| Kramer Harrison
Sign in or join now to see posts like this one and more.
Thumbnail
😮 1
Avatar
Tholin 04/26/2026 00:26
What would be cool is if we had control over layer thicknesses in gf180. I actually know someone who produced the old rainbow apple logo on a silicon die in all its colorful glory by manipulating etching depths. But they needed a lab and DIYing the process to do it.
Avatar
Avatar
Tholin
May even go as far as abusing quantum effects since we can manufacture structures smaller than wavelengths of visible light
needsadrink|woke 04/26/2026 00:41
Please don't break our fabs though 😆 us process engineers get cranky when we have to go to quality meetings because of these sorts of things lol... your best bet is probably to abuse the oxide nonuniformity caused by pattern density during CMP, but unpredictable is categorizing the result lightly 🫠 . What you're likely seeing in that 1.37um gap between lines is thicker oxide than the field due to local polish rate difference
Avatar
Tim 'mithro' Ansell 04/26/2026 00:41
I was just searching for the open source litho simulation and came across https://github.com/TorchOPC/TorchLitho - "Differentiable Computational Lithogrpahy Framework"
GitHub - TorchOPC/TorchLitho: Differentiable Computational Lithogrp...
Differentiable Computational Lithogrpahy Framework - TorchOPC/TorchLitho
Thumbnail
❤️ 1
Avatar
Avatar
needsadrink|woke
Please don't break our fabs though 😆 us process engineers get cranky when we have to go to quality meetings because of these sorts of things lol... your best bet is probably to abuse the oxide nonuniformity caused by pattern density during CMP, but unpredictable is categorizing the result lightly 🫠 . What you're likely seeing in that 1.37um gap between lines is thicker oxide than the field due to local polish rate difference
Tim 'mithro' Ansell 04/26/2026 00:42
You don't have to worry, this stuff is going to GF 😉
Avatar
Avatar
Tim 'mithro' Ansell
You don't have to worry, this stuff is going to GF 😉
needsadrink|woke 04/26/2026 00:43
I have eng peeps who work there haha, thinking of their mental health too 😁
Avatar
Tim 'mithro' Ansell 04/26/2026 00:50
Randomly ended up at https://ai4eda.github.io/
Awesome AI for EDA
This is a curated paper list of existing Artificial Intelligence (AI) for Electronic Design Automation (EDA) studies.
Avatar
Avatar
Tim 'mithro' Ansell
I was just searching for the open source litho simulation and came across https://github.com/TorchOPC/TorchLitho - "Differentiable Computational Lithogrpahy Framework"
namibj 04/26/2026 00:56
computational litho is for OPC or rather, calculating the structures from the masks, not simulating how things look under a microscope?
Avatar
Tim 'mithro' Ansell 04/26/2026 01:11
@namibj - Yes, but there were people talking about litho simulation in https://discord.com/channels/1361349522684510449/1495683592762953758 and other people here talking about Differentiable Computation stuff
Avatar
Tim 'mithro' Ansell 04/26/2026 01:35
Anyway, off to the airport again!
Avatar
Avatar
needsadrink|woke
Please don't break our fabs though 😆 us process engineers get cranky when we have to go to quality meetings because of these sorts of things lol... your best bet is probably to abuse the oxide nonuniformity caused by pattern density during CMP, but unpredictable is categorizing the result lightly 🫠 . What you're likely seeing in that 1.37um gap between lines is thicker oxide than the field due to local polish rate difference
Christopher 04/26/2026 01:40
If it passes DRC it shouldnt break the fab, right?
Avatar
needsadrink|woke 04/26/2026 02:01
hopefully not! lol
👀 1
Avatar
Brian Swetland 04/26/2026 02:45
I am so enthused watching all of this. Need to get the Great 2026 Compiler Project to a point where I'm happy with the overall progress so I can investigate possible projects for future wafer.space runs.
02:47
watching hobby/indie ASIC development starting to approach the kind of accessibility that hobby PCB production did in the early 2000s has me very excited
Avatar
Avatar
Brian Swetland
watching hobby/indie ASIC development starting to approach the kind of accessibility that hobby PCB production did in the early 2000s has me very excited
Tim 'mithro' Ansell 04/26/2026 03:01
That is exactly what I'm hoping to make happen! The first PCB I did was a "call us for a quote" and the only reason I got an answer was that my University had big orders with them and they owed my supervisor a favour or two.
👍 1
Avatar
Avatar
Christopher
If it passes DRC it shouldnt break the fab, right?
Tim 'mithro' Ansell 04/26/2026 03:02
In theory, practice and theory are the same, in practice they are not 🙂
😂 2
Avatar
Avatar
Tim 'mithro' Ansell
In theory, practice and theory are the same, in practice they are not 🙂
Christopher 04/26/2026 03:04
Perhaps what I really meant to ask was "If it passes DRC, are you contractually protected if something at the fab breaks" 😂
Avatar
Avatar
Tim 'mithro' Ansell
That is exactly what I'm hoping to make happen! The first PCB I did was a "call us for a quote" and the only reason I got an answer was that my University had big orders with them and they owed my supervisor a favour or two.
Brian Swetland 04/26/2026 03:04
yeah... compare with projects I've done in the last couple years, where it's a few tens of dollars to get 5-10 boards in 3-4 days. Just mind blowing. (edited)
Avatar
namibj 04/26/2026 03:05
along with "it's their fault for the DRC not being rigurous enough to cover their manufacturing line's requirements for process control"
👍 1
Avatar
Brian Swetland 04/26/2026 03:05
this kind of stuff makes me feel optimistic for the future, which is impressive considering how completely fucked bigtech appears to be at the moment (and working to destroy itself at a crazy pace)
Avatar
Avatar
Brian Swetland
yeah... compare with projects I've done in the last couple years, where it's a few tens of dollars to get 5-10 boards in 3-4 days. Just mind blowing. (edited)
namibj 04/26/2026 03:06
sadly pretty much the same still for HDI. They haven't figured out how to do blind/buried vias without paying human engineers several hours of labor 🙁
Avatar
Avatar
Brian Swetland
yeah... compare with projects I've done in the last couple years, where it's a few tens of dollars to get 5-10 boards in 3-4 days. Just mind blowing. (edited)
Tim 'mithro' Ansell 04/26/2026 03:06
I remember how much of a difference just OHSPark doing runs every few weeks even with it taking like ~8 weeks for stuff to turn up in Australia was.
Avatar
Brian Swetland 04/26/2026 03:07
yeah 2 week spins from OSHPark (west coast US was Easy Mode for that) was still absolutely revolutionary at the time
Avatar
Avatar
namibj
along with "it's their fault for the DRC not being rigurous enough to cover their manufacturing line's requirements for process control"
namibj 04/26/2026 03:08
That's a subset of the "DRC are there so you can be confident netlist extraction/device recognition output will correspond to system behavior", but these latter more stringent rules are far more flexible, mostly just affecting yield of the specific structures that are in violating without a blast radius as large as antenna violations.
Avatar
Avatar
Christopher
Perhaps what I really meant to ask was "If it passes DRC, are you contractually protected if something at the fab breaks" 😂
Tim 'mithro' Ansell 04/26/2026 03:08
Dunno, I'm pretty sure if you mess up their machines frequently despite DRC passing they would just start refusing all your orders.
Avatar
Christopher 04/26/2026 03:08
I would too
Avatar
Brian Swetland 04/26/2026 03:09
there are actual equipment-damaging failure modes possible?
Avatar
namibj 04/26/2026 03:09
I'd expect them to charge me for them to write DRC rules that actually hold on grounds of me being the first one daring enough to feed DRC-exploit-laden GDSII in high enough quantity.
Avatar
Tim 'mithro' Ansell 04/26/2026 03:10
No idea. I know that metal lifting off and floating around can be bad... But unclear if that hurts machines or all just your wafers... (edited)
03:11
And it's not really like we can introduce exotic contaminants with GDS file 😛
Avatar
Avatar
Brian Swetland
there are actual equipment-damaging failure modes possible?
namibj 04/26/2026 03:11
antenna violation AFAIK risks blasting chunks into the sputtering chamber and contaminating the walls; needs cleaning of the machine that is vaguely similar to like a high school classroom getting puked in: not normally needed, kinda can't be ignored without problems, technically things could progress but there will be issues downstream, and the cleaning is intense. No lasting damage to the building/facility though.
✅ 1
😆 1
Avatar
Brian Swetland 04/26/2026 03:12
I can definitely imagine failures that could damage the overall wafer and DRC to avoid that being especially important for shared shuttle runs and the like, but was unsure if it could be worse than that
Avatar
Avatar
namibj
antenna violation AFAIK risks blasting chunks into the sputtering chamber and contaminating the walls; needs cleaning of the machine that is vaguely similar to like a high school classroom getting puked in: not normally needed, kinda can't be ignored without problems, technically things could progress but there will be issues downstream, and the cleaning is intense. No lasting damage to the building/facility though.
Tim 'mithro' Ansell 04/26/2026 03:12
@needsadrink|woke - I think you just found a new analogy to use 😛
Avatar
namibj 04/26/2026 03:12
I don't know how often antenna violations cause that failure mode vs. just frying a couple gates into being very leaky
Avatar
Brian Swetland 04/26/2026 03:13
not surprising though that these very expensive manufacturing processes have very conservative pre-run checks
Avatar
namibj 04/26/2026 03:15
and well ofc density violations mess with CMP flatness and will cause fairly predictable/expected iiuc litho failures downstream from I assume out-of-focus/DoF effects? @needsadrink|woke can you share what exactly is the problem from CMP being done on uneven density, because I doubt it's the CMP itself breaking, but rather that subsequent processing takes issue with the surface flatness (lack thereof) from CMP being done on uneven density?
Avatar
needsadrink|woke 04/26/2026 03:16
well yeah its rarely a single point of failure, nonuniformities will always cause 2nd, 3rd order etc effects
Avatar
Avatar
Brian Swetland
not surprising though that these very expensive manufacturing processes have very conservative pre-run checks
namibj 04/26/2026 03:16
afaik there are negligible machine risks to DRC-illegally-narrow transistors on planar technologies (like >=45nm standard CMOS processes)
03:18
They're just gonna get increasingly varied transimpedance, to the point where it becomes essentially unusable.
Avatar
needsadrink|woke 04/26/2026 03:19
its hard to know what has the possibility of breaking without having the process flow spec to look at
Avatar
Avatar
needsadrink|woke
its hard to know what has the possibility of breaking without having the process flow spec to look at
namibj 04/26/2026 03:20
fair. I assume those documents are NDA even for these "open" PDKs, though?
Avatar
needsadrink|woke 04/26/2026 03:20
yeah, they are the secret sauce usually
Avatar
namibj 04/26/2026 03:20
figures.
Avatar
needsadrink|woke 04/26/2026 03:20
especially in full objective spec form haha... kept in safes, etc
Avatar
namibj 04/26/2026 03:21
yeah 😄
03:21
fab is just a cleanroom full of process control
03:22
(and wired+plumbed up machines, but that seems to mostly not be the big cost factor overall just to "plug them in", relative to the rest)
Avatar
needsadrink|woke 04/26/2026 03:24
yep its a nonstop futile exercise in keeping entropy at bay lol
03:27
stumbled across a linkedin post about the concept a while ago
Image attachment
Avatar
Brian Swetland 04/26/2026 03:30
that's not terribly surprising. there's an awful lot of "it's amazing anything ever works at all" in various places across a number of industries ^^
💯 1
Avatar
needsadrink|woke 04/26/2026 03:30
"constant rescue" is just the perfect way to put it. every morning is just an exercise in keeping calm as you read about the various disasters that hav transpired since you clocked out 😆
Avatar
Avatar
needsadrink|woke
"constant rescue" is just the perfect way to put it. every morning is just an exercise in keeping calm as you read about the various disasters that hav transpired since you clocked out 😆
namibj 04/26/2026 03:33
aren't they mostly pre-disasters on grounds of not yet having hit any severe yield impact, but are about to do so?
Avatar
needsadrink|woke 04/26/2026 03:37
hopefully! 😁 not always haha
Avatar
namibj 04/26/2026 03:48
sure. Anyways, I shouldn't chat too much about this while there's a 15 day deadline active.
Avatar
Avatar
namibj
I don't know how often antenna violations cause that failure mode vs. just frying a couple gates into being very leaky
Chips4Makers aka Staf Verhaegen 04/26/2026 09:38
I actually didn't hear about the former failure mode @imec; only heard about antenna just as reliability problem mainly related to CMP (chemical-mechanical polishing).
Avatar
Chips4Makers aka Staf Verhaegen 04/26/2026 09:47
Also haven't heard about machines being damaged bue to design problems; e.g. nothing that a good clean could solve. BTW, cleaning equipment was kind of standard procedure in the research fab @imec. For example there where tools that needed to get a clean each time they went from Cu-contaminated state to non-Cu-contaminated.
Avatar
namibj 04/26/2026 13:09
well yeah, but AFAIK a gf180mcu fab isn't a "research fab", but a "high throughput low cost" fab, and those expect to run their equipment with minimal disruptive maintenance until they need to disrupt it to prevent meaningful impact on yield, or if the maintenance is easy and good preventative maintenance.
Avatar
BreakingTaps 04/26/2026 15:34
i imagine being 30yrs old helps too. everything is probably bigger and more robust and less fancy if I had to guess
Avatar
Avatar
Chips4Makers aka Staf Verhaegen
Also haven't heard about machines being damaged bue to design problems; e.g. nothing that a good clean could solve. BTW, cleaning equipment was kind of standard procedure in the research fab @imec. For example there where tools that needed to get a clean each time they went from Cu-contaminated state to non-Cu-contaminated.
needsadrink|woke 04/26/2026 16:46
fault detection does go a long way to prevent completely catastrophic events for sure, but you can still get outages due to things like arcing in sputter chambers if your clear area is too high etc, or yeah liek you mentioned, materials contamination in production chambers, never fun because its never caught immediately and tends to put hundreds or thousands of wafers on ice for a review board to convene to disposition
16:48
usually its "fine" but if youre manufacturing stuff that has to conform to IATF 16949 or the like, you may end up being forced to downgrade a bunch of wafers
Avatar
namibj 04/27/2026 13:25
Are there already (conditional) plans for a Run3?
Avatar
Avatar
namibj
Are there already (conditional) plans for a Run3?
Andrew Wingate 04/27/2026 15:25
As far as I understand it, run 3 is pretty much locked in. Many of the changes we are hoping to implement from what we learned in run 1 will be implemented in run 3 to give the maximum amount of time for those to know a) what changes there are, and b) have enough time to make those changes. As far as the timeline goes, it depends on people being interested and purchasing slots, the more slots, the faster we make runs.
Avatar
Avatar
Andrew Wingate
As far as I understand it, run 3 is pretty much locked in. Many of the changes we are hoping to implement from what we learned in run 1 will be implemented in run 3 to give the maximum amount of time for those to know a) what changes there are, and b) have enough time to make those changes. As far as the timeline goes, it depends on people being interested and purchasing slots, the more slots, the faster we make runs.
namibj 04/27/2026 15:28
Any estimates regarding the deadline/heads-up that Run3 would likely spawn with?
Avatar
Avatar
namibj
Any estimates regarding the deadline/heads-up that Run3 would likely spawn with?
Andrew Wingate 04/27/2026 15:41
Not exactly. I can say that we expect to obtain the finished wafers [for run2] in Oct. and ship them as soon as we can after that. Run 3 timeline would me imminent around then. (edited)
Avatar
Avatar
Leo Moser (mole99)
The first bare dies have arrived! 🥳 All that hard work has paid off when you finally hold the chips in your hands ✨
Leo Moser (mole99) 04/27/2026 17:16
The CoB have arrived 🎉 Now I just need some PCBs, bad timing... https://discord.com/channels/1361349522684510449/1496850151950520443/1498370675914703032 (edited)
🎉 7
❤️ 1
waferspace 1
Avatar
Avatar
Leo Moser (mole99)
The CoB have arrived 🎉 Now I just need some PCBs, bad timing... https://discord.com/channels/1361349522684510449/1496850151950520443/1498370675914703032 (edited)
Tim 'mithro' Ansell 04/28/2026 05:24
Why bad timing?
Tim 'mithro' Ansell started a thread. 04/28/2026 05:26
Avatar
Tim 'mithro' Ansell 04/28/2026 06:23
If people have photos or other media they are willing to share about run #1 - could you add them to this Google Photos Album? https://photos.app.goo.gl/2vo4baXmki3fGFdb7
Embedded image
Avatar
Avatar
Tim 'mithro' Ansell
Why bad timing?
Leo Moser (mole99) 04/28/2026 06:31
Bad timing on my part, I don't have any PCBs to test the chips yet ^^
Avatar
Avatar
Leo Moser (mole99)
Bad timing on my part, I don't have any PCBs to test the chips yet ^^
Tim 'mithro' Ansell 04/28/2026 06:59
I was pondering if it was more of a "this is going to distract me from the bunch of DRC rules I need to be working on" 🙂
Avatar
Simi 04/28/2026 17:54
The CoB wire-bonded dies arrived at JKU today. They look awesome! 🙌 Unfortunately the DIP adapter board is still in production. Hopefully I can post bring-up results soon. 🙂
Image attachment
Image attachment
🎉 5
❤️ 1
Avatar
Tholin 04/28/2026 19:54
Tomorrow, I get the parts I need for my bring-up, on monday, I get the PCBs
Avatar
Avatar
Simi
The CoB wire-bonded dies arrived at JKU today. They look awesome! 🙌 Unfortunately the DIP adapter board is still in production. Hopefully I can post bring-up results soon. 🙂
stuart 04/29/2026 20:01
Amazing photos!
🙌 1
Avatar
asic destroyer 04/29/2026 20:25
Hi, does anyone have a PCB GitHub repo where I can check the connector again? I think I messed it up and want to compare it with a working reference. (edited)
Avatar
Avatar
Simi
The CoB wire-bonded dies arrived at JKU today. They look awesome! 🙌 Unfortunately the DIP adapter board is still in production. Hopefully I can post bring-up results soon. 🙂
asic destroyer 04/29/2026 20:26
Wie macht man so gute Fotos?
Avatar
Avatar
asic destroyer
Wie macht man so gute Fotos?
namibj 04/29/2026 20:55
Fettes Makro-Objektiv oder optisch gutes sauberes Mikroskop. Und gute Beleuchtung.
Avatar
Simi 04/29/2026 20:58
Cheap digital Microscope (Andonstar AD407) for around 100€ and a mobile phone camera. Try to get a good light. Honestly, I post-processed the pictures with ChatGPT. For the right picture, this worked incredibly well. For the left picture, it also worked fine. However, if you look closely, some bond wires look strange. This is due to the fact that in the original picture, the bond wires were sometimes not visible at all. 😅 (edited)
waferspace 1
🔥 1
Avatar
namibj 04/29/2026 21:01
errrrm please don't pass off AI images as photos
👆 1
Avatar
Avatar
Simi
Cheap digital Microscope (Andonstar AD407) for around 100€ and a mobile phone camera. Try to get a good light. Honestly, I post-processed the pictures with ChatGPT. For the right picture, this worked incredibly well. For the left picture, it also worked fine. However, if you look closely, some bond wires look strange. This is due to the fact that in the original picture, the bond wires were sometimes not visible at all. 😅 (edited)
asic destroyer 04/29/2026 21:03
I like the right picture best. (edited)
🙌 1
Avatar
Avatar
Simi
The CoB wire-bonded dies arrived at JKU today. They look awesome! 🙌 Unfortunately the DIP adapter board is still in production. Hopefully I can post bring-up results soon. 🙂
Andrew Wingate 04/30/2026 08:49
@Simi These images are amazing! Would you mind if we used them? pinging @kris
❤️ 1
Avatar
Avatar
Simi
The CoB wire-bonded dies arrived at JKU today. They look awesome! 🙌 Unfortunately the DIP adapter board is still in production. Hopefully I can post bring-up results soon. 🙂
Tim 'mithro' Ansell 04/30/2026 09:14
Please add these pictures to the shared photo album if you can!
Avatar
Leo Moser (mole99) 04/30/2026 09:19
I'm not too happy about the use of AI here either. I think we should try to keep photos authentic and only perform basic image post-processing (using the correct tools) if necessary.
☝️ 6
💯 3
Avatar
Tholin 04/30/2026 10:54
To anyone who has already received their COBs, did it get shipped in a box or envelope?
Avatar
Tholin 04/30/2026 11:55
Also, does this drop-down load for anyone? I’ve never seen it display anything else for years. I always have to contact customer support to change my deliveries and its becoming increasingly difficult to get through to a human.
Image attachment
Avatar
tnt 04/30/2026 11:57
Only times I ever see that working is when the first delivery failed.
Avatar
Tholin 04/30/2026 11:59
My Mouser order just failed to be delivered and it still says that. I’m trying to reschedule it to the same day as the COBs are set to arrive.
Avatar
Jorropo 04/30/2026 12:04
@Tim 'mithro' Ansell https://discord.com/channels/1361349522684510449/1361349523724570938/1499380331914989740 You can use: 05/01/2026 11:59 Friday, 01 May 2026 11:59:00 Here is what you have to send: <t:1777636740:R> <t:1777636740:F> it's <t: followed by the unix timestamp then : then a letter that changes the format (R for Relative, F for full, ...) and finally close it > (edited)
12:04
it shows a localized date
12:04
for example here is how I see my own message:
Image attachment
Avatar
Tholin 04/30/2026 12:24
It looks like next week is going to be bring-up day for me
12:25
More like bring-up weeks
12:25
Its going to take forever to get through everything
12:26
I’ve spent many hours this week preparing my C64C to receive my chips
Avatar
Thorben 04/30/2026 14:00
Bonded the first Cloneless1 dies here locally (custom pad frame) and tested them on a breadboard (always gives me some nostalgia 😅) before the real PCB arrives next week. Everything seems to work nicely 😁
Image attachment
Image attachment
💯 1
❤️ 4
🎉 2
😮 1
14:01
I'm impressed by how easily one can recognize (larger) layout features with the naked eye on those dies.
Avatar
Tholin 04/30/2026 14:02
What? Someone beat me to bonding to ceramic carrier? How?
😄 4
Avatar
Thorben 04/30/2026 14:04
Got the naked dies a week ago already. Then just had to request access to our bonding machine and here we are.
😮 1
Avatar
Tholin 04/30/2026 14:05
You have access to a bonding machine. Lucky.
14:06
I taped out a replica of the 6510 with a pad-out carefully chosen to allow bonding to a DIP-carrier. I thought I was gonna become the first to do this. Eventually.
waferspace 2
Avatar
tnt 04/30/2026 14:21
@Thorben Ball or Wedge ?
14:21
Looks like Au wire
Avatar
Thorben 04/30/2026 14:23
Wedge, and Au wire indeed.
Avatar
tnt 04/30/2026 14:25
@Tim 'mithro' Ansell I'm wondering if Au wire would help
Avatar
Avatar
tnt
@Tim 'mithro' Ansell I'm wondering if Au wire would help
Tim 'mithro' Ansell 04/30/2026 14:27
We are using AlSi wire (edited)
Avatar
tnt 04/30/2026 14:28
Oh, nm then. For some reason I thought it was Al wire.
14:31
@Tim 'mithro' Ansell Wait no, on the pictures from the bonding factory, it's "AlSi" wire.
Avatar
Tim 'mithro' Ansell 04/30/2026 14:33
Don't know how I typed Au when I meant to type Al
14:34
But I'm just generally confused I think. 😛
14:34
Al and Au are too alphabetically close
Avatar
Avatar
Thorben
Bonded the first Cloneless1 dies here locally (custom pad frame) and tested them on a breadboard (always gives me some nostalgia 😅) before the real PCB arrives next week. Everything seems to work nicely 😁
Tim 'mithro' Ansell 04/30/2026 14:35
Can you add them to the photo album at https://photos.app.goo.gl/2vo4baXmki3fGFdb7 ? (edited)
Embedded image
👍 1
Avatar
Avatar
Thorben
Bonded the first Cloneless1 dies here locally (custom pad frame) and tested them on a breadboard (always gives me some nostalgia 😅) before the real PCB arrives next week. Everything seems to work nicely 😁
Matt Venn 04/30/2026 16:41
Wow! Luxury chips! I love it!
❤️ 1
Avatar
tnt 04/30/2026 17:19
@Thorben What does the chip do btw ?
namibj started a thread. 04/30/2026 17:44
Avatar
Dory 04/30/2026 18:32
Kind of an off topic question but I assume there must be some voltnuts around here?
Avatar
Tholin 04/30/2026 18:43
There is the #off-topic channel, btw
18:43
For your off-topic needs
Avatar
Dory 04/30/2026 18:49
Facepalming rn
18:49
I am blind in more ways than I expected, thank you
Avatar
Tholin 04/30/2026 20:58
My multi-project die template/generator is complete. Just waiting for DRC to pass to be absolutely sure, and then I’ll write up docs on the weekend and push.
20:58
What?
Image attachment
20:58
Just as I say that, too....
20:59
Should’ve stayed quiet
Exported 884 message(s)
Timezone: UTC+0