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    "name": "general",
    "topic": "Welcome to [wafer.space](https://wafer.space/) - \ndocumentation at [wafer.space github](https://github.com/wafer-space) - \nbuy at [buy.wafer.space](https://buy.wafer.space) - \narchives at [discord.wafer.space](https://discord.wafer.space/)"
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      "content": "@Tim 'mithro' Ansell :  I noticed that the \"Technical specifications\" of the GF180MCU process on the wafer.space web page claim that the process has \"MIM & PIP\" capacitors.  That is not true.  A PIP capacitor (poly-insulator-poly) by definition requires two layers of poly.  There are processes out there with double poly layers (particularly good for floating-gate devices, and yes, they do make good linear capacitors).  GF180MCU is not one of them.",
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      "content": "Is anyone currently, or was able to utilize [litedram](https://github.com/enjoy-digital/litedram) for their project involving off-chip DRAMs? I'm currently working with it for a project I'm taping out here.\nSo far I got some results, but it doesn't seem to be designed for working with ASICs. Neither does litex in general.",
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      "content": "I think I thought Poly-Insulator-Poly was side-by-side?",
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      "content": "LiteX & LiteDRAM was/is definitely designed primarily for FPGAs",
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      "content": "@Tim 'mithro' Ansell :  No, you don't do poly side-by-side.  Poly is very thin and has practically no sidewall.  It's also sitting right on top of the substrate, so you'd end up with parasitic capacitance dominating.  Double poly caps are quite nice, although MiM caps still have the advantage that you can still put transistors and other components underneath them.",
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      "content": "Will fix that tomorrow, poke me if I forget",
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      "content": "I don\u2019t think I\u2019m gonna do much for this next shuttle. I want to tape out a RISC-V core with my custom SCL for sure, but only since I already have proven RTL for that. Probably a good idea to not expect another completely crammed die from me, I\u2019m afraid.\nI will, however, do some long-needed maintenance on my SCL and get some more silicon art in the pipeline.",
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      "content": "I do have ideas for custom silicon projects, but they are so big at this point, 90 days is not enough time to finish even one of them, I believe.",
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      "content": "The video from my talk at Hackware here in Singapore is up on YouTube @ https://www.youtube.com/watch?v=t6Z0_Krhshc",
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      "content": "Is there a guide for the minimum system requirements for generating gds?",
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      "content": "At the scale of complexity of a high utilization full chip",
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      "content": "I remember that @tnt had to have a fairly high end machine when he was working on pyfive",
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      "content": "Raw per core horsepower and lots of ram",
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      "content": "If I were to buy a build machine to make a chip, what kind of machine would I want?",
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      "content": "Also do we have similar hardware specs for an emulator of a similar design complexity?",
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      "content": "highest single-threaded performance possible (unfortunately). A lot of the steps are multithreaded and will take advantage of having a lot of cores, a few steps can be reasonably memory-heavy (30-60gb for a bigger design), but the bottleneck is usually DRC which has a lot of single-threaded sections. So the best single core performance you can get is most useful.\n\nI rented a \"gaming server\" from OVH with a Ryzen 9950x3d. My avg build time was 2-3hrs\n\nTim put together a cloud comparison here (was a few months ago so possibly a bit out of date): https://claude.ai/public/artifacts/44717da0-d032-4bb2-9763-87dcfbb66a8a",
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      "content": "on the upside, since most builds are bottlenecked on single core sections, you can kick off many parallel builds that each have slightly different setting tweaks when optimizing.",
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      "content": "(or use a cheaper machine for non-DRC part of the pipeline)",
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      "content": "I believe the website should be fixed now?",
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      "content": "My multi-project die contains both a RISC-V core and analog (DACs)",
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      "content": "Small correction",
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      "content": "I also E-Test data provided by GF can be found @ https://docs.google.com/spreadsheets/d/10zQF_L-KsV-n5zMISB8C67llsldodtbSALWoNdpY17Y/edit?gid=1771808804#gid=1771808804 -- anyone see anything interesting?",
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      "content": "The template completed in 4 hours on my intel Lenovo t16 with 40GB RAM",
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      "content": "Actually just generating GDS should be trivial on any system of the last 2 decades",
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      "content": "And you said at this price point there's no testing!",
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      "content": "Having a lookup table for the test names to description would be helpful to make sense of things aside from guessing and looking at standard deviations of the values for a given unit of measure",
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      "content": "yeah I guess the big thing is being able to run DRC in a reasonable amount of time without running out of RAM",
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      "content": "so it is looks like I am looking at around ~$3K  if I bought something off the shelf; ram being a big part of the cost",
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      "content": "my laptop is probably not going to cut it, only has 16GB of RAM",
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      "content": "There are data for 25 wafers, I though you had only run half a lot.",
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      "content": "Very nice to get the ETest data though. Doing a few spot check vs the PDK values, it's pretty close to typical.",
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      "content": "@Tim 'mithro' Ansell One thing that bugs me though is the name of the test \"TM5L9K\" ... I though we were using the 11K top metal thickness option. ( I rechecked https://discord.com/channels/1361349522684510449/1423053988210675852/1423076158219489300 )",
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      "content": "Something else a bit weird is the MiM cap data.  SPEC is between 1.7 fF/um^2 and 2.3 fF/um^2  but the pdk lists nominal at 1.5 fF/um^2. ( Although I guess they might be compensating for some measurement setup thing ... )",
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      "content": "There's always disk swapping :/",
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      "content": "I'd suggest trying to run the template through to completion, to benchmark. $3k sounds a bit crazy if you're doing this for the first time and haven't done any benchmarking first",
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      "content": "Even renting a cloud host for a few hours or days will be massively cheaper",
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      "content": "Well this isn't exactly the first time I tried the tools.",
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      "content": "i'd ++ the cloud rental route. The OVH server I rented was $200/month. I really only needed it for one month of intensive builds, two at the most. Unless you need/want the machine for other stuff it's hard to beat a cloud rental for short term usage",
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      "content": "I think RAM is the main thing. For a full chip 64G is definitely  needed I think.",
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      "content": "Looking at this like I am starting a company and want to see what it would cost to have basic infrastructure.",
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      "content": "What do you guys use to run the checks for the shuttles?",
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      "content": "Also, re. 22:55 in the presentation: 480 LUTs doesn\u2019t sound like a lot for an FPGA, but that is actually twice the amount of the 240 LUT MAX II CPLDs I have a big pile of because they keep coming in handy in projects (and I fit a whole DDR2 controller in one of those once!). And they would be even more useful to me if they were 5V tolerant. So, actually, I\u2019d REALLY love to get my hands on a bunch of the Fabulous FPGA for whatever 5V systems I still build sometimes.",
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      "content": "One thing to consider would be a libre silicon compute infrastructure. Timeshared remote systems for a structured development environments and infrastructure for the drc/lvs grind on the way the shuttles.",
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      "content": "You can also run the DRC checks through https://platform.wafer.space",
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      "content": "Looks like @Leo Moser (mole99) has some competition -> https://github.com/MidstallSoftware/aegis and https://news.ycombinator.com/item?id=47646472",
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      "content": "They are claiming 2880 LUT4's",
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      "content": "If compute infrastructure is what is blocking you, I'm sure we can find someone who is willing to lend you time on some hardware.",
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      "content": "Hi Tim",
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      "content": "Hi!",
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      "content": "Great to see you share the project",
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      "content": "Are you planning on taping out on run #2?",
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      "content": "Idk yet but I do want to do tapeout",
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      "content": "I'm currently doing some improvements to the tapeout workflow. I got it down from over 6 hours to just 3.",
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      "content": "Hi @The Computer Guy, impressive project! Especially hitting 2,880 LUT4's on GF180MCU using the default standard cell library.\n\nI've tried increasing the LUT count in my FPGA, but it would require simplifying the switch matrix of the tiles, which would impact the complexity of the designs that could be implemented.\n\nI'm wondering if you have tried implementing some real-world designs that make use of most of the 2,880 LUTs?",
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      "content": "Hey so I do plan on trying a RISC-V core on it at some point. Or it would be Fourth.",
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      "content": "That would make a great benchmark. Besides the blinky in your repository, have you tried implementing any other designs yet?",
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      "content": "Not yet, it's mainly blinky and the test suite",
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      "content": "@The Computer Guy / @Leo Moser (mole99) - Have you considered putting a serv core in spare space around SRAM tiles? \ud83d\ude1b",
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      "content": "No lol",
      "author": {
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      "content": "I did so in a previous chip, not exactly SERV though: https://github.com/mole99/greyhound-ihp",
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      "content": "@Leo Moser (mole99) / @The Computer Guy - You should also get a corescore.store for your parts \ud83d\ude42",
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      "content": "True! Greyhound has a core score of at least 1 \ud83d\ude00",
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      "content": "Lol, how would I do that?",
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      "content": "https://github.com/olofk/corescore?tab=readme-ov-file#quick-start",
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      "content": "Ah",
      "author": {
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      "content": "However, I think you need silicon first.",
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      "content": "I'm not too worried about Aegis Terra 1's performance since it's meant to be a starting point lol",
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      "content": "It kinda seems like it, I don't think it would be too happy with the simulator.",
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      "content": "Right now I am in the scoping process preparing a machine to do development. Since the drc can be offloaded I might be able to use an old decommissioned gaming pc for dev.",
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      "content": "OpenROAD is using 330GB of RAM out of my 512GB lol",
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      "content": "@The Computer Guy hi, I'm lofty, one of the yosys/nextpnr devs. I did have some thoughts on the FPGA architecture side of things.",
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      "content": "Oh cool",
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      "content": "I've definitely had thoughts about yosys and nextpnr being more optimized for systems like Ampere. I daily drive Arm hardware so it would be nice if yosys and nextpnr could take advantage of my 128 cores. I wish OpenROAD could as well heh.",
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      "content": "multithreading is something we're working on to one extent or another; neither codebase is ideal for such things (Yosys's RTLIL core representation is not thread-safe, and nextpnr achieves local threading by layering over the arch API)",
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      "content": "Yeah, I've seen some of the issues and code. I know in general this is hard to get multithreaded.",
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      "content": "I will ask: are you using router1 or router2?",
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      "content": "I've been using viaduct with nextpnr",
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      "content": "<https://github.com/MidstallSoftware/aegis/tree/master/nextpnr-aegis>",
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      "content": "yes. I saw.",
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      "content": "after all, I was the one who proposed viaduct :p",
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      "content": "Ah",
      "author": {
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      "content": "when nextpnr-aegis runs, does it use router1 or router2",
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      "content": "Lemme run it and see",
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      "timestamp": "2026-04-06T23:10:58.067+00:00",
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      "content": "It would be cool for the Aegis backend to be upstreamed into nextpnr so I don't have to do the overlay",
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      "content": "we are relatively flexible with accepting such architectures, but you would likely need to port your code to himbaechel instead of viaduct",
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      "content": "Ah",
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      "content": "I think I remember seeing both and wasn't sure which to use",
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      "content": "use himbaechel.",
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      "content": "Ok, after the tapeout improvements I'll do that",
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      "content": "(since the joke is likely lost: viaduct is called such because it a bridge API for small arch(itectur)es. [himbaechel](<https://de.wikipedia.org/wiki/Himb%C3%A4chel-Viadukt>) is a bridge API based on viaduct for large architectures)",
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      "content": "Gotcha",
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      "content": "Himbaechel is a better fit for Aegis?",
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      "content": "I don't see anything from nextpnr which indicates if its router1 or router2",
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      "timestamp": "2026-04-06T23:16:38.625+00:00",
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      "content": "Viaduct won't see any future improvements that Himbaechel receives from our own work on it",
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      "content": "Ah, that makes sense",
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      "content": "for the scale of your FPGA, Viaduct is *fine*, but I think you'll appreciate having to build the architecture database once at build time rather than on every run",
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      "content": "Ah",
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      "content": "Ig that's a good time to also make things a bit more streamlined. I made it where the parameters for the design is just passed in. When switching to Himbaechel, I could use the descriptor JSON for the chip.",
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      "timestamp": "2026-04-06T23:19:18.675+00:00",
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      "content": "there are messages such as [this one](<https://github.com/YosysHQ/nextpnr/blob/764c6a6696923949a043fb35ccf71f6525e9a074/common/route/router1.cc#L1282>)",
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      "content": "Ok, yeah I see that",
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      "content": "also if the router output has `|`s, it's router1, if it has `=`s, it's router2",
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      "content": "Ah, so it is router1",
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      "content": "What's the difference between router1 and router2?",
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      "content": "try running again with `--router router2`",
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      "timestamp": "2026-04-06T23:20:56.468+00:00",
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      "content": "r1, when properly tuned, produces higher Fmax results. r2 produces worse Fmax results, but requires very little tuning and runs much faster.",
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      "content": "Ah",
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      "content": "also r2 is multithreaded-ish and r1 is not.",
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      "content": "Gotcha, with r1 it did say it ran for 0.11s for the blinky example",
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      "content": "Oh, r2 did it in 0.02s",
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      "content": "<https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/018-attosoc>\nsee if you can get this one to synth. that should begin to differentiate the two.",
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      "content": "Ah",
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      "content": "also, on a personal note:\n> Existing open-source FPGA efforts either reverse-engineer proprietary architectures (Project IceStorm, Apicula) or build tooling around closed silicon (Yosys, nextpnr)\nI think it's perhaps worth pointing out Cologne Chip GateMate as a half-proprietary architecture. it's true the HDL is closed, but we're their official toolchain, and we can publish information from their confidential docs as long as it's not verbatim.",
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      "content": "e.g. [this](<https://github.com/YosysHQ/prjpeppercorn/blob/main/schematics/cpe/cpe.pdf>)",
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      "content": "Oh cool",
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      "content": "If I can get the nextpnr support upstreamed, it would be cool to do that with yosys as well. A `synth_aegis` command would be cool, it would only really need the JSON descriptor I think.",
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      "content": "you would be expected to provide tests and maintain it to some degree though",
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      "content": "Oh",
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      "content": "Fair",
      "author": {
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      "content": "nextpnr's standards for architectures are a bit lower than yosys'.",
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      "content": "I was thinking both would have high standards",
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      "content": "I think everyone, including the OpenROAD devs would love to figure out how to take advantage of many-core systems. \n\nAlmost all the existing research and effort has been focused on trying to produce the best solutions when measured by number of cpu cycles / instructions (mainly due to the perverse incentives when you license your software per CPU core) rather than solutions which might consume overall more CPU in the end but have a shorter wall run time.\n\nMost software people at Google were very interested in trying to figure out how we could do something more map-reduce style which allowed the expensive steps complete in minutes but we where never quite able to get the resources needed to do that effort when still being behind on other functionality.",
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      "content": "@The Computer Guy - BTW I would love to know more about your SERDES. Have you seen my talk @ https://bit.ly/open-pipe-talk at all?",
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      "content": "I haven't seen your talk on serdes lol",
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      "content": "Alright lol",
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      "content": "@The Computer Guy - If you are procrastinating, I have plenty of reading material (much which is out of date) at https://bit.ly/tim-silicon-2024 \n\nI have a *very* old presentation at http://bit.ly/goog-fpga-22q3 which has a bunch of your \"competition\".",
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      "content": "There was someone else on this server that was working on SERDES type things too....",
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      "content": "@The Computer Guy - This seems to be that discussion. (poke @EmbeddedKen).",
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      "content": "https://github.com/MidstallSoftware/aegis/pull/8",
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      "content": "Yeah this seems much fairer",
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      "content": "Great",
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      "content": "Gonna work on an architecture documentation while I wait for the tapeout workflow to finish",
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      "content": "speaking of multi-threading, last weekend I realized that there are some threading knobs left at 1 when running librelane/project template. most notably the resizing steps. gave me a 2-3x speedup going from 1 to 16 cores (presumably a lot of synchronization losses keeping it from linear)\n\n I also started to play around with implementing nvidia's INSTA idea (https://ieeexplore.ieee.org/document/11132858) and it was 2-5x faster although the QoR wasn't always comparable. Worked well to get to TNS = 0, but didn't really like pushing positive slack margins for some reason, probably just my bad code",
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      "content": "Oh cool, you're here lol. I remember seeing you followed me on Twitter a bit ago which was funny because that was after I saw one of your videos.",
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      "content": "hi hi! yes I was excited to see you pop into my twitter feed, folks working on silicon and fpgas are rare \ud83d\ude42 try to follow whenever a good project pops up!",
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      "content": "Awesome, yeah I've got some even cooler projects in the pipeline after Aegis",
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      "content": "Ik I'm one of the few people doing this stuff on NixOS, I'm even doing it all on Arm lol",
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      "content": "Is there a way to make OpenROAD not take 6 hours for detailed routing & placement?",
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      "content": "- Make your design less congested\n  - Decrease the density (allow more area for the same amount of logic)\n  - Decrease your target clock frequency (increase the clock period)\n  (even if you will eventually push for area or clock speed, you can relax them while you are iterating on your design to make the hardening faster)\n- Make sure you have enough RAM, otherwise you may end up using swap / virtual memory which is substantially slower",
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      "content": "Turns out apparently you can tell OpenROAD to use multiple threads, it's only been using 1 of my 128 cores",
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      "content": "- Make your design modular, harden smaller parts and use them as macros at the top level",
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      "content": "Are you calling OpenROAD directly? If you use librelane, detailed routing should already run with `DRT_THREADS` set to the number of machine threads, and many other parts of the flow are single-threaded.",
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      "content": "I know it gets mentioned a lot during talks, but what actually is the story behind PCB manufacturing becoming accessible? When I first got deep enough into EE to want to make my own PCBs, JLCPCB was already a thing, so I missed the beginning part of all that.",
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      "content": "I keep hearing there is parallels between that story and the direction open source silicon is going in, but I have no context to get it.",
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      "content": "@Tholin - I don't know if there is any official history.",
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      "content": "@Tholin - The first ever PCB that I ever got made commercially was in University and the PCB house only allowed me to submit a design because they did other work for the university. They definately had a \"Call us for a sales call and set up an account\" type setup.",
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      "content": "@Tholin - The big change was then OHS Park which was then followed by Dirty PCB. They where services which would pool together designs and then them to the PCB house and such.",
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      "content": "At that point I could get PCBs made for the same cost of shipping to Australia, the turn around time was like maybe 6 weeks however as they designs only went to the PCB house like every couple of weeks and shipping to Australia was aweful \ud83d\ude42",
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      "content": "Dirty PCB was cheaper because you didn't get things like solder mask or silk screen or anything, OHS PCB was better but more expensive. Neither group would hold your hand or help you fix DRCs or stuff. They manufactured what you sent them and if it wasn't correct it was your own fault.",
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      "content": "Then a bunch of the Chinese PCB houses like JLC, Seeed and PCB Way started offering services to the rest of the world.",
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      "content": "And that is my short story of my own experiences, don't know what is was like for others.",
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      "content": "You might be interested in this video with Tim: https://www.siliconimist.com/p/waferspace-tim-mithro-ansell",
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      "content": "It's likely (at least mildly) related to new features added to the manufacturers' software which allowed them to panelize disparate designs more easily.",
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      "content": "I still have emails from 2011 when it wasn't osh park yet and you were just emailing \"pcb-order@laen.org\" to get added to a panel and you were manually sending paying through paypal transfer ...",
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      "content": "Dang, Aegis Terra 1 is way too big from the sound of it for wafer.space. I did plan on eventually starting another family of FPGA's. Good time to do Aegis Luna 1. The Luna series is meant to be small scale while Terra is meant to be the leading series. If I do 19 x 19, 2 tracks, 2 DSP column iteration, 1 BRAM column iteration, and 1 SerDes then I fill up the die by like 80% - 90%.",
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      "content": "What kind of machine do you have? I\u2019m a little bit jealous.",
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      "content": "40 x 19",
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      "content": "It's 760 LUTs",
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      "content": "I thought the previous chip you shared with 2,880 LUTs was targeting wafer.space?",
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      "content": "I couldn't get Terra 1 to fit",
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      "content": "So Luna 1 was made",
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      "content": "Then I misunderstood. I thought you had already fitted your previous design into the wafers.space template.",
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      "content": "No because I didn't know of that until I was working on improving the tapeout",
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      "content": "Great interview @Essen . I did some work on Cirrus Logic MaverickCrunch gcc compilers about 20 years ago. I think their HQ is/was in Austin, TX.\n\nListened to the pod cast whilst driving and doing other errands.\n\nYour bfloat16 implementation and blog posts are great for someone who has a deep understanding of the software and not so much of the hardware implementation of floating point.",
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      "content": "https://youtu.be/L-QVgbdt_qg\n\nIs another gem on floating point, for anyone interested in how the Intel 8087 was designed.",
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      "content": "> [Run] Evaluating: WP_C=0.81, WP_D=0.88, WN_MAIN=1.81, WN_CC=0.42, WN_TAIL=5.51, LP_C=0.20, LP_D=0.42, LN_MAIN=0.15, LN_CC=0.15, LN_TAIL=0.15, V3=0.00                                                                                                                                                                          \n>   --> Success: Freq = 4.982 GHz, V_pp = 2.141 V\nsky130; no reactive elements; xschem (no layout parasitics accounted for yet); not really tuned yet though.\nSearch algo is ongoing at the task of figuring out the relevant area of physically possible parameter space (like, from manufacturable transistor sizes down to those that result in oscillations).",
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      "content": "Hi everyone, could people bug me about getting announcements out about Run 1 and Run 2? I've been really slack and keep getting distracted.",
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      "content": "For all you FPGA enthusiasts here, I've brought up the FPGA of Greyhound: https://www.linkedin.com/posts/leo-moser_fpga-asic-opensource-activity-7450118975205593088-17B8\n\nI'm looking forward to testing my FPGA on wafer.space run #1! \ud83d\udc4f",
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      "content": "Will anybody be going to (or presenting at ?) the Latch-Up conference in Waterloo Ontario (Canada) in a couple of weeks ?",
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      "content": "I was hoping to make it but I don't think I will end up doing so",
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      "content": "I didn't know about that conference until just now lol.",
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      "content": "Hello! I was wondering if I could get a hand with setting up my workflow to design the chip for this process? Rn I managed to get most of the template set up, but on runnng my code Yosys is throwing 130 check errors at me, and I can't find what they actually are?",
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      "content": "Did you look in the runs directory?",
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      "content": "yep, but the log just says 130 Yosys check errors found",
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      "content": "The librelane log will say that, but in the runs directory will be the actual Yosys output",
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      "content": "Not really, the step only contains a config.json and state_in.json",
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      "content": "I am very new to LibreLane so I'm not quite the best at knowing where to find stuff tho xd",
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      "content": "So many PCBs for my bring-ups...",
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      "content": "Fixed the issues I had with Yosys (I think) but now I get\n```ERROR    add_global_connections failed to make any connections for 'rst_n_pad/DVDD' to VDD.    ```",
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      "content": "For some reason it canot connect power to the rst pad huh...",
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      "content": "Weird...",
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      "content": "Started a thread.",
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      "content": "Some feedback: On the template on the github it would be neat if setting any pad count to 0 would disable the generation code for that pad type, which should be doable with an if block",
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      "content": "Bit of a bump, is this something that could be played with on a TT or similar? If it's not a decent task for a motivated beginner then it's not for me, but it would be pretty cool to learn",
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      "content": "Isn't tt much much smaller usable area? Silicon capacitors are nothing new, the PDK parasitics models should include capacitance already. I'm not sure what the mention of \"AI\" in the google doc is about",
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      "content": "there's probably some best-fit model that exists for a given capacitance, or if you can accept some other higher parasitics. The idea for trying it out on TT is to test out a few caps without going broke though heh.",
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      "content": ">  deep trench \nfrom the linked muRata datasheet.\n\nSounds like it's based on DRAM storage capacitor manufacturing technology; we don't have that in gf180mcu.",
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      "content": "TT doesn't have the structures that are used for these highly linear capacitors",
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      "content": "High aspect ratio caps are something completely different",
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      "content": "They dont use standard processes",
      "author": {
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      "content": "(Also lacking the packaging but that's just a non-selected process option (WLCSP bumping) that could probably be taken for wafer.space based on a cost tradeoff if the process had access to the deep trench capacitor structures needed.)",
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      "content": "well, look at the linked muRata datasheet first page 1st prose paragraph",
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      "content": "err, 1st body paragraph",
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      "content": "I know what you're getting at, I don't know how that's at all relevant",
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      "content": "> hese deep trench silicon capacitors have been developed with a semiconductor MOS process. They provide\n> very high reliability and capacitance stability over voltage (0.1%/V) and temperature (60 ppm/K).",
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      "content": "What does this have to do with testing capacitors on the gf process",
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      "content": "The reason these silicon capacitors are worth something on the market of passive SMD parts is because their dielectric is afaik grown silicon dioxide on a surface area enhancing trench structure.\nThat dielectric is awesome electrically.\nThat structure patterning provides suffiiciently low parasitics to be worth the cost of semiconductor patterning for a mere SMD capacitor, considering the electrical awesomness of the SiO2",
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      "content": "Yes, and they use ALD & SoI to achieve their aspect ratios, but that doesn't mean you can't test MiM caps on gf180",
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      "content": "ok buy a slot have some externally contacted quite shitty MIM caps?",
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      "content": "wafer.space doesn't give you WLCSP.",
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      "content": "Without that the packaging parasitics make these practically useless, also MIM caps are not really that good comparatively.",
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      "content": "(Use non-litho manufacturing instead....)",
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      "content": "The MIM are good... if you need on-die caps that don't eat active area and are pretty linear. Yeah.",
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      "content": "I'll hold off for someone else's opinion. Noted.",
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      "content": "@bunnie was explaining the reason silicon caps are useful is because of how thin they can be.",
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      "content": "The idea would be to build structures on all of the silicon layers, metal layers and mim layers which try to produce the highest possible capacitance.",
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      "content": "It's basically an optimization problem.",
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      "content": "Yeah, I figured part of the challenge is finding a way to do the inverse problem solving",
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      "content": "The other benefit I could see would be the ability to generate proven caps for other purposes",
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      "content": "Correct",
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      "content": "GDSFactory has a bunch of modes which have been used for silicon photonics optimization in a similar manner",
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      "content": "yeah i remember reading recently about some of these advanced packages for chiplet interconnects",
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      "content": "apparently they have trench caps in them for decoupling on the interposer",
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      "content": "and i have some of the library cells open in klayout and.... wow these look weird lol",
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      "content": "the fine metal features and huge poly just seem so bizarre",
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      "content": "i'm used to looking at poly that is like double patterned or something and is pushing litho limits and metal is enormous by comparison",
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      "content": "so seeing signal lines on M1 that are like half the size of the poly is just confusing to me lol",
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      "content": "buuut i need to not get nerdsniped too much on this until i get some chores done :p",
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      "content": "for reference if anybody is curious... this is a nand2 on UMC 180nm",
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      "content": "the chip had 3.3V compatible IOs and a 1.8V core, this particular cell is from a closeup image that I don't have any context for so unsure if in the IO area or core",
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      "content": "(i took the photo in 2014 and have no notes from it)",
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      "content": "it had a lot of custom layout so this isnt part of a standard cell",
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      "content": "very bouba",
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      "content": "no matter how kiki your layout is, after litho and etch it's gonna turn out bouba if it's a min-sized feature :p",
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      "content": "straight lines and 90 degree angles are lies perpetuated by big geometry",
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      "content": "huh.... I thought you said you're not gonna look until you get 1.8V oxide \ud83d\ude04",
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      "content": "~~embrace ring shaped ring oscillators~~",
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      "content": "I would love to get SEM imaging of various GF180MCU stuff. I think at some point I sent you some samples. I have a lot more potential samples now.",
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      "content": "@azonenberg - I'm actually talking to Lattice about getting known good die of Lattice FPGAs to offer co-packaged/wire bonded GF180MCU parts with cheap open source supported FPGAs. That might be a gateway option for exploring PCIe type things further.",
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      "content": "Interesting. But my goal here is not so much \"I want to build an asic on gf180 with pcie\" as it is pathfinding for future gen e.g. pcie gen3/4/5 on $FAB 90/65/45",
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      "content": "my realistic \"I think we can actually do this\" near term goal is to build a pcie \"gen 0.5\" PHY on gf180mcu",
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      "content": "something that is protocol compatible with gen1 but underclocked to 1/2 or 1/4 or 1/8 rate",
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      "content": "and can talk to an fpga transceiver running in sub rate mode",
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      "content": "but the idea being that the same circuit would hopefully lay the groundwork for a faster one on a more modern node",
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      "content": "so while i'm sure there might be other projects that could benefit from such a copackaged design with fpga + asic, it doesn't fill my goal here where development of the phy/protocol IP itself is the point",
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      "content": "I think i have some samples from you in my microscope food bin from skywater but i need to see what might be gf180. i've been too busy to get to them so far",
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      "content": "I'd need work's signoff to image them in their lab, alternatively if my friends across town get any of their sems working i can use theirs with no issue",
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      "content": "i can definitely image optically on my home setup on the labsmore X1",
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      "content": "I was thinking of it as a way to experiment with different parts of the system split between ASIC and FPGA side - like what I describe in https://bit.ly/open-pipe-talk",
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      "content": "Fair, that is definitely a possibility and i absolutely like the idea",
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      "content": "also for zynq-style cooperation flows",
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      "content": "Well SGMII would be nice \ud83d\ude42",
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      "content": "e.g. maybe you could run something like 16-bit APB/AHB between the asic and fpga die or something",
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      "content": "yeah i think even sgmii is going to be hard, from what i have seen from you and other folks, without the 1.8v fets. with them, it's probably doable",
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      "content": "i think 1/4 rate pcie as a sandbox is likely doable though",
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      "content": "try to build out a full flow with VCO, CDR, equalizers, etc",
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      "content": "i.e. 625 Mbps instead of 2.5 Gbps",
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      "content": "that's just barely around Fmin of xilinx GTP/GTXs",
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      "content": "I wouldn't necessarily based anything on my results ... I'm a novice analog designer \ud83d\ude05",
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      "content": "and i have a computer science degree :p",
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      "content": "Not an EE",
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      "content": "i need to learn a ton of analog to be able to actually build CMOS analog that does anything",
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      "content": "i'm reasonably confident i could build digital standard cells without a lot of trouble since i've RE'd so many of them by now",
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      "content": "one of the things i want to do soonish, and will probably be asking for some handholding at some point, is building some 3.3V cells for gf180mcu",
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      "content": "i know other people are doing it but i want to learn and i figure i should build an inverter before i build a VCO :p",
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      "content": "There are some. Tholin made a library.",
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      "content": "It's not silicon proven yet but some proto should be on WS1 run.",
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      "content": "Well, i'll look after i've done a few on my own",
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      "content": "and see how much better theirs are :p",
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      "content": "i dont want to end up unconsciously copying, i want to start from just the design rules and see what i come up with",
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      "content": "then compare after",
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      "content": "Oh ... I misread the sentence ... I thought you'd be asking for someone to do it, not that you wanted to do it yourself, my bad.",
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      "content": "no i want to do it as a learning exercise",
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      "content": "and probably put it on a TT because why not",
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      "content": "Yeah make sense.",
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      "content": "and if mine end up being good enoguh other people can use the lib, great",
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      "content": "the goal is both for practice with the tools, and to prep for eventually building a 1.8v lib if we manage to get full gf180bcd or whatever it's called one day",
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      "content": "first step is going to be figuring out what tools i still need to set up and learning how to integrate them to do simulations etc",
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      "content": "i've used yosys before but my copy is probably hopelessly out of date, i have klayout installed already for other reasons",
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      "content": "i installed the gf180mcu PDK",
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      "content": "i installed magic but the UI is so horrible i want to stick with klayout if at all possible",
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      "content": "i do not have any extraction or P&R tools installed to my knowledge",
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      "content": "or timing",
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      "content": "i assume most or all of that is part of openlane which i havent set up yet",
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      "content": "extraction is actually done with magic ...",
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      "content": "ah ok, well then i'm going to have to suck it up and deal with the pain lol",
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      "content": "klayout is starting to have basic extraction, but it's new and basic ATM, never tried it.",
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      "content": "last time i poked at it i turned off some layers and couldnt figure out how to turn them back on",
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      "content": "and nothing turned them back on",
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      "content": "but yeah basically before i do much of anything else i want to get all of the tooling installed, draw an inverter, and figure out how to simulate it. then do a ring oscillator, then some more cells",
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      "content": "I actually like magic . The learning curve is steep but after a few hours, I end up way more productive than with point and click in klayout.",
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      "content": "There was a \"cheat sheet\" around with the default keyboard short cuts.",
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      "content": "I would like to see a new tool with a UI from this century and GPU accelerated rendering one day. Maybe it'll just be a frontend around magic's geometry kernels and extractions and stuff",
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      "content": "klayout has no gpu acceleration at all afaik, magic is opengl but not as much as i would hope to see",
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      "content": "klayout gets reeeeally slow on big gds's",
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      "content": "years back i opened a TS28HPC+ GDS on it",
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      "content": "but not what i would consider acceptable performance for actually doing any kind of engineering",
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      "content": "obviously the kinds of things we're doing on gf180mcu will have much less polygons",
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      "content": "and not 50+ GB GDS's",
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      "content": "@azonenberg - I've always thought that you could load the GDS into something like the Google Maps API \ud83d\ude1b",
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      "content": "Sooo i would actually like to see something along those lines that does tile based rendering and caches a texture for each layer as a png on disk",
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      "content": "precomputing stuff so the drawing is ~instantaneous",
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      "content": "i have experienec building such stuff for GIS in years back",
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      "content": "but my long term vision for what i want to see in a next-gen layout editor/viewer is something using vulkan which seems to be the way of the future for cross platform, and the ability to use it for both rendering and compute acceleration",
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      "content": "i want GPU LVS/DRC/extractions, field solver, etc :p",
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      "content": "Grid is 5 nm, chip is 3x5 mm tha'ts one 600k x 1000k PNG per layer.",
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      "content": "no not a single image",
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      "content": "you do a pyramid like google maps",
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      "content": "max zoom is say 512 x 512 5nm pixels per tile",
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      "content": "then you'd have power of 2 or 4 reductions from that",
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      "content": "one set of tiles per layer",
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      "content": "And you don't have to render them all in advance. you can rough decimate and render low res of the whole chip, then as the user pans and zooms render things just off screen in anticipation of them coming into view soon",
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      "content": "this is what I did in a GIS app years back, we'd prefetch and decompress tiles in th edirection you were panning and zooming before they got on screen",
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      "content": "Sure but eventually you still end up with that full resolution stored on disk. Even if split.   Even if you manage to compress 100:1 that's still 500 Mbytes per layer.",
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      "content": "no popping and LOD delays like google maps has",
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      "content": "Well yes, but it can be sparse. you won't be looking at every tile all the time",
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      "content": "you can cap the cache to however many GB the user wants to allocate",
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      "content": "and re-render tiles as needed",
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      "content": "also realistically for ASIC design a couple GB of disk space is not an unreasonable ask",
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      "content": "anyway, i have way too many things on my plate already and i am not attempting to replace magic or klayout any time soon",
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      "content": "but I *am* tempted to try to make a gpu accelerated view-only GDS display tool as a PoC some time to feel out the idea",
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      "content": "and if it turns out to be something we can start porting editing functionality from the other tools into, great. if not, maybe it'll just be the asic version of gerbview",
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      "content": "There's \"THE CHIPMAP\u2122: VISUALIZING LARGE VLSI PHYSICAL DESIGN DATASETS\" by Jeff Solomon, December 2002.\n\nIt implements a mipmapping pyramid, as you described.",
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      "content": "i've worked with some heavily CLI/keyboard based tools and dont like them much",
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      "content": "i like menu/mouse driven stuff that have keyobard shortcuts for common actions but it's not the main/only way to do things",
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      "content": "Are the 3.3V devices even too bad to squeeze 2.5 GBaud out of them?",
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      "content": "I'd consider asking them about what IO buffer performance you'd get with that co-packaging so you can at least try to match it with the connected ASIC pad.\nA fairly known wire bond has far more constrained parasitics than some \"generic\" PCB trace.",
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      "content": "Are the models for gf180mcu at least decent quality, unlike the sky130 ones?",
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      "content": "No idea, never tried ...\nAnd the sky130 ones aren't all that bad, they're just not designed with subthreshold operation in mind because at the time they were made, nobody was doing that ...",
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      "content": "Any reason why I shouldn't switch to klayout for my efforts before I sit myself down to watch 6 hours of tutorial(s) in hopes of getting the hang of it without really spare time to \"just\" dabble \"playfully\" until I no longer need the manual more than once every 5 minutes?",
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      "content": "Left/right click on the smol square button with the layer draw style \"tile\" on it.",
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      "content": "Link before I wake up again in ~20 hours pls?",
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      "content": "https://github.com/iic-jku/osic-multitool/blob/main/magic-cheatsheet/magic_cheatsheet.pdf",
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      "content": "In magic I never use anything else than the `box` mode and a few time the `wiring` mode. Never use import from spice or the other mode .....",
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      "timestamp": "2026-04-20T11:44:33.736+00:00",
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      "content": "... What _is_ the mask pixel size, anyways?\nOr do they not quantize at granularity visible in e.g. standard cell design?",
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      "content": "The manufacturing grid is 5 nm ... that's all we know. The rest is details that are not public/available/specified ...",
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      "timestamp": "2026-04-20T11:45:51.388+00:00",
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      "content": "~~I think we're supposed to write more TCL and use less mouse with magic~~",
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      "content": "But different masks have different resolution, the poly mask is much finer than the implant mask for instance ... they only reserve the finer thing for stuff that needs it.",
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      "timestamp": "2026-04-20T11:47:13.164+00:00",
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      "content": "That's the \"lossless\" pixel size of handing the gds layers as bitmaps instead of their normal vector-shape-stuff?",
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      "content": "Pretty much. All coordinates need to be aligned to the grid.",
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      "content": "I know actual features will be larger, but alignment isn't bound by the same optical resolution laws :ferrisCatOwO:",
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      "content": "(only gf180mcu or is sky130 the same/do you remember the number for it?)",
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      "content": "Same grid for both.",
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      "content": "And IHP too",
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      "content": "++ the general sentiment against KLayout. Everytime I have to use it seriously it makes me angry. I know I shouldn't get mad at OSS, but it's like they looked at all the normal UI conventions and went \"Ehh, what if we just change it slightly so everything is just a bit different\". also yeah it bogs down fast under bigger designs",
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      "content": "fwiw I'll be doing imaging of my chip, but not sure if or how many cross-sections. We'll see how lazy I feel. Not sure I'm skilled enough at lapping to de-layer either. Probably need @azonenberg's magic touch for that \ud83d\ude42",
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      "content": "We got some pretty nice sky130 cross sections with some fine grit sandpaper IIRC - @digshadow - Do you remember the method we used?",
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      "content": "magic's excuse at least is \"back in my day we had to use X10, because X11 wasn't invented yet\" or something \ud83d\ude41",
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      "content": "we actually have a nice little lapping station here at work i'll probably use after hours. epoxy molds, full set of grits, water flushing etc. mostly a laziness problem haha \ud83d\ude04  i'll do at least a few, the cross-sections I did of a i486 were a huge hit on the channel a few years ago (ditto to ion etching xsections)",
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      "content": "hoping to get some 3d surface profilometry data too",
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      "content": "Have you considered trying the diamond mirror tactics on chips?\nIf they have enough layer adhesion it should be possible to cut them with a defined edge (not just sand them off with undefined edges) without delaminating it?",
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      "content": "oh that's a fun idea! I don't think my machine would have the accuracy needed, it's \"only\" +/- a few microns positioning accuracy. But I might be able to convince some diamond lathe friends to try that \ud83e\udd14",
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      "content": "will have to think about the material stack, there are some materials that diamonds don't like to cut. mostly ferrous materials so probably ok, but will need to think about the nitrides and silicides",
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      "content": "Actually I was particularly thinking towards cross-section ability, possibly of a trench/angled nature",
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      "content": "ahh I see, which wouldn't care about positioning at all. hmmmmm",
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      "content": "Well, would, but that \"only\" should suffice",
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      "content": "yah",
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      "content": "For scraping off BEOL though I'd assume supervision with just a medium-power optical microscope (NA=0.3 or around) to be plenty for controlling how much more needs to go.",
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      "content": "think so yeah. my fixturing system has a few microns of repeatability error which might cause issues if I have to pull it off the machine to check under a scope, but can probably make things work",
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      "content": "dud chips are cheap and plenty, don't be afraid to try",
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      "content": "hehe yes, I have a whole pile of wafers and chips to destroy as needed \ud83d\ude04",
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      "content": "> pull it off the machine to check under a scop\njust slide it off to the side and affix the objective such that it can look at the work site without having to release the fixture",
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      "content": "yeah was thinking something to that effect. it's a bit tricky since there's not really space to mount anything inside the machine, and you have to defeat some door interlocks if you want to run the machine with the door open and stuff hanging out. but i've done it before, just a PITA to get setup \ud83d\ude42",
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      "content": "I still have to get my handful of V2S200D soldered to try them out... they took a regular PDM asic and swapped the membrane for a probe mass.",
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      "content": "(After I've shipped the best high speed serializer I can fit into the little space on my small sky26a 1x2 tile, so in 3 weeks.)",
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      "content": "Im actually looking at doing this for training a CNN for those capacitors heh",
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      "content": "no idea. i'm gonna make it as fast as I can whenever i get to it on whatever PDK is available at that time",
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      "content": "and if i have to downclock it by a few powers of two, it'll still let me prove out the architecture, digital protocol stuff, and learn things",
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      "content": "hmmm",
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      "content": "You gonna use scripted \"cells\" for the differential high speed logic parts (I don't mean the output power stage, but rather the mux/latch/serializer)?",
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      "content": "(I don't think it's wise to hand-draw the MCML for my trials, and I haven't yet found anything vaguely represenative to learn from.)",
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      "content": "I have no experience doing that but should probably learn at some point",
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      "content": "i've never done ASIC layout at all so everything is new to me :p",
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      "content": "i've looked at a ton of other people's layout since I do silicon RE as part of $dayjob",
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      "content": "(but entirely digital focused)",
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      "content": "I didn't expect the tooling to be this.... obtuse",
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      "content": "i've done RTL design for both FPGA and ASIC",
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      "content": "and a lot of custom floorplanning for FPGA, plus working with physical designers on ASIC to do high level floorplanning and looking at the resulting GDS (in klayout because they didn't want to buy me a synopsys tool seat for some silly reason, not like they're expensive or anything :P)",
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      "content": "also, the default colors in the techfiles are so confusing to me lol",
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      "content": "or not sure if the color comes from techfile or if its klayout/magic prefs?",
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      "content": "in the RE space i'm used to drawing p diffusion as dark yellow-brown, n diffusion as green, not drawing P+ or N+ explicitly, poly as red, metal1 as dark blue, other colors for higher metal layers",
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      "content": "(Like, that's the issue..... I know I could just sit down and power through and just draw by hand or hard-code-script by hand in magic with bare rectangles on the relevant layers until I get the couple cells needed.... but there's no decent way to make that style of \"cell design\" undergo some nightly batch optimization for e.g. symmetrizing edges, favoring as much missmatch tolerance as needed for usable yield, and making sure logic levels are set so that symmetrized loads can provide their PSRR benefits.)",
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      "content": "I do expect this work to be largely portable between the gf180mcu and the sky130a processes, even if some layout arrangements have to swap due to the massive transistor size difference (yet IIUC basically same metal sizes), so... yeah.",
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      "content": "are the 3.3v fets any bigger?",
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      "content": "or are you using 5v for this?",
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      "content": "i thought the 5v fets were huge but the 3.3 were about the same size as the 1.8 just slower",
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      "content": "but i never actually looked into it",
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      "content": "or are the 3.3 still longer channels?",
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      "content": "You mean between the two processes?",
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      "content": "> Note that the minimum gate length for 3V operation is 0.5 \u00b5m.",
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      "content": "> The 5V device has minimum gate length of 0.9 \u00b5m.",
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      "content": "\"huge\" isn't the word I'd use",
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      "content": "900nm wow no wonder they chomnk",
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      "content": "but 1.8V devices are 0.15 minimum",
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      "content": "that's still quite large lol",
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      "content": "this is going to be a wierd process to design for with how \"cheap\" high density metal is compared to transistors",
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      "content": "that's to get the safe operating area up to gate fully on and 5V difference between source and drain",
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      "content": "are those specs for the thick oxide? we have two oxide thicknesses available right?",
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      "content": "or is \"3v operation\" assuming thin oxide",
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      "content": "e.g. _11V/16V NMOS FET_",
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      "content": "aiui there's 3 oxide thicknesses total on gf180 family and we only have the two thicker available on gf180mcu?",
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      "content": "there's a 1.8 oxide and a 5.5 oxide",
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      "content": "oh",
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      "content": "i thought there were two oxides and you had the choice of 1.8 and 3.3 or 3.3 and 5",
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      "content": "and gf180mcu was the latter",
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      "content": "so the 3. 3 and 5v fets are the same oxide and you just draw longer channels to get 5v vds?",
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      "content": "so vgs max is the same for either?",
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      "content": "yes",
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      "content": "Interesting, i must have misunderstood what i was reading on the pdk docs then",
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      "content": "i thought we still had two thicknesses, just that our \"thin\" was the normal 1.8v process's \"thick\"",
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      "content": "and our \"thick\" was extra-thiccc",
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      "content": "well that explains some things then",
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      "content": "i guess that means our 3.3 fets and the normal process's 3.3 fets are not the same then?",
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      "content": "or do their 3.3 use this same thick oxide?",
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      "content": "ok huh",
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      "content": "apparently only 1 gate oxide but there's also a field oxide",
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      "content": "oh sorry I thought you meant \"my\" (short-term) pdk situation",
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      "content": "sorry the numbers I just quoted were sky130a",
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      "content": "gf180mcu does have two oxide thicknesses used for different voltage devices in a single process",
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      "content": "OK so i was right",
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      "content": "(afaik only ever 2)",
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      "content": "there are 3 thicknesses available and gf180mcu has the two thicker",
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      "content": "and the 1.8v version has the thinnest plus one of the two thicker for io",
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      "content": "dunno how exactly sky130a manages to have both 1.8V devices of IIUC quite decent performance as well as (up to) 20V FETs, but oh well",
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      "content": "so how big are the 3.3 fets on gf180mcu then?",
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      "content": "and the 5",
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      "content": "i poked around there and didnt see dimensional rules for poly, got a direct link?",
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      "content": "W L",
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      "content": "ok so 280nm channel length for the 3.3 fets",
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      "content": "and looks like 500/600 for the 5v?",
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      "content": "nfet 06v0 0.3 0.6\npfet 06v0 0.3 0.5\nnfet_06v0_nvt 0.8 1.8",
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      "content": "whats the difference between _nvt and normal nfet? is that a high vt low leakage one? or higher vds max?",
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      "content": "for cascodes I think?",
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      "content": "native threshold voltage",
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      "content": "uses light P doping of wafer for the channel with no implants in the channel",
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      "content": "as you can see, it's effectively a depletion-mode nmos",
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      "content": "(i.e. gate voltages are more like a jfet than a \"normal\" mosfet in operation; it's still a mosfet though so the gate _is_ floating and isolated in both polarities)",
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      "content": "https://en.wikipedia.org/wiki/Native_transistor huh",
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      "content": "interesting. i'm used to just having lvt/svt/hvt implants",
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      "content": "just to trade leakage against speed",
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      "content": "but i know very little about anything like this which seems like what you'd use in more analog stuff",
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      "content": "apparently they're good as current sources because you can tie the gate to source and they behave as a current source",
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      "content": "(ofc in that case the absolute current isn't PT stable but it _is_ fairly V stable as it obviously should)",
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      "content": "and at times thay may have lower resistance probably due to the absurdly low threshold voltage giving insane overdrive",
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      "content": "You've seen some nmos cascodes before, right?",
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      "content": "i've heard the term and have probably seen them but cant remember specifics",
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      "content": "the vast majority of what i do is just standard cell logic",
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      "content": "if the top one has convenient threshold you can apparently tie it's gate to the bottom one's gate? they say, calling that \"self-cascode\"...  weird anyways; but yeah, should be easier to bias as you can tie it off to ground",
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      "content": "@Tim 'mithro' Ansell btw looking at the wafer photos it looks like a grid of normal sized dies, then short and skinny on one side and tall and skinny on the other",
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      "content": "then there's an ultra small spot in the corner",
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      "content": "i didn't see that ultra small spot as an orderable option, is that foundry test or your personal projects or what?",
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      "content": "Double Secret 0.5 x 0.5 Die",
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      "content": "(or is that tinytapeout lol)",
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      "content": "!",
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      "content": "Are natives supported on this process? I worked with some other fab and they had to be special requested",
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      "content": "I guess it\u2019s not orderable because there\u2019s only one of them - it basically exists as a consequence of the half slots existing. The usable area is similar to the largest design you can put on Tiny Tapeout.\n\nOn run 1 that has my TinyQV SoC in it as a test. I\u2019m not sure if it\u2019ll actually get bonded though as it would require a different setup just for that one slot.",
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      "content": "In wsrun #2, there are actually three quarter slots, as we're adding one more horizontal cut. But yes, Tim wanted to keep those for other purposes.",
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      "content": "You can compare to https://github.com/wafer-space/ws-run1",
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      "content": "I think @Leo Moser (mole99) or @Tim Edwards might know...",
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      "content": "Also https://mithro.github.io/gf180mcu-project-template/",
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      "content": "I have never seen this before",
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      "content": "@Tholin - That is weird it says \"1. Shipper or Importer must provide a completed Commercial Invoice.\" but there was a completed Commercial Invoice uploaded to the electronic documentation and included in the fedex pouch.",
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      "content": "Heh, I also got FedEx import trouble this morning ( unrelated shipment ), they're asking for 3 times more than I was expecting as import fee ...",
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      "content": "I can even view the invoice. But I clicked the button and all they actually wanted was for me to agree to accept any additional fees and import charges that might come up. I just had to click a checkbox.",
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      "content": "It may be a while until I have my dies. Fedex is extremely unaccommodating to people who are never home during their delivery times its always a days-long back and forth that usually ends in me having to waste a PTO day just to be home for the delivery.",
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      "content": "Yeaaah FedEx ain't the best. They sent me a letter to my house threatening legal action because I didn't pay 24\u20ac... Turns out I paid it, they just rejected it without giving any reasons and never told me to resend it... Fun...",
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      "content": "NAtional post telling me they would deliver a package after the weekend because I \"wasn't home\" (I watched the mailman take a smoke break in front of my house and then leave as I got the message)",
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      "content": "Longer-term the economy of actually specifically such a \"high voltage\" capable process with low per-die cost makes me want to go for my \"MVDC-tamer\" project again, getting back into it around next year it seems (looks at schedule of active projects).\nIt's a switched capacitor converter around 13.56 MHz (or half/double; for interference mitigation reasons) with a central FPGA brain and optically isolated floating drivers that yeet out digital pre-distortion waveforms to an expected class-B \"vaguely linear PA\" that then actually wobbles the gate of a 10s of mm\u00b2 WBG \"power switch\"-class transistor.\n\nThe power switches are depending on native voltage rating series-connected for extra blocking voltage which necessitates extremely precise coordinated switching.\nPrevious best opportunity was an ice40 up5k married to a Parallax Propeller 2 for a few (3~8 depending on finer details) local power switch dies undergoing individual waveforms and supervision.\n\n(Propeller 2 GPIOs have 3ns 8bit DACs at 123.75 Ohm (@3.3 V full-swing; with a resistive load to GND that gives nice 75 Ohm @2V) in each one as well as a first order Delta sigma modulator able to have it's own bitstream mirrored by a nearby GPIO; the idea was for the ice40 to take the raw bitstream and extract information on real gate voltage waveform by reconstructing the harmonics individually, and helping the processor update it's wavetable.)\n\nBut a P2 is like 12$ in quantity plus the up5k and importantly not yet including the analog PA. [It has 64 GPIOs and 512 kiB of shared RAM plus 512x 32bit registers plus 2 kiB core-local addressed ram (used e.g. for ~~DMA~~Streamer to feed the DACs) with 8 cores. Clocks are RP2350 tier, it's 130nm on-semi. Ofc that's fairly overkill for just feeding a gate driver and measuring the gate waveform to adjust things.]\n\nI know the sky130 process allows on-die photodiodes; if that's also on gf180mcu the optical receiver could also be on-die.",
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      "content": "Probably the most relevant aspect to using wafer.space ASIC would be if they could be less thick, I guess.",
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      "content": "The first bare dies have arrived! \ud83e\udd73\n\nAll that hard work has paid off when you finally hold the chips in your hands \u2728",
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      "content": "The die people just received are ~250um thick.",
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      "content": "ohhhh yeah that would be fine",
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      "content": "Arrived! \ud83e\udd73\ud83c\udf89  It\u2019s so exciting to see the actual dies. Thanks everyone at wafer.space and everyone involved for making that possible \ud83d\ude0a\n\nhttps://github.com/meiniKi/gf180mcu-fazyrv-hachure\n\nShuttle ID: **G801**\nCode: **CAFE**\n\nCan\u2019t wait to make some more close up photos under a better microscope and bring up the chip \ud83d\ude00\ud83e\udd1e",
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      "content": "I will get home in two hours. I know my dies and a microscope I impulse-purchased are waiting for me there.",
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      "content": "Stay tuned!",
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      "content": "Please share your project ID and links to your project on GitHub with things like photos so that we know what we are looking at! \ud83d\ude42",
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      "content": "Added. Thanks for the hint \ud83d\ude0a",
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      "content": "Bed time for me, hope to wake up to more exciting photos and reports \ud83d\ude42",
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      "content": "Awesome to see",
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      "content": "y'all are making it very hard for me to focus on $dayjob stuff and not drop everything to start playing with layout for one of my projects :p",
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      "content": "It looks like mine (TQVA/TQVB/TQVC) have successfully been delivered to my office, but I'm away until 12th May so it'll be a while before I see them!",
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      "content": "Does this look like the pad ring is technically excessively wide, as only the immediate surroundings of the silvery pads \"need\" to be reserved?\nLike, sure, that gives space for the IO transistors associated with that pad, but that's the only \"necessity\", or not?",
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      "content": "It is said somewhere on the docs that using a custom pad you can get some extra usable area",
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      "content": "Yeah I mean there's ESD structures and such too. but yeah if you did custom you could probably steal a bit of additional space",
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      "content": "But it doesnt look unreasonable from what I have seen on other 180nm nodes",
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      "content": "see this (somewhat dirty but it was the first photo I had handy Xilinx XC2C32A on UMC 180nm",
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      "content": "this is a smaller die so the padring dominates more",
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      "content": "or the XC2C384 which is... i dont have measurements off the top of my head but probably a bit taller and ~twice as wide as a waferspace tile?",
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      "content": "On most of these older nodes with less metal layers, inboard of the pad itself it's common to have a set of large multilayer metal rings for vccio, vcore, and ground. And that does eat area, so might as well put your esd diodes and pad drivers and such on the lower layers underneath",
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      "content": "Huh that pre check repo on GH seems to do DRC better than running it through KLayout for GF180MCU. Hopefully I can get the DRC to pass this week.",
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      "content": "Something happened there",
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      "content": "First round dies arrived for MOSbius chip. Thanks @Tim 'mithro' Ansell @Andrew Wingate \n\nSome dies are off the grid",
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      "content": "If anybody wants to send me dies to image, I can run them on my Labsmore X1 CNC optical microscope at 20x easily",
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      "content": "If I get to upload the images to siliconprawn i'll do it for free, just send me a prepaid return shipping label if you want the silicon back",
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      "content": "You just need one die? Or two or three, in case something goes wrong?",
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      "content": "I only need one, and these are big/thick enough I do not anticipate problems. If you want to send a few for insurance, that's fine though",
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      "content": "Just to avoid a second shipment in case I drop one or chip a corner with tweezers or something",
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      "content": "Alright. Do I have to ship it far from here in the EU?",
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      "content": "I'm in the US but postage for something that small/light will probably not be too bad",
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      "timestamp": "2026-04-23T21:55:17.304+00:00",
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      "content": "actually pretty bad because you have to go for full fedex-class shipment unless it changed in the past few months again; reason being the mandate for DDP shipping.\n\nErr, apparently private gifts up to 100$ are allowed. 16 EUR uninsured; 26.5 EUR insured, from Germany via DHL; delivery should be through USPS.",
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      "content": "yeah i would expect post office, if you shipped as commercial samples or gifts, since no money is changing hands, would be the cheapest option",
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      "content": "Huh I would just send it as a padded letter. If they're within dimensions they should not be more than 5\u20ac",
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      "content": "yeah thats what I was assuming you would do",
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      "content": "padded bubble mailer",
      "author": {
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      "content": "And they also would not need to be declared afaik",
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      "content": "not a box",
      "author": {
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      "timestamp": "2026-04-23T22:02:42.693+00:00",
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      "content": "probably needs a CN22 but doesn't need to say more than e.g. \u00abgift, semiconductor sample\u00bb and some realistic sounding value",
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      "content": "yeah, decalre it as $4 or $7 or whatever the per die cost is",
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      "content": "that should easily fit under the gift limit",
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      "timestamp": "2026-04-23T22:03:41.274+00:00",
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      "content": "Your country still allows goods in international letters?",
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      "content": "Yeah lol",
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      "content": "I used to ship stickers that way",
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      "content": "Germany ceased in like 2018 or so",
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      "content": "As long as it's within parameters it counts as mail, and therefore there's no legal need to declare it or any way to have it inspected unless they feta you have ricin inside or similar biohazards/radioactive samples/flammable materials",
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      "content": "If it's not in the illegal items list and it fits, a post stamp will get the job done",
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      "content": "ehhhh that's not true for international",
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      "content": "because you do need customs declaration if it's goods",
      "author": {
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      "content": "(this may well be \"gift\", but it's still declaration)",
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      "content": "CN22 is the declaration sticker you can put on small padded envelopes",
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      "content": "There are few exceptions to that outside of customs unions.\nThe issue outbound from Germany e.g. is that you can't send mere letters with customs declaration on them.",
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      "content": "The packaging literally doesn't matter beyond that some thicker parcel classes (not the small 2kg class ones I'm referring to here) mandate hard boxes to ship without surcharge; the small class allows envelope class packaging.",
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      "content": "In years past I have definitely sent ordinary postal envelopes from the US in envelopes with a customs form that covered almost the whole thing",
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      "content": "Oh you could in the past from Germany too",
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    {
      "id": "1496996114375643227",
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      "timestamp": "2026-04-23T22:08:06.51+00:00",
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      "content": "but it was allowed and not absurdly priced, single digit USD postage",
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      "content": "i cant remember how recently i last did it",
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      "content": "They no longer allow that with just a 1.25 EUR (20g)/1.8 EUR (50g)/3.3 EUR (500g)/6.5 EUR (1000g) stamp value though.",
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      "content": "I don't know if the US has ceased outbound letters from having customs declarations",
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      "content": "Alright. Lemme know where to send it to and I\u2019ll see about it tomorrow.",
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      "content": "yeah the only customs changes I *know* about in the US the last few years were inbound",
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      "content": "as i buy a lot more stuff from overseas than the other way around",
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      "content": "hmm, I think this is what we're all talking about, DHL is just charging more for it than other countries:",
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      "content": "also, azonenberg, it's REALLY difficult to get a return stamp from the US",
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      "content": "yeah that's the small parcel",
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      "content": "in norway, roughly the same dimensions costs me half of that",
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      "content": "If the shipment is that expensive it's probably better if the sample makes a one-way trip",
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      "content": "especially if these are from the early \"roughly handled you don't want to use these for real\" test batch",
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      "content": "yeah",
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      "content": "though the other direction would be whatever USPS charges, if they still allow letters it'd be best to paypal you that return postage because usps does not sell that to foreigners",
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      "content": "well, people in foreign",
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      "content": "that said, for microscoping it, you could argue it's a \"document\" given that personally taken pictures (not commercial prints of works with royalties) are also very much \"documents\".\nWorst case they take the one chip and eat it.\nSend registered mail mayhaps still under 10 EUR.",
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      "content": "\u00abmicrofiche\u00bb \ud83d\ude42",
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      "content": "well, yeah",
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      "content": "FYI - I was planning to send you and a few other people a set of die with one or two samples from every project.",
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      "content": "Oh. I guess that solves that",
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      "content": "That is part of the reason I want people to get back 1,000 parts even if they think they only need like 20. With that many you can thrown a few in an envelope and if it gets lost, who cares?",
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      "content": "I'm still catching up with all the activity from last night! Great to see everyone is getting chips and such.",
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      "content": "I would love someone to explore on-die photo diodes on GF180MCU. I don't think they are supported in any way by default but I'm sure people could find ways to make /something/ work.",
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      "content": "Great to hear! \ud83d\ude1b",
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      "content": "well, how hard can it be \ud83d\ude04",
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      "content": "take the approach/tactics from sky130's photodiode pcell, port to gf180mcu?",
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      "content": "I can probably do some characterization if someone sends me a sample, i have a spectrometer i could measure various light sources against",
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      "content": "makes sense",
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      "content": "related: @Tim 'mithro' Ansell what percentage of the overall order cost is the mask set vs the wafer lot?",
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      "content": "like, hypothetically if someone wanted more dies after the first order and was OK with getting everyone else's projects manufactured in higher volume too",
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      "content": "how much would you save doing a second wafer lot on the same mask set",
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      "content": "a lot for Run1; less lot for Run2 \ud83d\ude04",
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      "content": "do you happen to have any understanding of their design? There's probably some friendly Run2 users with some spare space that could fit such structures.",
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      "content": "Don't know if this made it here -> https://www.linkedin.com/feed/update/urn:li:activity:7443670533818204161/ -- Would love to see if someone could figure out how to simulate the patterns we see from things like gf180mcu silicon top layers....",
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      "content": "luxrender should probably be able to handle it, I guess.\nMight struggle with lateral diffractive structures though, but those aren't as much of an issue on gf180 as with smaller ones.",
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      "content": "(progress on MCML P-Cells is going decently; next step is (after sleep) sit down and figure out how I want the routing to be organized, and then go and set that up. This obviously isn't DRC-compliant.\n\nThere is no good reason why those resulting P-Cells shouldn't quite directly translate to gf180mcu, though.\nBiggest issue is likely metal layer starvation with that process, though; higher routing density relative to transistor channels might offer opportunities to collapse two of the local routing layers I'll plan to use, though.\n\nWithout parasitics this buffer, well, two of this plus some P-MOS loads, simulated to 10.332 GHz @ 646 mV differential peak-peak (so 323 mV single-ended swing, well in excess of the required 200 mV for good action from downstream gates).\nWhen I have routing finished I'll see about resuming the optimizer loop with parasitics extraction.)",
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      "content": "About 60% to 80%  is the mask cost.",
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      "content": "honeslty i'm surprised its not like 90% lol",
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      "content": "masks are expensive",
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      "content": "i guess not so much on 180",
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      "content": "from what i've heard especially on newer nodes when you order a mask set you practically get the first wafer lot free :p",
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      "content": "i mean you pay for it but the cost is negligible compared to the masks",
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      "content": "@azonenberg - I'm buying 25 or 50 wafers",
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      "content": "yeah i was mostly just curious, i dont actually plan to mass produce anything on gf180mcu any time soon",
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      "content": "one batch would be plenty for all of my near term needs",
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      "content": "G801CHES.\n\n(It's a nightmare to take photos of these...)",
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      "content": "pol filter to cancel specular reflections of the cover tape?\n\"Take one out and stick it to a base that can be handled and have/provision a lid to close over it when not actively imaging\"? E.g. say microscope slide and some 3d-printed lid, possibly based on another microscope slide if it should be see-through?",
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      "content": "first I would need access to a microscope.",
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      "content": "Neither of those are microscope-required.",
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      "content": "I'm assuming this is pending clearance (to be allowed to send these off to him) given by all your customers, at least those where the GDSII is not under a license that would allow you to do such anyways (e.g. TT's Apache2)?\nThough it's probably easy for ya two to just pull some stock NDA template you'd have around and just ship under conditions of not doing anything with the chips that don't release clearance, at least if you don't want to have to wait with that shipment until all customers had reasonable time to opt-in to the siliconprawn.\n\nOFC if it turns out there are no chips left that are expected to have siliconprawn-grade surface quality that you could \"just\" package up into a suitable tray or piece of the tape or so for shipping to him, then sure.\n\nMaybe the die sorter control scripting is easy enough to be instructed to just make a tape of round-robin-picks with as many dies of each design as you'd want to allocate to this usage, from which you could later cut continuos strips of (integer multiples of) how-many-designs-there-are to have \"sample sets\"?",
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      "content": "Yeap! I mean one way to think about it is that I charge $7k USD per customer and I can have ~40 customers, so my costs must be under 40*$7k == $280k USD",
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      "content": "platform.wafer.space lets you set if I'm allow to share your project publically with everyone.\n\nAs well, the license agreement when submitting your project generally gives wafer.space the right to use things created from your design (IE photos, the full wafer, etc) in marketing and other purposes.\n\nIf you want to keep your project super secret and have NDAs and such, then wafer.space isn't the right service for you.",
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      "content": "See also https://github.com/wafer-space/ws-run1",
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      "content": "And I also only provide free silicon to people who are sharing things under open source licenses.",
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      "content": "ahh fair wasn't aware there's such broad license for marketing given to you; that should cover these things I think.",
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      "content": "I've been running into a ton of DRC problems but I see there's been issues with DRC in the PDK. I cannot tell if I have real DRC issues or if they're not valid. I've been trying to search around and have seen discussions on this topic and a few issues on the buggy DRC.",
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      "content": "(I do have good \"news\" to report though, in that it does seem kinda practical to vibe code custom PCells on top of gdsfactory.)",
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      "content": "Yeah, @Andrew Wingate machine is pretty flexible for doing things like that and he will continue to iterate on things before Run #2.",
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      "content": "@The Computer Guy - BTW There are currently a few pending new DRC rules that @Leo Moser (mole99) is working on right now.",
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      "content": "Great, I've been trying to get 0 DRC issues but it seems no matter what I do nothing works. Hopefully those new DRC rules fixes things.",
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      "content": "I ***believe*** that the GDSFactory team has been working pretty hard to get AI to work with their tooling as part of their proprietary \"GDSFactory+\" platform.",
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      "content": "I think these new DRC rules will give you more new DRC errors that you didn't see before.",
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      "content": "Oh...",
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      "content": "So you should share the DRC issues you are seeing on discord and ask for help.",
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      "content": "Cool, I'll post something in #questions here in a bit once I can commit.",
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      "content": "clearly not DRC-compliant yet, but \"correct netlist and correct general geometry/layout-topology\" (from where e.g. iteratively increasing DRC minimums from 0 to actual ones to gradually push out e.g. vias to be far enough apart from each other) is almost there (forgot to move an m1-m2 via when moving the rest of the via stack; somehow cut diffusion in the GDSII under the gates (should only happen by the actual gate itself during FEOL processing \ud83d\ude09 )..), so.... yeah.\n\nGood chances thus for the MCML I'm hoping to get done by the ttsky26a deadline to be easily portable to WS Run2, with mostly scripted tuning to the quite different process, but somewhat manual adaption to the different stackup.",
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      "content": "so far only at higher levels at least as far as I've been told",
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      "content": "Also check out glayout by the FASoC and @Mehdi",
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      "content": "I could have scripted magic Tcl but that seems like something neither I want to write nor feel like it gives functional results if vibe-coded, unlike this which gives decently sensible geometry with around 70~80% hit rate.",
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      "content": "Look good. Is it manual layout?",
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      "content": "No fully vibe coded pcell",
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      "content": "(Like, Google Jules.)",
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      "content": "@namibj - I have an outdated presentation about their work at https://bit.ly/goog-analog and https://bit.ly/goog-nist - I wish @Mehdi was better at advertising his work to the community.",
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      "content": "bottom section of an MCML ring oscillator's differential delay cell",
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      "content": "hits like 10 GHz with decent amplitude befrore layout parasitics on sky130",
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      "content": "Cool! We have building a framework called glayout that builds libs of pcells, composite cells and blocks, in hierarchical way.",
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      "content": "Does it have enough flexibility/low-level to handle this kind of stuff?",
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      "content": "@namibj - I would say that OpenFASoC's approach is to build \"auxiliary cells\" which fit into the digital place and route flow (despite being analog designs). Which makes it very easy to do like 100s of different variants.",
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      "content": "the other parallel vibe coded branch/attempt",
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      "content": "@Mehdi - Do you have a more recent presentation you could share here?",
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      "content": "I mean these are technically digital cells.... just not CMOS logic, but rather MCML.",
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      "content": "@Mehdi - My presentations are from like 2022 and you have done a huge amount of work since then.",
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      "content": "Yes, I am on my phone right now. But I can share one soon",
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      "content": "don't worry about \"right now\", I'm not gonna get to it before I'm done sleeping.",
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      "content": "Yes, that helps.",
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      "content": "@namibj - The coolest thing about OpenFASoC approach is that by making it progrmatic they have taped out the same solution on old process nodes like GF180MCU/SKY130 and more modern stuff lke GF12LP/Intel 16 with very little effort.",
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      "content": "I sorta \"just\" have to make enough cell library to get a PoC done in 2 weeks \ud83d\ude04",
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      "content": "All with open source tools!",
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      "content": "Well this is not possibly gonna be the same-ish on gf180mcu; the concepts stay but the cell layout is going to change substantially from the sky130 example to gf180mcu; 45nm; fin-fet",
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      "content": "no idea about past-fin-fet/EUV territory, things get weird there.",
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      "content": "Reinforcement Learning-Enhanced Cloud-Based Open Source Analog Circuit Generator for Standard and Cryogenic Temperatures in 130-nm and 180-nm OpenPDKs | Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design https://share.google/Ws4S9nqpX29eiGCm0",
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      "content": "Sure I can help \ud83d\ude4c",
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      "content": "5v6 is finalizing; the auto code review has confirmed it to have fixed the glaring LVS/extraction breaking fails of [the linked is 5v5]",
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      "content": "if you're curious?",
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      "content": "some DRC from those vias there in the center being way too close, and the poly corners underneath not being \"fat\", but otherwise....",
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      "content": "yeah, the DRC `poly.2` about min spacing was fixable by just adding a few poly boxes; the otheres are basically via pushing though, I don't do that by hand.",
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      "content": "The biggest hurdle I can see from an optimization perspective is a differentiable DRC engine - where appropriate. I've been looking into training a DRC surrogate for the time being",
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      "content": "DRC can't be that hard to run...",
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      "content": "Like, as in, writing a plain DRC engine.",
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      "content": "Just swap comparisons for ReLU and add up. \n\nWrite in a language with auto diff.",
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      "content": "It would be easier if DRC rules came from the foundry with better descriptions and examples and unit tests",
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      "content": "Oh sure.",
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      "content": "I'm 100% sure that there are plenty of wrong assumptions and (software tooling) implementation specific details in all foundries current DRC decks",
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      "content": "Actually yeah I feel it's possible an existing DRC engine could just be transcribed to a language with auto diff support and the ReLU swap done.\n\nGradients won't be the nicest, but what else other than comparisons that aggregate to a go/no-go Boolean do they do anyways....",
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      "content": "Yeah \ud83d\ude41",
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      "content": "(this effort is for after the sky26a deadline)",
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      "content": "Actually the optimization efforts I've been doing are not differential, they're line-search; it's hard to measure oscillator performance in spice in a way that's differentiable \ud83d\ude41\n\nThere definitely is optimization work that differentiates through spice though.",
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      "content": "(I hope to maybe get a full MCML standard library into ttsky26b; probably not gonna make it in time for WS Run 2 but some testing cells should be ready in time for that.)\nThey are of particular interest for their combination of speed and low PDN ripple. Density is not effectively comparable for a while; likely around 20~60% though vs. regular high speed CMOS logic cells.)",
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      "content": "Is the DRC using KLayout supposed to take a few hours?",
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      "content": "`nix ps` shows the klayout command has been running for 9017.5s",
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      "content": "Hey. Honestly whatever you're seeing via AI on electrical PDKs appears to be entirely emergent from just injesting a lot of Python and chip design lingo - we also have an embedded agent in GF+ which is even better at this, but the capabilities are just they like Python and we finally cleaned up the cells, lol.",
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      "content": "Things like differentiable DRC are on the cards for GDSFactory+ as a part of our differentiable everything initiative - I just paid Nitro for this lol",
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      "content": "here I say that yet I've just let the agent run loose on the klayout codebase to write planning documentation for such refactoring \ud83d\ude04",
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      "content": "ok some rules are gonna be easy to differentiable DRC; some like e.g. sky130a's `via.5a`: `via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um` aren't as easy because e.g. that one seems to only blame the via's perimeter for that rule violation, despite it actually being the surrounding geometry on m1 that is too close. Sure, if the via wasn't minimum size it could be shrunk and if m1 would suffice then it would then resolve.\nBut yeah, needs better attribution of blame to the actual vertices that are too close.\n\n@Leo Moser (mole99) your/ @Clyde Laforge 's work on the KLayout DRC refactor, does that touch the concept of attributing DRC violations to ALL the responsible source vertices, or is it orthogonal to introduction of such a concept?",
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      "content": "Won't work effectively for e.g. `via.5a` with KLayout though as that just blames the edges of the via not mentioning the metal to put/extend there.\nDoes work for e.g. `m2.2 : min. m2 spacing : 0.14um` though, at least the ones that are min-distance-between-`EdgePair`'s.",
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      "content": "Yes I\u2019m pretty sure the librelane flow does this - there\u2019s a log about mirrored cells from the resizer iirc",
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      "content": "Initial photo dump from my BTAP chip! \n\nWe have a nice keyence at work, but apparently no one bought the polarizer for it \ud83e\udd26\u200d\u2642\ufe0f  Should be able to get some nicer stitches once we get one. Ditto to a polarizer that fits my macro camera lens. Hoping to do some de-layering but not holding my breath that I'll get usable results from that",
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      "content": "echo'ing everyone else: huge thanks to the wafer.space team! Such a cool feeling to hold chips that you've designed, really appreciate all of the team's hard work to make this possible!",
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      "content": "What's that golden dot pattern on the top left of the last one (the central close-up one)?",
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      "content": "slightly out of focus dummy metal fill pattern. just the stuff that get's added to satisfy the DRC metal density rules",
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      "content": "I guess top metal but can't understand why.",
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      "content": "Ohh fill that explains sure.",
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      "content": "it really obscures details elsewhere \ud83d\ude41 hopefully a light lapping of the top layer will remove all the fill and help show more details",
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      "content": "I'd expect it to fairly easily come off on a nice flat grinding surface as e.g. used by over lockers in \"die lapping\" (post-packaging diy back grinding for improving thermals).\nYou probably have some of the equipment options those people recommend.\nI think it's just float glass plus extremely fine sandpaper or dispersion-bound lapping powder/paste (c.f. optical polishing of telescope mirrors with pitch on a negative to embed the grit in).\n\nIf the surface is flat you just have to balance pressure on the die along two axis to get only rid of top metal but not lower metal across the whole chip.\n\n[Edit: I initially read it as \"light tapping\" and was a bit confused about your plan... I only read \"lapping\" after hitting send.]",
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      "content": "Me and my two artists have been hyperanalyzing all the die shots people have been sending to try and elevate silicon art to the next level",
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      "content": "hehe light tap breaking \ud83d\ude04 \n\nWe have a surface plate at work that generally gets abused for sanding/lapping so I'm thinking to grab that + some fine diamond paper? Trying to figure out the best way to fixture it to prevent rounding/tilt though. I dont have a tripod fixture, although I guess I could DIY without much hassle? Maybe just glue 3-4 chips onto a flat piece of metal and hope it's fairly planar across all of them",
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      "content": "I've been scrolling through the siliconprawn discord IC photos, really impressed with what some of those folks can do! amazing microscope shots",
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      "content": "We believe that silicon art can be more than just shapes in a single metal layer",
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      "content": "May even go as far as abusing quantum effects since we can manufacture structures smaller than wavelengths of visible light",
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      "content": "ah yeah, could definitely engineer the features to give you diffraction patterns that you want, rather than randomly. real structural color stuff",
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      "content": "cool idea!",
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      "content": "Look at that green glow in-between the metal5 stripes here",
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      "content": "I wonder what the significance of that is",
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      "content": "What is the spacing between them?",
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      "content": "lemme pop it into imagej, one s. i think that might just be out-of-focus aberration blur in this case, the stitching auto-focuser algorithm was preferring to focus on the middle layers it seems",
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      "content": "1.37um ish",
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      "content": "Is this just the horizontal stripes of the default top-level power grid?",
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      "content": "Because then, it should be closer to 1\u00b5m",
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      "content": "Which I would like to note is twice the wavelength of green light",
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      "content": "yeah it's just the power stripes. from this region",
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      "content": "Btw, what is the difference between the photos where its all colorful and the ones where its just shades of orange?",
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      "content": "the orange is coaxial light, and the colorful one was something closer to ring lighting + some DIY polarizer (which didn't work particularly well)",
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      "content": "off-center lighting definitely helps make more colors pop, i assume from the thin film interferences of different layers",
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      "content": "my evening yesterday, trying to find a good combo of lighting and settings \ud83d\ude02",
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      "content": "You're not gonna round against a flat reference if you put any proper attempt into flattening the motion-force vector to be more in-plane than plane-normal, say by sticking the chip to something as simple as a microscope slide with a dab of not-too-shear-strong (so you can shear it off later to release) glue. I'd try fairly shitty superglue for that, I'd expect to be able to release that if necessary, but you probably have a better idea.\n\nThe thought is to inspect the progress and adjust tilt-bias (e.g. by shifting where exactly into the chip's backing plate you introduce the friction-generating \"force\") as necessary.\nI'd just try on one by hand tbh... the skills/nuances should be fairly close to achieving a good straight bevel or even more, a straight-and-flat back, on a \"simple\" wood chisel.\n\nThis is top metal, not some low thin layers, the flatness we target is on the order of several lambda... and pretty sure it's not _that_ hard to hand-lap a parallel plate glass disc to sub-lambda flatness if you have a good flat reference to just copy the surface curvature from.",
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      "content": "pretty sure for proper polarizer explotation of the \"specular reflections maintain polarization, if the light source is polarized you can filter the reflections out if you adjust the angles correctly\" that photographers use outdoors with sunlight against e.g. water surfaces and glass panes would want the light source to also be polarized and the polarizer angle between the source and the scope to be adjusted for the illumination angle? Might need collimated illumination to work well, I haven't gotten back to the local microscope to test that theory out on actual hardware (with 3D goggles and a collimated flashlight, and a hand-held (if it doesn't by chance screw in) DSLR polarizer on the soldering microscope).",
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      "content": "Excited to see that! Any thoughts on if you could simulate the behaviour with things like that optical simulation / ray tracing tooling?",
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      "content": "Maybe? Ray tracing has the best chances of actually simulating the effects of different light angles accurately.",
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      "content": "Did I paste this here in the end? https://www.linkedin.com/feed/update/urn:li:activity:7443670533818204161/",
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      "content": "What would be cool is if we had control over layer thicknesses in gf180. I actually know someone who produced the old rainbow apple logo on a silicon die in all its colorful glory by manipulating etching depths. But they needed a lab and DIYing the process to do it.",
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      "content": "Please don't break our fabs though \ud83d\ude06 us process engineers get cranky when we have to go to quality meetings because of these sorts of things lol... your best bet is probably to abuse the oxide nonuniformity caused by pattern density during CMP, but unpredictable is categorizing the result lightly \ud83e\udee0 . What you're likely seeing in that 1.37um gap between lines is thicker oxide than the field due to local polish rate difference",
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      "content": "I was just searching for the open source litho simulation and came across https://github.com/TorchOPC/TorchLitho - \"Differentiable Computational Lithogrpahy Framework\"",
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      "content": "You don't have to worry, this stuff is going to GF \ud83d\ude09",
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      "content": "I have eng peeps who work there haha, thinking of their mental health too \ud83d\ude01",
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      "content": "Randomly ended up at https://ai4eda.github.io/",
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      "content": "computational litho is for OPC or rather, calculating the structures from the masks, not simulating how things look under a microscope?",
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      "content": "@namibj - Yes, but there were people talking about litho simulation in https://discord.com/channels/1361349522684510449/1495683592762953758 and other people here talking about Differentiable Computation stuff",
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      "content": "Anyway, off to the airport again!",
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      "content": "If it passes DRC it shouldnt break the fab, right?",
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      "content": "hopefully not! lol",
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      "content": "I am so enthused watching all of this.  Need to get the Great 2026 Compiler Project to a point where I'm happy with the overall progress so I can investigate possible projects for future wafer.space runs.",
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      "content": "watching hobby/indie ASIC development starting to approach the kind of accessibility that hobby PCB production did in the early 2000s has me very excited",
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      "content": "That is exactly what I'm hoping to make happen! \n\nThe first PCB I did was a \"call us for a quote\" and the only reason I got an answer was that my University had big orders with them and they owed my supervisor a favour or two.",
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      "content": "In theory, practice and theory are the same, in practice they are not \ud83d\ude42",
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      "content": "Perhaps what I really meant to ask was \"If it passes DRC, are you contractually protected if something at the fab breaks\"  \ud83d\ude02",
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      "content": "yeah... compare with projects I've done in the last couple years, where it's a few tens of dollars to get 5-10 boards in 3-4 *days*.  Just mind blowing.",
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      "content": "along with \"it's their fault for the DRC not being rigurous enough to cover their manufacturing line's requirements for process control\"",
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      "content": "this kind of stuff makes me feel optimistic for the future, which is impressive considering how completely fucked bigtech appears to be at the moment (and working to destroy itself at a crazy pace)",
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      "content": "sadly pretty much the same still for HDI.\nThey haven't figured out how to do blind/buried vias without paying human engineers several hours of labor \ud83d\ude41",
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      "content": "I remember how much of a difference just OHSPark doing runs every few weeks even with it taking like ~8 weeks for stuff to turn up in Australia was.",
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      "content": "yeah 2 week spins from OSHPark (west coast US was Easy Mode for that) was still absolutely revolutionary at the time",
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      "content": "That's a subset of the \"DRC are there so you can be confident netlist extraction/device recognition output will correspond to system behavior\", but these latter more stringent rules are far more flexible, mostly just affecting yield of the specific structures that are in violating without a blast radius as large as antenna violations.",
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      "content": "Dunno, I'm pretty sure if you mess up their machines frequently despite DRC passing they would just start refusing all your orders.",
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      "content": "I would too",
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      "content": "there are actual equipment-damaging failure modes possible?",
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      "content": "I'd expect them to charge me for them to write DRC rules that actually hold on grounds of me being the first one daring enough to feed DRC-exploit-laden GDSII in high enough quantity.",
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      "content": "No idea. I know that metal lifting off and floating around can be bad... But unclear if that hurts machines or all just your wafers...",
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      "content": "And it's not really like we can introduce exotic contaminants with GDS file \ud83d\ude1b",
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      "content": "antenna violation AFAIK risks blasting chunks into the sputtering chamber and contaminating the walls; needs cleaning of the machine that is vaguely similar to like a high school classroom getting puked in: not normally needed, kinda can't be ignored without problems, technically things could progress but there will be issues downstream, and the cleaning is _intense._ No lasting damage to the building/facility though.",
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      "content": "I can definitely imagine failures that could damage the overall wafer and DRC to avoid that being especially important for shared shuttle runs and the like, but was unsure if it could be worse than that",
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      "content": "@needsadrink|woke - I think you just found a new analogy to use \ud83d\ude1b",
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      "content": "I don't know how often antenna violations cause that failure mode vs. just frying a couple gates into being very leaky",
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      "content": "not surprising though that these very expensive manufacturing processes have very conservative pre-run checks",
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      "content": "and well ofc density violations mess with CMP flatness and will cause fairly predictable/expected iiuc litho failures downstream from I assume out-of-focus/DoF effects?\n@needsadrink|woke can you share what exactly is the problem from CMP being done on uneven density, because I doubt it's the CMP itself breaking, but rather that subsequent processing takes issue with the surface flatness (lack thereof) from CMP being done on uneven density?",
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      "content": "well yeah its rarely a single point of failure, nonuniformities will always cause 2nd, 3rd order etc effects",
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      "content": "afaik there are negligible machine risks to DRC-illegally-narrow transistors on planar technologies (like >=45nm standard CMOS processes)",
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      "content": "They're just gonna get increasingly varied transimpedance, to the point where it becomes essentially unusable.",
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      "content": "its hard to know what has the possibility of breaking without having the process flow spec to look at",
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      "content": "fair.\nI assume those documents are NDA even for these \"open\" PDKs, though?",
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      "content": "yeah, they are the secret sauce usually",
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      "content": "figures.",
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      "content": "especially in full objective spec form haha... kept in safes, etc",
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      "content": "yeah \ud83d\ude04",
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      "content": "fab is just a cleanroom full of process control",
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      "content": "(and wired+plumbed up machines, but that seems to mostly not be the big cost factor overall just to \"plug them in\", relative to the rest)",
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      "content": "yep its a nonstop futile exercise in keeping entropy at bay lol",
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      "content": "stumbled across a linkedin post about the concept a while ago",
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      "content": "that's not terribly surprising.  there's an awful lot of \"it's amazing anything *ever* works at all\" in various places across a number of industries ^^",
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      "content": "\"constant rescue\" is just the perfect way to put it. every morning is just an exercise in keeping calm as you read about the various disasters that hav transpired since you clocked out \ud83d\ude06",
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      "content": "aren't they mostly pre-disasters on grounds of not yet having hit any severe yield impact, but are about to do so?",
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      "content": "hopefully! \ud83d\ude01 not always haha",
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      "content": "sure.\nAnyways, I shouldn't chat too much about this while there's a 15 day deadline active.",
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      "content": "I actually didn't hear about the former failure mode @imec; only heard about antenna just as reliability problem mainly related to CMP (chemical-mechanical polishing).",
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      "content": "Also haven't heard about machines being damaged bue to design problems; e.g. nothing that a good clean could solve.\nBTW, cleaning equipment was kind of standard procedure in the research fab @imec. For example there where tools that needed to get a clean each time they went from Cu-contaminated state to non-Cu-contaminated.",
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      "content": "well yeah, but AFAIK a gf180mcu fab isn't a \"research fab\", but a \"high throughput low cost\" fab, and those expect to run their equipment with minimal disruptive maintenance until they need to disrupt it to prevent meaningful impact on yield, or if the maintenance is easy and good preventative maintenance.",
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      "content": "i imagine being 30yrs old helps too. everything is probably bigger and more robust and less fancy if I had to guess",
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      "content": "fault detection does go a long way to prevent completely catastrophic events for sure, but you can still get outages due to things like arcing in sputter chambers if your clear area is too high etc, or yeah liek you mentioned, materials contamination in production chambers, never fun because its never caught immediately and tends to put hundreds or thousands of wafers on ice for a review board to convene to disposition",
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      "content": "usually its \"fine\" but if youre manufacturing stuff that has to conform to IATF 16949 or the like, you may end up being forced to downgrade a bunch of wafers",
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      "content": "Are there already (conditional) plans for a Run3?",
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      "content": "As far as I understand it, run 3 is pretty much locked in. Many of the changes we are hoping to implement from what we learned in run 1 will be implemented in run 3 to give the maximum amount of time for those to know a) what changes there are, and b) have enough time to make those changes. \nAs far as the timeline goes, it depends on people being interested and purchasing slots, the more slots, the faster we make runs.",
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      "content": "Any estimates regarding the deadline/heads-up that Run3 would likely spawn with?",
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      "content": "Not exactly. I can say that we expect to obtain the finished wafers *[for run2]* in Oct. and ship them as soon as we can after that. \nRun 3 timeline would me imminent around then.",
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      "content": "The CoB have arrived \ud83c\udf89  Now I just need some PCBs, bad timing...\n\nhttps://discord.com/channels/1361349522684510449/1496850151950520443/1498370675914703032",
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      "content": "Why bad timing?",
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      "content": "If people have photos or other media they are willing to share about run #1 - could you add them to this Google Photos Album? https://photos.app.goo.gl/2vo4baXmki3fGFdb7",
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      "content": "Bad timing on my part, I don't have any PCBs to test the chips yet ^^",
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      "content": "I was pondering if it was more of a \"this is going to distract me from the bunch of DRC rules I need to be working  on\" \ud83d\ude42",
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      "content": "The CoB wire-bonded dies arrived at JKU today. They look awesome! \ud83d\ude4c\nUnfortunately the DIP adapter board is still in production. Hopefully I can post bring-up results soon. \ud83d\ude42",
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      "content": "Amazing photos!",
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      "content": "Hi, does anyone have a PCB  GitHub repo where I can check the connector again?\n\nI think I messed it up and want to compare it with a working reference.",
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      "content": "Wie macht man so gute Fotos?",
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      "content": "Fettes Makro-Objektiv oder optisch gutes sauberes Mikroskop. Und gute Beleuchtung.",
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      "content": "Cheap digital Microscope (Andonstar AD407) for around 100\u20ac and a mobile phone camera. Try to get a good light. Honestly, I post-processed the pictures with ChatGPT. For the right picture, this worked incredibly well. For the left picture, it also worked fine. However, if you look closely, some bond wires look strange. This is due to the fact that in the original picture, the bond wires were sometimes not visible at all. \ud83d\ude05",
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      "content": "errrrm please don't pass off AI images as photos",
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      "content": "@Simi These images are amazing! Would you mind if we used them?\npinging @kris",
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      "content": "Please add these pictures to the shared photo album if you can!",
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      "content": "I'm not too happy about the use of AI here either. I think we should try to keep photos authentic and only perform basic image post-processing (using the correct tools) if necessary.",
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      "content": "To anyone who has already received their COBs, did it get shipped in a box or envelope?",
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      "content": "Also, does this drop-down load for anyone? I\u2019ve never seen it display anything else for years. I always have to contact customer support to change my deliveries and its becoming increasingly difficult to get through to a human.",
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      "content": "Only times I ever see that working is when the first delivery failed.",
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      "content": "My Mouser order just failed to be delivered and it still says that. I\u2019m trying to reschedule it to the same day as the COBs are set to arrive.",
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      "content": "@Tim 'mithro' Ansell https://discord.com/channels/1361349522684510449/1361349523724570938/1499380331914989740\nYou can use: 05/01/2026 11:59 Friday, 01 May 2026 11:59:00\n\nHere is what you have to send: `05/01/2026 11:59 Friday, 01 May 2026 11:59:00` it's `<t:` followed by the unix timestamp then `:` then a letter that changes the format (`R` for Relative, `F` for full, ...) and finally close it `>`",
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      "content": "it shows a localized date",
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      "content": "for example here is how I see my own message:",
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      "content": "It looks like next week is going to be bring-up day for me",
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      "content": "More like bring-up weeks",
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      "content": "Its going to take forever to get through everything",
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      "content": "I\u2019ve spent many hours this week preparing my C64C to receive my chips",
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      "content": "Bonded the first Cloneless1 dies here locally (custom pad frame) and tested them on a breadboard (always gives me some nostalgia \ud83d\ude05) before the real PCB arrives next week. Everything seems to work nicely \ud83d\ude01",
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      "content": "Looks like Au wire",
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      "content": "We are using AlSi wire",
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      "content": "@Tim 'mithro' Ansell Wait no, on the pictures from the bonding factory, it's \"AlSi\" wire.",
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      "content": "But I'm just generally confused I think. \ud83d\ude1b",
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      "content": "Can you add them to the photo album at https://photos.app.goo.gl/2vo4baXmki3fGFdb7 ?",
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