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    "category": "Information",
    "name": "general",
    "topic": "Welcome to [wafer.space](https://wafer.space/) - \ndocumentation at [wafer.space github](https://github.com/wafer-space) - \nbuy at [buy.wafer.space](https://buy.wafer.space) - \narchives at [discord.wafer.space](https://discord.wafer.space/)"
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      "content": "@Noritsuna Imamura - Have you had a chance to give the ISHI bare die a probe? I would be interested to know how that goes! \n\nPlease take lots of photos of your testing and share them too! I'm 100% sure others here would also be interested in your results.",
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      "content": "From the picture - AiSi1% at 0.8mil width. Apparently the 0.8mil wire is about 5x or 10x more expensive then the typical 1.0mil width bonding wire they use.",
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      "content": "BTW Everyone, I still remain very interested in trying to bring back gate arrays in the form of a base device created by wafer.space that then uses a single final coarse metal layer to do the final programming of the die - see some random ideas @ http://bit.ly/ws-gatearray-v1",
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          "description": "GF180MCU Gate Array https://bit.ly/ws-gatearray-v1  Goal Create a good gate array which is programmable with post manufacturing additional of a metal layer in the  1-4um sizes.  Specifications  Final Metal Layer for Programming  The goal is to have the gate array programmable by adding a single e...",
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      "content": "that's a fun idea. was thinking about laser trimming earlier today but I like this idea more",
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      "content": "We plan to conduct tests using the probe.\nHowever, we expect that preparations will take a little more time.\nOnce the measurements are taken, we plan to report the results.",
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      "content": "@BreakingTaps - An alternative idea is to use something like lasers to cut paths rather than metal to add paths.",
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      "content": "@BreakingTaps - I feel like people like you, the Dr Semiconductor guy, and Hackerfab people could then do \"ASICs\" use these die in a few hour turn around.",
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      "content": "yeah we have an Au ball bonder at work if we ever do a tapeout for a test project i can hand bond initial test ones",
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      "content": "a little RV32 core, a splash of SRAM, UART, SPI, and gate array fabric might make an interesting little chip",
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      "content": "Yeah this is a really compelling idea, especially since you'd have 1000 to play around with. Will do more thinking on it!",
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      "content": "It seems like there is a lot of choice in the tiny silicon proven RISC-V cores like SERV and TinyQV and Fazy",
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      "content": "Most structured ASICs I have seen (eASIC, Triad Semiconductor) were using via layers for the customization layer(s). Via layers should also be able to be done faster for a maskless process like ebeam litho.\nOne idea I had was to actually start from FPGA architecture but replace the storage cells in the LUTs and the routing cells with vias.",
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      "content": "any idea on how the material cost compares to the capex/machine time there? Because without it's little to go on, sadly.",
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      "content": "This was talking about the material cost of the actual wire (according to the bond house), not anything else.",
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      "content": "Yeah, I know.\n(It's just not at all actionable to any of us AFAIK without being able to see any perspective there.)",
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      "content": "doesn't have to be for sure tho",
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      "content": "Yes, but the current \"standard\" way of doing most structured ASICs / gate array devices has lead to them no longer being manufactured / killed them -- so following down that path seems like not the best idea \ud83d\ude42",
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      "content": "Hey folks! Quick GF180/wafer.space question: are there any usable on-chip NVM options for open submissions, like MTP/YMTP, or should I design assuming no embedded NVM and boot from external QSPI flash?\n\nMostly looking for practical experience / gotchas, not an official commitment. Thanks!",
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      "content": "Somebody made an OTP efuse compiler, iirc the first tapeout failed due to a missing power connection",
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      "content": "i dont know if the next revision is back yet",
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      "content": "but AFAIK gf supports fuses on this node",
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      "content": "its the kind of thing you would use for trim settings not firmware",
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      "content": "Oh yeah, sounds painful \ud83d\ude05 are there any other options for rewritable NVM though? (not OTP)",
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      "content": "Not to my knowledge. Flash etc needs a lot of extra masks that add significant cost",
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      "content": "There may be a ROM compiler, i know folks were working on them but not sure what's been silicon proven so far",
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      "content": "but if you need it field programmable just hang a spi flash off they're cheap",
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      "content": "for me its some complicated to have 3 different flash, but for first demonstrator maybe its best option)",
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      "content": "It was me :). New revision is currently being wirebonded, so in a couple of weeks we'll see if it works.",
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      "content": "what's the tl;dr here? Just not commercially viable vs taping out your own chip? I'm not super familiar with the history of these devices",
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      "content": "AFAIK people use FPGAs and probably modern scaling's issues with leakage power discouraging from doing things the old way.",
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      "content": "Very cool pictures!",
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      "content": "My theories on why gate arrays went extinct are the following:\n * Gate arrays meant dealing with a silicon foundry. Once you have gone through the huge effort of dealing with a silicon foundry, then the performance improvements of going full custom seem higher ROI.\n * Most groups focused on trying to make gate arrays competitive with custom silicon design from a PPA rather than focus on time to market and customizability.\n * Foundries still wanted to own the customization step, not just the production of the starting gate array material.\n * Gate array refused to learn from what FPGA people where doing.\n * CPUs & FPGAs got a lot better.\n * The industry is so focused on volume and scaling that gate arrays don't make sense when you assume every project needs to sell 1 million units before it breaks even.\n * Maskless solutions in foundries never took off because again the industry is so focused on huge scale.\n * Everyone one was focused on the silicon side and did not invest in the software side.\n\nI haven't done an exhaustive search, but a lot of the gate array examples I have seen had the silicon wafers prepared to the end of FEOL and then used highest density metal for configuration. This (maybe) makes sense if you are trying to do gate arrays of transistors and form them into standard cells and SRAM blocks but also means they still take quite a long time to be made (IE O(months) rather than O(hours)).\n\nBasically, nobody was focused on:\n * How to I make gate arrays cheap and fast for the small run or even individual unit use case.\n * Providing prebuilt items like SRAM blocks, wide busses, etc.\n * Focused on enabling as many different solutions for programmability.",
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      "content": "I would say that gate arrays might be interesting if they'll be available with a rapid PCB prototyping kind of \"programming\" service. Something like a TinyTapeout, but with a turnaround time of about a week and a cost of around 200$/10 units might find its users.  The gate array should have something like 20% of logic density if compared with a full custom layout on the same technology, so WS full slot based GA will be large enough to fit a decent design even with around half of the area reserved for the fixed logic like a CPU and SRAM.",
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      "content": "@Egor Lukyanchenko - If we could prove a wafer.space die could be programmed using something like the HackerFab Stepper (which is like ~$10k USD) and each wafer.space die is $7 USD a part, then $200 USD for 10 units in 1-2 weeks kind of seems like something someone could have a small side business doing. (10*$7 == $70 USD for the die leaves $130 USD to cover the time and HackerFab stepper investment).",
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      "content": "@Tim 'mithro' Ansell \n> If we could prove a wafer.space die could be programmed using something like the HackerFab Stepper\nIf the spatial resolution of the HackerFab machine for adding the top metal is known, the achievable logic density of such GA could be easily estimated. The software flow based on Yosys+OpenROAD appears to be doable, as the only truly custom step is constrained placement, which is closer to the FPGA than to ASIC. But designing a \u201cgood\u201d GA architecture, which could achieve a reasonable density and speed, will take quite some time, I think.\n\n>  (10*$7 == $70 USD for the die leaves $130 USD to cover the time and HackerFab stepper investment)\nThat is where my 20$/piece price came from :).",
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      "content": "Yeap, so it just needs someone to \"do the work\" \ud83d\ude42",
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      "content": "I agree - if there was a way to one-time program gate arrays (post-production), that would be popular and useful, and a good use for any excess capacity.",
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      "content": "> The industry is so focused on volume and scaling that gate arrays don't make sense when you assume every project needs to sell 1 million units before it breaks even.,\nYeah this is overall sooooo endemic.\nReally hurts innovation, obviously.",
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      "content": "afaik the biggest spenditure would actually be time, and space",
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      "content": "You cannot guarantee a scalable chip if you don't have a reliable cleanroom, and you need to have not only the litography machine (which, granted, tens to be the most expensive machine), but also a way to bake the wafers, a way to supply said wafers, a way to deal with potentially dangerous chemicals, a way to inspect the chips, and you need to do all this with reproducibility always in mind",
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      "content": "To be fair as they do advertise on the Hacker Fab website, they're quickly refining the process and the price to manage making low-volume chips is quickly going down",
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      "content": "I myself know I want to make a Hacker Fab myself, for my low-volume ASICs, but I would never feel comfortable selling at any scale larger than 5 or 10 of them to individuals",
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      "content": "I'm actually skeptical that a reliable cleanroom is needed when you are doing stuff on individual chips and something like a single 5um or 10um metal layer. Plus if you have a 1 in 10 failure rate, you have only lost like $7 USD for that failure.",
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      "content": "A semiconductor fab wouldn't accept a 10% failure rate per metal layer because they need to do like 5 or more metal layers and on failure you just burnt a an almost complete wafer. But here you only have 1 layer to do and a failure is only negatively impacting a pretty cheap cost.",
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      "content": "Hmmm that is fair",
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      "content": "In practice a good solvent choice might even be abe to get rid of most meaningful aberrations",
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      "content": "It's risk verse reward -- If I'm spending $X billions to build a fab, then I'm going to be a bit more demanding than if I'm just spending $10k USD \ud83d\ude42",
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      "content": "of course, that is fair! But you also have to take into account that the difference too is in the fact that the one assembling a billion-worth fab is a multibillion company, whilst the 10k fab is an individual",
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      "content": "And the multibillion company already has a market and investors, so it can ensure that the projects will see the light of day",
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      "content": "I can guarantee that if I also had investors and knew I'd make at least as much as I spend on making a fab setup, I would just, make the fab",
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      "content": "But it's a bit of a risky gamble",
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      "content": "Those minimal fabs try to solve this by fitting the equipment in a small, highly automated volume instead of maintaining a full cleanroom. I think you can make this idea work.",
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      "content": "Hmmm yeah that definitely sounds like a pretty plausible idea",
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      "content": "Yeah and the market can't be too hard to find",
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      "content": "yeah single layer is not that intense cleanroom; also you just use essentially a line of laminar flow hoods; you don't need the humans in the clean part of the room",
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      "content": "While it is a definitely a privileged position, I'm sure that there are a lot of people who have $10k spare compared to multibillion dollar companies willing to risk building semiconductor fab.",
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      "content": "5 to 7$ for a chip, custom made with at most 6 weeks lead time, seems like a great offer I know I wouldn't pass on",
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      "content": "Medical sensors need the analog capacity, and subthreshold design for ULP as well",
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      "content": "Also small businesses might benefit from this",
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      "content": "well there is a whole small business in and of itself",
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      "content": "If we can find a way of doing heterogeneous packaging the opportunities will explode, which I know @namibj was interested in",
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      "content": "hmmmm",
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      "content": "It can probably be done by using \"internal pads\", kind of how PCB stacking was done during the transition to transistor logic",
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      "content": "I've seen a few good PCBs, if on the older side, that used this to their advantage, so I don't see why it couldn't be done with silicon",
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      "content": "My entrepenurial and experimental sides are coalescing too much over this idea and I feel the pull to make a crowdsupply campaign to try and get an \"indie semiconductor fab\" to be a real thing /hj",
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      "content": "Share?",
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      "content": "Check the link Tim sent, its something people are working on for sure",
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      "content": "Uhhh I have one very good example on the workshop. It used to be on the innards of a locomotive when the whole thing about \"electronic security\" was starting to be a thing",
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      "content": "Iirc they have various copper pillars that are bolted in between two PCBs and they're used to transmit data directly between the 2-layer PCBs",
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      "content": "Well I say two later but it's just a one-sided copper substrate",
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      "content": "Yeah I know and that's the thing, it's something I'm definitely interested on trying for myself anyways so might as well make my thesis and a business out of it xd",
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      "content": "I'm trying to convince PCBA houses to offer wire bonding as part of their PCBA services which opens up a way to integrate a bunch of devices together.",
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      "content": "Yeah the bad thing is that that would be a costly service not many at-scale clients would use",
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      "content": "JLC for example earns most of their money off of medium-batch PCBA and large-scale PCB manufacture",
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      "content": "PCBs where once a costly service \ud83d\ude42",
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      "content": "Everything else they offer is just either cheap to have running or can be easily made with the otherwise defunct machines involved",
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      "content": "Yeah of course! But that didn't stop them from being popular!",
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      "content": "Wire-bonding is still a very niche process except for very specific applications, and the companies that can afford to supply dies can already afford to bond and coat it themselves",
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      "content": "So you try telling the JLC executives that if they drop a bunch of money at adding another service, it might be profitable after... Well, between a long time and never",
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      "content": "@Dory - Don't know about JLC, but a number of other groups (like PCB Way) already have wire bonding machine -- they just don't offer access to those machines to non-chinese customers today because they don't have a way to do automated quoting like they can with PCB/PCBA.",
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      "content": "Ahhh that is very fair",
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      "content": "I wouldn't have thought that is the case, see",
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      "content": "But then again it makes sense too",
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      "content": "Though I'm guessing my argument for why you wouldn't do it small scale still applies",
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      "content": "It's so costly to have a few bare dies shipped to china, pay full time engineer hours for operation of a machine that can easily take an hour to be done, and needs their full attention, and then to pot it an ensure it will last",
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      "content": "But it'd be awesome to see it become a thing, so I'll pray for your success from the sidelines hehe",
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      "content": "Workshop?",
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      "content": "I'm happy the GaN are lateral devices, so unlike the SiC JFETs from (formerly) UnitedSiC, no need for silver sintering.",
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      "content": "Though I should look at whether that (low temperature silver sintering) can do enough resolution to work for flip chip bonding of wafer.space dies without (much/expensive) post-processing.",
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      "content": "Yeah I have a little workshop on the other side of town. Well it's my father's but we kinda share",
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      "content": "Allows for automatic generation of multi-project setups with all 50 GPIOs shared between the projects, up to 15 projects",
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      "content": "One possible application for this is it to further reduce tape-out cost by carrying multiple different people\u2019s projects on one die",
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      "content": "I'd probably be able to bankroll a single one of these dies worth of wafer.space next year if we have figured out a way to bond the gate drive current to the wafer.space die for it.\n\nI'd actually assume it should be possible to do without flip-chip but instead \"just\" using the kind of thick rectangular al bond \"wire\" they use for e.g. the TO-247 packages of the UnitedSiC Gen4 cascodes:",
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      "content": "That's a large SiC vertical jfet drain down with a 30V vertical silicon mosfet drain sintered to the SiC source; the SiC gate is the tiny pad off to the left; then the mosfet has a kelvin gate bonded out (two legs of the TO-247 for gate purposes, one is source the other gate) and ofc the fat source bonding for the load current.",
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      "content": "Very cool! \n\nI'm very on board with promoting this work and having people hiring your services to help people afford slots by sharing.",
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      "content": "I would ***potentially*** be interested in exploring how a pattern like this on the top metal could be used for bonding directly rather than needing bond wires (IE provide free silicon if there is spare/leftover space on the shuttle).",
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      "content": "non-wedge-bonding should likely be fine with active area underneath; for merely testing the flip-chip tactic(s) as-such it shouldn't really need more than.... wiring a normal IO pad to a suitably large pad in a more central location on the die?\nI don't know what non-customer-GDS slices you're planning to have for Run2, but later this month or possibly early next month I'd be up for making a more concrete proposal/\"pitch deck\" with the ESD aspects researched out for such an option/opportunity.\nIf that's what you're approximately thinking of here?",
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      "content": "I don't really care about being pitched too, I'm just interested in helping promote the exploration of ideas which might help reduce cost further by eliminating wire bonding and such.",
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      "content": "no I mean regarding a concrete concept of how to potentially explore how such a pattern on top metal could be used for flip chip bonding, without having to dedicate the flip chip pad's top metal occupied area across all layers (e.g. it should only need a fraction of the active area underneath, unless we assume particularly advanced fine-pitch flip-chip techniques)",
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      "content": "oh sorry, I again misread; I thought you said \"I don't really recall being pitched to\"",
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      "content": "I won't have any of the analog PA things (needed to make integration with one of those GaN chips useful) ready in time for Run2, but there's other things that could be bonded to a Run2 die to trial the bonding process itself.",
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      "content": "I also don't need to necessarily understand everything either :-). Throwing stuff against the wall and seeing what sticks is part of the idea behind trying to make things continually cheaper.",
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      "content": "Filling the die with different types of silicon capacitors (MIM, MOS & MOM) and maybe even some efuses with a very simple 1-wire core so info about lot number, wafer number, wafer position could be burned into the device would be perfectly resonable to me.",
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      "content": "Yeah, I thought to mean that for whoever would try to make more productive use of the lower layers in that area (those not used by the ESD structures), to \"convince\" them that this upper layer structure with a little bit of active pad structure underneath would be harmless enough to include.\nCould be with some new sram macro trial or something more experimental than normal slice usage, I'd assume.",
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      "content": "Oh yeah it should be perfectly fine to trial efuse designs (well, EPROM as a general concept, I don't mean the specific UV-erasable variety) in the spare active area under such a pad.",
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      "content": "Random Google doc with ideas @ https://docs.google.com/document/d/1ahoCTmPvKExYtk3qqxvjMpnq5XOcIQvVWMF84zgi82k/edit?tab=t.0",
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          "title": "wafer.space - GF180MCU Silicon Capacitor",
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          "description": "GF180MCU Silicon Capacitor Goal Create software which is able to generate a \"maximal silicon capacitor\" for a given configuration.  Specifications  GDSFactory https://gdsfactory.github.io/gdsfactory/ \u000b Uses AI to tune the capacitor capacity (IE the shapes of structures). https://gdsfactory.github...",
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      "content": "in lieu of anything better I'd suggest an ice40ul1k-swg16 or a ice40up3k/ice40up5k (I heard they're the same; the former just isn't sold in the QFN48 package)",
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      "content": "but yeah silicon capacitor pinned raw out to the pads could be something; antenna diodes are used in avalanche connection to be reverse-biased in normal operation, right?",
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      "content": "sorry this was the one for the up5k; the above ones were just the ultra lite vs. ultra [non-lite]",
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      "content": "I'm currently working to source known-good-die of ice40up5k through my Lattice contacts.",
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      "content": "I miss the days when those parts were $4-5 in handful quantities",
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      "content": "@Brian Swetland - How much are they these days? I've generally gotten them at $1-$2 USD per part in the past (but I've been buying multiple full reels at a time).",
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      "content": "looks like cut tape, single digits is $10-11 on digikey/mouser... down to $8-9 in the hundreds",
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      "content": "I assume some combo of popularity and the parts crunch that kicked off a bit into the pandemic were contributing factors here",
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      "content": "being able to buy 5-10 for ~$4 each was hobbyist fpga nirvana back when the yosys/nextpnr tooling was getting solid",
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      "content": "I don't believe the reason for example eASIC in the end failed was technical but financial, e.g. investors driving it in the wrong direction. A lot of companies fail not because of technical unfitness.",
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      "content": "Is there a feedback mechanism for the patterns between the dies? I am running into a problem where I need to generate data to train a model, and I don't want to grab people's work and throw it into a training dataset without explicit permission.",
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      "content": "\"patterns between the dies\"?\nCan you rephrase that message, it's hard to understand what you're trying to say there.",
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      "content": "There are test patterns in the spaces between the dies",
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      "timestamp": "2026-05-03T16:52:39.512+00:00",
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      "content": "If you don't need the extra IO get up3k (so I've heard; I'll try in some weeks, probably shortly after the Run2 deadline), the only way they could reasonably do the implied binning to lower fabric block/component availability would involve per-die PnR (even if only a reduced PnR, it's clearly gonna involve per-die bitstreams) and there's no sign in any of the dcumentation that they would burden the customers with such.\nAt least in the open tooling I'm told it just doesn't apply the lower ressource limits, treating it essentially equivalent to a 30-ball WLCSP up5k and at worst setting a couple bits to mark the bitstream as \"for up3k\" to pacify possible validation.",
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      "content": "you can get the latest gowin parts for a few bucks a piece, I believe they're supported by an open source toolchain",
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      "content": "Yeah, it's actually pretty surprising what you can get away with at 1um and larger size. All my diy stuff was in open shop air and rarely had issues with particles. Solvent cleaning and thorough DI water rinses takes care of most particles at a size that matter to big features.\n\nWouldnt be hard to automate in a little HEPA cell either. Single metal layer is just spincoater, hotplate, litho machine and sputter or evap.\n\nMan this is really tempting me \ud83d\ude05",
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      "content": "for maskless metal I'd expect options beyond the traditional litho technique, such as perhaps laser machining.\nLike, the concept of laser trimming is officially supported on the gf180mcu open PDK...",
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      "content": "Possibly, but could be a real challenge. Would probably want at least picosecond laser to limit thermal damage, and green or shorter wavelength to limit depth and focal spot size. Have to deal with debris. Have to be very careful about getting a full ablation and no shorts. End of the day might be harder than a simple 405nm direct write into resist and metal liftoff. \ud83d\ude15",
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      "content": "Yeah.\nThought picosecond sounds a little severe there, and you don't need green for spot size reasons there.\nAre (active, triggered) Q-switched Nd:YAG with their practical lower pulse lengths of about 5~10 ns that poorly suited to ablating \"unwanted\" intersections? Hmmm.\n\nBest not to get bogged down with those thoughts now though, I got a sky130 deadline to ship a bunch of MCML cells for.",
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      "content": "Well spot size is limited by wavelength, so eventually you'll want a shorter wavelength to minimize ablation zone (even with a gaussian spot and only the middle ablating). And nanosecond pulses are deeply thermal because they are so slow, you get a ton of substrate and edge heating. In an ideal world you are in \"cold\" ablation regime (fs to low ps) where your breaking bonds faster than thermal diffusion\n\nI'm on the road at the moment, but can share some 1064nm ns pulse microscope shots of thin films when I get back. Hard to get sub 20um and they are very rough edges.\n\n1064 absorption depth in Si is like a mm or something, easy to nuke other structures below the metal \ud83d\ude15",
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      "content": "Oh hmm fair. Though I'd expect deeper penetration into substrate resulting in less damage to the substrate once/after the metal is gone.\nBut yeah, fair, nano scale has sub-nano timescales \ud83d\ude04",
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      "content": "Update: will have my dies imaged with a scanning electron microscope by a hackerspace that has one. Raw dies ship out to them towards the end of next week (or this week, if you\u2019re in a timezone where its monday).",
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      "content": "Waves silicon seductively......",
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      "content": "I'll clean the later version up once the looming deadlines (ttsky26a & WS Run2) stop threatening me; if anyone wants my preliminary/kinda-experimental tooling (which I'm still cooking rn, I hope it gets to jump into proper optimization/refining before Thursday 5am UTC) before then, _please **ask**_.",
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      "content": "For people who are interested in the state of run #1, here is a summary.\n\nEach wafer has 28 full reticle shots and a bunch of partial reticle shots which mean most designs end up with about ~34-36 full dies per wafer.\n\nThe status of all 25 wafers from run #1 are:\n * 1 \u2715 wafer was manually fully picked by Andrew, these are the sample / loose tape die people should have received.\n * 2 \u2715 wafers where fully picked by Andrew, these are the die people should have received on a 7 inch reel.\n * 11 \u2715 wafers had just the full reticle shots picked using an existing pick and sort house here in Singapore, meaning that we end up with 308 (11 * 28 == 308) being delivered on a wafer dicing frame and 11 \u2715 \"carcasses\" with each about ~6  good versions of each project die on them (so another 66 chips). The carcasses will be going with Andrew to allow him to do testing on the custom die picking machine.\n * 6 \u2715 wafers are diced but unpicked that will be going back with @Andrew Wingate to final testing of the custom die picking machine.\n * 1 \u2715 wafer are with @stuart's alternative dicing, pick and sort house in China (~34 die).\n * 4 \u2715 wafers where undiced and sent to people to use as display items.\n\nThat should be the total 25 wafers manufactured in run #1 (which is a short run that required paid projects to be duplicated to two slots). \n\nLooking at how the numbers have finally shaken out a short run of only 25 wafers saved about 15% of the manufacturing run cost, so normal runs will be two lots -- IE 50 wafers.",
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      "content": "The people who don't get COB, their raw dies have shipped today.",
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      "content": "@Tim 'mithro' Ansell When will the next 11 wafers make their way to china for COB ?",
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      "content": "Would it be possible/practical to have a tiny shared test harness on the reticle that would allow one (coarse?) probing contacting to that harness to the be mux'd to the individual dies pre-dicing to sort out bad dies without having to probe each one individually?\n\nOr would that not be relevant due to the large process node, very-sub-reticle sized individual dies, and the individual-die packaging allowing per-die post-packaging probing at e.g. the COB mezzanine plug?",
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      "content": "Nothing can cross the seal ring",
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      "content": "Me got nerdsniped.\nInternet says well resistor can and are occasionally used for wafer acceptance testing of like non-pinned-out bandgap references and the like?",
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      "content": "(those can't power the DUT tho so it's not gonna work without \"proper\" pads inside the seal ring, hence COB-first test-after looking quite superior)",
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      "content": "Well the 11 wafers don't exist anymore - they are now ~40 separate wafer dicing frames with dies mounted on them. Those have either been shipped to people who wanted only bare die or on their way to china for chip on board mounting.",
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      "content": "GlobalFoundries puts process test structures into the margins of the reticle - this is where the \"etest\" data for the production run comes from -> https://docs.google.com/spreadsheets/d/10zQF_L-KsV-n5zMISB8C67llsldodtbSALWoNdpY17Y/edit?gid=940809968#gid=940809968",
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      "content": "Most \"production scale\" semiconductor chip stuff has a testing phase which is done before dicing. Creating the test harness and test routing is extremely expensive as you are generally aiming to test a whole reticle at a time. The die which fail the test generally get marked with a black dot.\n\n@bunnie will hopefully publish an interesting blog post about going through that experience recently for his BaoChip.",
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      "content": "I have devastating news",
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      "content": "And idk when I\u2019ll be able to",
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      "content": "The dies are upside-down",
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      "content": "I don\u2019t know what to do now",
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      "content": "Even if this is fixable by revision of the PCBs that the COBs plug in to, I have no money for that",
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      "content": "So its gonna be a couple months, at least",
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      "content": "afaik all remaining raw dies have been shipped out to me, so there is nothing that wafer.space can do on their end",
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      "content": "@Tim 'mithro' Ansell If you DO still have raw dies of mine, I would be willing to pay for another set of COBs with the die rotated correctly, as I am 100% sure that this would be cheaper than me re-designing and re-building all 8 PCBs I designed for this bring-up",
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      "content": "I am checking right now if the COBs as they are (flipped) are still usable",
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      "content": "Nope. They\u2019re unusable. Power and ground are shorted to GPIOs all over the place. Most critically, two design select lines are shorted to ground, so can not be controlled.",
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      "content": "If I had made the locations of the power and ground pads symmetrical in my padring layout, I would still be able to bring up one or two things today with the generic DIP breakout, but as it stands, the COBs I have are bricks.",
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      "content": "Oh, the mosbius design on wafer space isn't public ? Can't find a link to the repo with gds and such ?",
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      "content": "Who was the other person that had custom COBs? They may wanna check theirs too.",
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      "content": "That's why I was asking about mosbius above.",
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      "content": "Althugh when they posted their COB design they did note QR code should be in the NE corner so that should be correct.",
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      "content": "I believe we have a bunch of your die still here at the bond house",
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      "content": "@Tholin - I believe we should be able to get another 20 bonded for you tomorrow. So now is the right time to discover that issue.",
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      "content": "Thank you",
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      "content": "The PCBs are fine, you just need to somehow instruct them to rotate the die 180\u00b0",
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      "content": "I wonder if a clear indicator of direction would help with preventing this in the future. Say, putting an arrow pointing outwards in one of the two remaining corners of the die, and a corresponding arrow pointing inwards on the PCB silkscreen?",
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      "content": "Actually, better idea. How would people feel about a script that reads in a padring configuration from a project and generates a KiCad symbol for it?",
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      "content": "Yes, we are planning some changes around how the corners are filled. @Andrew Wingate suggested keeping the corner opposite of the QR code empty to make the orientation more visible.",
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      "content": "That would be great :) We could even integrate it into the precheck.",
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      "content": "One thing I *eventually* want to work on (no promises when) is a 3D renderer that produces images of a die as it would appear under a microscope. I don\u2019t think I can model all the quantum effects accurately, but I can approximate how things look specifically for gf180mcu.",
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      "content": "I realized I\u2019m maybe the only person in here with practical experience with multiple 3D rendering techniques, so I\u2019ve added this to my todo list.",
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      "content": "I have been wanting to be able to make colorful images using refraction or other to generate the colors.",
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      "content": "I\u2019m experimenting with it",
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      "content": "To tape out on run2",
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      "content": "The amount of patterns I can do is limited due to DRC",
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      "content": "Can't wait to see. \nAlso Tim and I just landed in china. \nTomoorw we will be visiting the bondhouse and believe you have more boards and die there @Tholin",
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      "content": "Alright",
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      "content": "Could you still check bonding success rate checking for ESD diodes on the pins that are not shorted to GND/PWR.",
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      "content": "Laptop cannot connect to discord from china",
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      "content": "*GBs",
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      "content": "That is going to be incredibly helpful",
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      "content": "The verification of Tiny Tapeout GF0p2 projects can be seen at https://tinytapeout.com/chips/silicon-proven/#ttgf0p2",
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      "content": "@Tholin - Still working with @Andrew Wingate to figure out how to upload the photos somewhere.",
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      "content": "How much is the total filesize combined?",
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      "content": "@Tholin - I think about ~35G (but that includes other die captures too).",
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      "content": "Ah, I see the problem",
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      "content": "Make a torrent?\nUnless you have need for access restrictions, that is.",
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      "content": "I think a random torrent is likely to have more issues with hotel WiFi and China internet than just using rsync to put them on a server I have.",
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      "content": "Has anyone done simulation using the noise models in the GF180MCU PDK? If so, could you add any info you have to the thread @ https://discord.com/channels/1361349522684510449/1501344740350758992",
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      "content": "So what can I do to get Zeptobars doing wafer.space silicon? \ud83d\ude1b",
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      "content": "The wafer.space gf180mcuD JKU multi-project chip is alive! \ud83e\udd73 \n\nLast night, I wired up the DIP adapter PCB on a breadboard. I just supplied the board with 3V3 or 5V via decoupling capacitors, connected my AWG to the clock input and tied the reset input to high... and voila, the sanity bring-up test works. On one digital output, the Super Mario Bros. theme song is played via a buzzer through a PWM signal. \ud83d\ude4c\nNothing fancy, just a quick breadboard build-up and test, but at least we can say that the chip is alive! \ud83c\udf89\n\nNext, our students can come in and test their own projects. Some motivated students have also decided to build a PCB as part of a seminar work. \ud83d\ude4c \nI will also try to pour some dies into epoxy cubers. I have already received the materials for it. I just need to find some time for it. \ud83d\ude42",
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      "content": "That is very cool!",
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      "content": "I\u2019ve characterized my SCL at the ss_125C_3v00 corner, so all three corners are now done",
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      "content": "I\u2019m thinking of doing a 4th characterization at ss_080C_3v10 since that default slowest corner is kindof extreme. I don\u2019t think anybody here needs their chips to be running at 125\u00b0C, so I\u2019d like to offer an alternative maximum constraint of \"just\" 80\u00b0C at 3.1V",
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      "content": "So people can aim for a higher fmax at the tradeoff of a more constrained temperature and voltage range that the part is speced for.",
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      "content": "(I\u2019m pretty sure at 125\u00b0C you start having other problems, like the epoxy on the COB melting)",
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      "content": "Hi, @Tholin! Thanks for your amazing work on 3.3V SCL! Do you plan to extend your library? Because if you do, I would like to ask you to add some kind of delay cell to improve hold fixing. Currently I have problems with increasing a hold margin for my Caravel port, which I would like to do for safety. OpenROAD generates thousands of buffer cells but with only ~100ps delay each it has a hard time and takes a huge area.",
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      "content": "I\u2019m currently working on making it easier for people to collaborate to the repo",
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      "content": "I\u2019m just one person, unfortunately",
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      "content": "A delay buffer appears to be simply two buffers in a trench coat, where the first three inverters have a narrow gate width. You might even want to experiment with the gate length for even larger delays.\n\nSee here: https://gf180mcu-pdk.readthedocs.io/en/latest/digital/standard_cells/gf180mcu_fd_sc_mcu7t5v0/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_1.html\n\nAdjusting Tholin's buffers would probably be a good start.",
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      "content": "so help me out here...\ncan I build an octocore 6502 with 64b addressing?",
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      "content": "will that work here?",
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      "content": "or similar 'weird stuff'?",
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      "content": "the limitations are your imagination and silicon area",
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      "content": "well that and money to pay to a slot on the shuttle",
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      "content": "someone implemented 6502 on tinytapeout: https://tinytapeout.com/chips/ttihp26a/tt_um_chrismoos_6502_mcu",
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      "content": "ok, so im only limited by pads (pins) and available 'cells'/transistors?",
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      "content": "yeah pretty much",
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      "content": "aye, I was talking to those guys, speed is limited to ~33mhz and a small number of pins",
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      "content": "that and the knowhow to implement all of the things",
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      "content": "i need 80-120 pins, and want to hit 800-1200mhz",
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      "content": "I think the pad ring is not that big",
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      "content": "it said 56-120+ pads",
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      "content": "on the website, so im not sure if we mean different things, perhaps some are multiplexed",
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      "content": "yeah the default isn't that big",
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      "content": "im not sure yet",
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      "content": "just getting some conceptual boundaries",
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      "content": "you are on your own if you don't use the default",
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      "content": "ok, 'can I make the whole thing SRAM'?",
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      "content": "sure",
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      "content": "how many 'cells'?",
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      "content": "or transistors do i get?",
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      "content": "depends on a lot of things",
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      "content": "@Tim 'mithro' Ansell or @tnt might have some approximate numbers",
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      "content": "https://mithro.github.io/gf180mcu-project-template/",
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      "content": "there's some information here total cells used/% area used: https://github.com/wafer-space/ws-run1/blob/density-report/reticle_density_report.md",
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      "content": "TIny Tapeout projects also show the number of cells used in the GDS github action",
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      "content": "Here's mine as an example for Tiny Tapeout\nhttps://github.com/FangameEmpire/ttsky26a_spacewar/actions/runs/25696603247\n2200 cells ~= 70% of two tiles",
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      "content": "Or do you mean wafer.space as a whole",
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      "content": "all of this is on the main page",
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      "content": "Read the little text down below",
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      "content": "Those are theoretical, using the standard cells included in the temolate",
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      "content": "not sure what you are expecting?",
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      "content": "Oh sorry I am very sleepy and thought you were wayfarer",
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      "content": "Wow I really need either new glasses or a few more than eight hours of sleep",
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      "content": "Again really sorry",
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      "content": "it is fine just giving the basic idea",
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      "content": "looks like its fine for some basic ideas. creating a large sram array with embedded processor is not trivial however",
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      "content": "i wasnt sure if the SRAM listed was 'if its all ram' or in addition to some other components",
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      "content": "i have some 65xx variations/other architectures im interested in developing, including ML algorithms in vhdl",
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      "content": "yeah those are estimates based on the area of a cell and the user area",
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      "content": "an octocore 6502 that can chain handle 64b is certainly a goal, as is some math coprocessor for 6502/816 etc",
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      "content": "since the tools are free you can run some experiments and get an idea of what you can do",
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      "content": "i even have a 4bit 6404 microslice design i might test out someday, as well as a coprocessor for the 6502 that increases address space and some other functions",
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      "content": "i mean, im starting on an fpga, i have some ideas for a hardware company and might try to build some custom stuff, presales/crowdsourcing etc to get funded",
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      "content": "cool",
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      "content": "does a 'smart digital drawing tablet/e-reader' need a 64bit cpu?\nwhat if it uses expired patents from the wacom intuous2 line?",
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      "content": "probably not. not a lawyer. \ud83d\ude42",
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      "content": "well, not a legal question, more a theoritical one",
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      "content": "there are some cool devices well served by simple hardware",
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      "content": "yes it could probably work on a 8 bit processor \ud83d\ude42",
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      "content": "now wafer.space just burns the silicon, it has to go to packaging afterwards?",
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      "content": "well it does wire bonding to COB if you pay a little extra",
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      "content": "but yeah it is a very minimal process",
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      "content": "notice the cost \ud83d\ude42",
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      "content": "I think if you want QFN then chipfoundary might be easier path\nhttps://chipfoundry.io/",
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      "content": "it will all depend on time, energy and money",
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      "content": "they want 15K usd",
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      "content": "yeah it is a newer process and packaging is not cheap",
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      "content": "Unless I forgot, they are (almost?) stricter on the pad ring than the WS COB seems to be, and packaging is _not_ anywhere near 150$/QFN.",
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      "content": "i mean, if i have volume its probably worth it, though they seem big around risc-v",
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      "content": "(IIRC they run the entire lot through the same packaging and just make sure they know afterwards which of the designs that share the reticle ended up in the particular QFN, such that they can keep them sorted.)",
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      "content": "WS is comparatively affordable. iirc the early bird pricing was 4$/chip @ 1k",
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      "content": "iiuc that assumes packaged via COB onto the mezzazine socketable package/board and the standard pad ring.",
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      "content": "yeah this is way cheaper",
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      "content": "per chip",
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      "content": "like, maybe i can explain... I dream of owning an electronics company. and building ruggedized electronics for hobbyists, education, farmers, truckers and the trade industry... games and art stuff.\nmy mom has this little \"50-in-1\" color video game on the back of the bathroom door. it plays pong and a racecar game and checkers and such... its like, 8bit. you can buy these a dime a dozen on 'the bay' or 'the rainforest (amazon)'\n\nnone are made i America. I want to be the guy with an American factory that makes these, and e-readers, trail computers, gps, digital logbooks for truckers, a nice 16b drawing tablet. a retro console you can hook up to modern tvs, construction site computers, AR/VR headsets, etc.\n\n\"I wanna be the guy\" ... who picks red or blue, and makes jobs for some really talented people, while building hardware and software I think it cool.",
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      "content": "so, if this is a step towards that, I still have  years until Im retirement age",
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      "content": "and Ill probably want to run this company long after that",
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      "content": "im ok, not being the biggest, most profitable. I like open hardware design.",
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      "content": "its going to take 'economy of scale' for any of it to work out at all",
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      "content": "i probably should have gone for an MBA in finance huh?",
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      "content": "ambitious..... like, a lot.",
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      "content": "yeah, so i want to start small, with some open hardware designs and sell kits",
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      "content": "i have a masters in instructional design and technology, I was a year away from a phd in computer engineering when my advisor retired",
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      "content": "im published on a paper about technical risk, the project was a simple 6502 based computer kit for education",
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      "content": "i plan to open source the design and try to market it to schools, colleges etc, hobbyists",
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      "content": "i have the parts for the prototype on my desk over there",
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      "content": "its <$100 usd, and has a lot of support on the 6502 forums",
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      "content": "beyond this, I want to improve the design to Mk2, and see if I can get it to function as a good calculator/solver",
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      "content": "maybe, in the next 2 years",
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      "content": "id recommend studying a bit of economics and maybe doing an online business course if you're dead set on this idea",
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      "content": "there are many reasons why things aren't all made in the US, most of them benefit the US more broadly",
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      "content": "yeah indeed. I have an incomplete in markov processes and I just got into a grad certificate program in nuclear nonproliferation to keep status as a degree seeking student",
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      "content": "so many people need jobs, and education is really lacking here, Im hoping to address both concerns",
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      "content": "well, you're not going to address both concerns without first knowing the stomping ground yourself",
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      "content": "if I will accept 'not making millions per year personally', I think I can stay competitive",
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      "content": "thats not really how this work",
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      "content": "yeah my bachelors is interdisciplinary studies, I took a lot of business courses in grad school too, mostly management though... I collect books and recently got a bunch of stuff on economics.. MIT opencourseware might be a good place to look for classes",
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      "content": "its more an expression of humility, and acknowlegement that manufacturing is all but dead in the US. I thnk it could see a revival though, if Im willing to compete for *market share* instead of *market dominance*, I think ive got some disruptive ideas here",
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      "content": "you cant run a business without making profit",
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      "content": "though, maybe im just being optimistic. do you have a background in business?",
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      "content": "manufacturing fights for thin margins",
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      "content": "well, a nonprofit is a business, profit is its own thing, Im not saying I want to run __this business__ as a non profit, though low margins were more what I was thinking. you cant run a business without being *solvent*, Im aiming for solvency, profit would be great.",
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      "content": "for example, we quit making tvs in America some years ago. \nto understand why, is multifold, though comes down to profit margin, it was just way cheaper to make them in mexico and china, etc. these days india is surging ahead in manufacturing.\nenvironmental regulations, workplace safety, and employee expectations are all a factor.\nthe thing I can change, is to reduce executive compensation, reduce greed, and focus on other things",
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      "content": "like, theres a guy, CEO, and instead of making millions a year, they make 70k like the rest of their managers",
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      "content": "im fine with that, if it creates a sustainable process",
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      "content": "yet I understand, my willingness to take a smaller check, is only one factor",
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      "content": "do you have much experience running or starting a business?",
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      "content": "india is surging in part because theyve been so impoverished for such a long time, and they're being massively impacted by gas shortages right now...",
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      "content": "awesome. Ive not done a lot of manufacturing. i have some grad certificates relating to entrepreneurship and innovation, though in life sciences, it was a lot of health device regulations, and a grad certificate in organization change and consulting, which is mostly management org psych. Ive run a small business off and on for decades, though mostly just me providing services to others, computer repair, web design and landscaping/lawn care\n\na far cry from manufacturing electronics, though some stuff is practical experience. like I said I was a year off from a phd in computer engineering (my advisor retired for health reasons). i do what I can here and there.",
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      "content": "i would honestly say a few courses in finance/accounting would be very close to an MBA.",
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      "content": "ive got the management and regulatory stuff, just not the money side, nor a lot on manufacturing. selling crafts on a small scale yes, not making thousands of units per week or such",
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      "content": "now I do think if I move towards used equipment, niche markets and simple designs, I might do ok",
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      "content": "ive written a few business plans and work plans over the years. \ndo you work in semiconductors?",
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      "content": "If you want open source semiconductors manufactured in the US, the ChipFoundry.io is your current only choice. \n\nwafer.space is a Singaporean company which provides access to silicon that is manufactured in Singapore by GF.",
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      "content": "If you want to build your own \"budget silicon foundry\" then you might want to check out the HackerFab group. They are doing some interesting stuff but it is more  late 1980s / early 1990s level at the moment and definitely not cost competitive for anything in volume.",
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      "content": "why open source?\ndo you just mean open access?\ni have no problem using a company in singapore, Im not sure why thats important\nat some point, if I could get my own machines in house to do this in the US, it would be really cool.",
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      "content": "Pretty sure \"open source\" here means that you get access to a PDK without having to sign NDAs, and effectively getting married to the platform",
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      "content": "gotcha, ok. its just a different use of the jargon\nmany of these platforms (small business fabrication) want you to use 'their chips' or 'their shell',, and using a template is helpful to some. I just happen to be looking for a place I can have specific control of what Im building",
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      "content": "Well, that also depends on what's in their PDK - which is also good if you can access it before signing a contract",
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      "content": "likem the ISAAC/ISAc,, its an ISA/AT-bus controller for small platforms, and it has specifc requirements, so finding a good fit is important",
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      "content": "is that 'product development kit'?",
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      "content": "process design kit?",
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      "content": "Maybe more like \"process\".  Not sure what it stands for exactly, but it's a definition of things like standard cells and all the nitty gritty that you would need in order to simulate",
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      "content": "right, so atm, to get started, today Im looking for a white label company to put my brand name on flashlights",
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      "content": "I'm not an expert on the space; just trying to answer a couple of the simpler questions.",
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      "content": "as I move forward, I have a couple of small devices that require unique silicon",
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      "content": "no totally, just a 'today I am', how Im trying to generate capital/revenue",
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      "content": "ISAAC is an 8b AT/ISA bus controller.\nit pairs with a 6502, an lcd driver (like an EVE or Epson SD chip), and similar chips\nplus we are looking for an audio driver/processor for a set of small handheld devices\n\nso Tiny Tapeout might be a good choice for that audio chip, they cant handle an ISA controller (not enough pins)\ntheir VGA experiments are rudimentary, and so wafer.space seems more our speed for a couple of these",
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      "content": "tiny tapeouot is 'very cool', they just dont have the 'oomph' in terms of capabilities for a lot of stuff.\n\nmaybe for a 4bit microslice or 8b math coprocessor, etc\nwafer.space, seems 'bigger', though its 1000 'units' at $4000+",
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      "content": "TinyTapeout is just a multi-project-per-die system for getting onto multi-project wafers. I.e. the last wafer.space run also had a TinyTapeout as one of the projects. \n\nThink of it like a multi-board PCB house, and TinyTapeout is splitting one of the boards amongst friends who are all sharing the same physical PCB",
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      "content": "meaning the wafer.space and the tinytapeout projects that ran on GF180 had the same capabilities (made in the same fab etc), just different amount of silicon to work with",
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      "content": "ok gotcha, it just seems like they are more limited overall\nanother place I looked required riscV in some manner. \nfinding the right fabricator is certainly going to be an important step.\nI just dont want to get locked into 'building for a system and its constraints'",
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      "content": "so far, wafer.space seems to be 'the most open' or 'blank slate' I can find",
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      "content": "It will be more limited mainly because you're sharing silicon and pins with other projects, yes.\n\nIf you are mostly in \"digital\" land, RTL (the programming language for hardware) is mostly portable. You can take the RTL for a RISC processor and tape it out on both Sky130 and GF180 (or TSMC 65 etc etc) without too much fuss. The trick is that most fabs require you to sign an NDA to get the process kit that lets you actually \"synthesize\" the transistors.\n\nSo without that NDA, you're limited to the handful of open fabs like Sky130, GF180, and whatever the IHP one is\n\nThat said, you're still going to have to build for a system in mind. I.e. older nodes aren't very efficient for SRAM so it ends up eating a ton of space and you're design will reflect that. Newer nodes are trickier with analog, etc etc",
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      "content": "so 'standard cells', is this like fpga LUTs?\ni see it thrown around, its ~4-20 transistors right?",
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      "content": "im a vhdl guy, and yes, a lot of this is new jargon. i think i see what yo are saying though at least to some degree",
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      "content": "a \"standard cell\" will be basic components like AND, OR, NOT, NAND etc as well as things like buffers, inverters, delay cells, flip flops. You can see the full list here for gf180: https://gf180mcu-pdk.readthedocs.io/en/latest/digital/standard_cells/standard_cells.html\n\nBut yeah each is like 3-10 transistors depending on complexity\n\nYour VHDL gets synthesized to this base list of standard cells, then OpenRoad (or proprietary software) places and routes connections to all those cells like a PCB autorouter",
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      "content": "ok, gotcha. so 'standard cell' ~= 'gate or feature'",
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      "content": "yep pretty much \ud83d\ude42 so if you switch fabs, you get a new PDK with a new set of standard cells, but the synth -> place -> route process is mostly automated. Hit recompile and essentially rebuild the same logic on a new fab process",
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      "content": "how many cells do i get for a 1x1 die?",
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      "content": "scroll down to \"Theoretical maximum standard cell density\" on the wafer.space website and Tim has some numbers, as well as real numbers from the first Run",
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      "content": "most dense real design was ~316k logic cells it looks like",
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      "content": "i found it, so it will vary based on routing/complexity",
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      "content": "yep!",
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      "content": "im getting '100k cells average' at a glance, more if you are optimized, maybe 150k",
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      "content": "so it is certainly realistic to consider \"an 8 core 6502, that has a 64b mode\"\nor similar levels of complexity.... you could put an 80386 on here ok",
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      "content": "i think this is probably a good fit for me in the long run, once I have a more concrete design.",
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      "content": "couldn't say, outside my experience \ud83d\ude42 but someone taped out a Z80, and iirc the 6502 was a really old fab node (like 10um or something?) so probably very doable. For me at least, the biggest hurdle was just SRAM size because I didn't want to deal with off-chip flash. there's gobs of space if you're just doing digital logic without much need for memory",
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      "content": "(work time, bbl!)",
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      "content": "yeah 6502 had no on chip ram, though adding some is certainly a goal",
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      "content": "have a good day, Im hunting drop shipping suppliers here for some working money",
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      "content": "Well, also keep in mind that 6502 was NMOS, not CMOS - everything nowadays is CMOS. But wafer.space does have 5V logic standard cells available.",
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      "content": "(I expect most places would concentrate on 3.3V logic and I/Os)",
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      "content": "65c02 and 65ce02 were cmos",
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      "content": "they still make the 65c02 today",
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      "content": "iu just want custom chips",
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      "content": "i should say '6502 based'",
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      "content": "Yes, I'm just mentioning it in case you were planning on making a plug-in replacement, threshold levels and so on would need to be considered",
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      "content": "no, im more looking at the ce02 variant and going my own direction while maintaing the overall Instruction Set",
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      "content": "6509 is a cool design, it had more memory/address space and better conforms to the AT bus",
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      "content": "i have a portable 8b game platform that can plug into a tv and upscale from 480x270 or so to fHD built for the 8b style of games. marketed at hobbyists, enthusiasts etc",
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      "content": "it needs either a 'full 6502 based SoC', or the ISAAC I mentioned and such",
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      "content": "im almost certain if I could fab out some 6502s (based systems) with onboard ram and better i/o I could sell a few thousand, its just getting everything lined up",
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      "content": "beyond these designs, Im looking at ML algorithms implemented in hardware, in-memory and near-memory computing etc",
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      "content": "6502 stuff is my playground though, how Ill learn the basics",
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      "content": "I finally got back to collect my bare dies!  The quarter slot ones are very small.  https://hachyderm.io/@rebelmike/116563528101924895",
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      "content": "those look so small you could accidentally inhale one",
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      "content": "You can tell I designed this back in december",
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      "content": "Is that a centurion emulator ? \ud83d\ude42",
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      "content": "EPC-co does N\"MOS\" (for practical intents it's basically a 5V node with very good support for extended drains)",
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      "content": "Yeah, I don't know all the differences, but it's just important to understand if something is being designed as replacement.",
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      "content": "I actually have plans to make a 6502 nmos in gf180. I got the original netlist remapped to gf180 transistors \ud83d\ude05   And I got it running basic instructions in a spice sims.",
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      "content": "(ok, well I'm cheating a bit, I had to remap the depletion loads as pull-ups implemented by pmos wired as diodes ... )",
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      "content": "Ok, so, gf18mcud I understand to have unusual routing density relative to transistor size that's clear when looking at routed digital standard cell section when zoomed in enough to fit only around a dozen or so cells on screen? \nI heard about as much? \n\nAnd the minimum 3.3V transistors have as minimum available threshold voltage still at healthily-low 0.53/0.63/0.73 (min/typ/max)?\n\nI really should look at how complex that lets MCML gates get without making them unusably slow...\n(I should at least get a VCO+serializer cell ready for the Run2 deadline, better hurry while there's still time.)",
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      "content": "They used negative threshold voltage nmos there?",
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      "content": "Oh they don't do it in silicon, just _on_ silicon substrates \ud83d\ude04",
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      "content": "Yeah they were using , depletion nmos.",
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      "content": "DACs work, surprisingly",
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      "content": "I assume you have opamp / buffer in the path ?",
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      "content": "On the chip, yes",
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      "content": "Not on the board ?",
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      "content": "Then yeah, I'm surprised it works because your wires were looking awefully thin for a 75R load \ud83d\ude05",
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      "content": "The opamps I built are rated for a 1Kohm load *at best*",
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      "content": "At least, according to simulation",
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      "content": "Was the sim wrong?",
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      "content": "Maybe?",
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      "content": "how do you mean, \"rated\"?\nAlso note that the screen probably does AGC and especially including shelf-based DC offset correction, by sensing the black level left and right of the painted area. That part is actually electrically trivial.",
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      "content": "Look! 24-bit color!",
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      "content": "yay",
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      "content": "(how? 8bit on-die DAC?)",
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      "content": "Something's off here",
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      "content": "On-die DAC, yeah",
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      "content": "doesn't look like analog artifacting though. Code broken?",
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      "content": "There are no latches between the combinatorial color-generating logic and the DACs, so we're seeing some intermediary states make it to the display. Wild.",
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      "content": "huh",
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      "content": "Because its analog, the signal is continuous and this can happen",
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      "content": "I question the why",
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      "content": "This also means the DACs can switch way faster than 25MHz. Incredible.",
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      "content": "assuming you have a sense of a pixel clock ofc",
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      "content": "We're seeing intermediary states as the combinatorial logic settles",
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      "content": "!",
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      "content": "I completely forgot!",
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      "content": "All of the VGA demos were build using my custom, high speed D-flip-flop standard cell",
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      "content": "Replacing the PDK\u2019s DFF",
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      "content": "is the PDK one's (that) bad?",
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      "content": "Its optimized for area, not speed",
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