============================================================== Guild: wafer.space Community Channel: Information / general Topic: Welcome to [wafer.space](https://wafer.space/) - documentation at [wafer.space github](https://github.com/wafer-space) - buy at [buy.wafer.space](https://buy.wafer.space) - archives at [discord.wafer.space](https://discord.wafer.space/) After: 04/30/2026 23:59 ============================================================== [05/01/2026 01:36] mithro_ @Noritsuna Imamura - Have you had a chance to give the ISHI bare die a probe? I would be interested to know how that goes! Please take lots of photos of your testing and share them too! I'm 100% sure others here would also be interested in your results. [05/01/2026 01:53] mithro_ From the picture - AiSi1% at 0.8mil width. Apparently the 0.8mil wire is about 5x or 10x more expensive then the typical 1.0mil width bonding wire they use. {Attachments} 2026-05_media/cob-bonding-wire-1532B.png [05/01/2026 02:10] mithro_ BTW Everyone, I still remain very interested in trying to bring back gate arrays in the form of a base device created by wafer.space that then uses a single final coarse metal layer to do the final programming of the die - see some random ideas @ http://bit.ly/ws-gatearray-v1 {Embed} http://bit.ly/ws-gatearray-v1 wafer.space - GF180MCU Gate Array (bit.ly/ws-gatearray-v1) GF180MCU Gate Array https://bit.ly/ws-gatearray-v1 Goal Create a good gate array which is programmable with post manufacturing additional of a metal layer in the 1-4um sizes. Specifications Final Metal Layer for Programming The goal is to have the gate array programmable by adding a single e... 2026-05_media/AHkbwyKaqPmC93Vc2-f176zoeWp8v7g0M9AKBsrE66-C5880 {Reactions} ๐Ÿ‘ [05/01/2026 02:22] polyfractal that's a fun idea. was thinking about laser trimming earlier today but I like this idea more [05/01/2026 02:26] noritsunaimamura We plan to conduct tests using the probe. However, we expect that preparations will take a little more time. Once the measurements are taken, we plan to report the results. [05/01/2026 03:11] mithro_ @BreakingTaps - An alternative idea is to use something like lasers to cut paths rather than metal to add paths. [05/01/2026 03:13] mithro_ @BreakingTaps - I feel like people like you, the Dr Semiconductor guy, and Hackerfab people could then do "ASICs" use these die in a few hour turn around. [05/01/2026 03:28] azonenberg yeah we have an Au ball bonder at work if we ever do a tapeout for a test project i can hand bond initial test ones {Reactions} waferspace [05/01/2026 03:39] dnaltews a little RV32 core, a splash of SRAM, UART, SPI, and gate array fabric might make an interesting little chip [05/01/2026 03:46] polyfractal Yeah this is a really compelling idea, especially since you'd have 1000 to play around with. Will do more thinking on it! [05/01/2026 03:57] mithro_ It seems like there is a lot of choice in the tiny silicon proven RISC-V cores like SERV and TinyQV and Fazy [05/01/2026 09:35] chips4makers Most structured ASICs I have seen (eASIC, Triad Semiconductor) were using via layers for the customization layer(s). Via layers should also be able to be done faster for a maskless process like ebeam litho. One idea I had was to actually start from FPGA architecture but replace the storage cells in the LUTs and the routing cells with vias. [05/01/2026 09:39] namibj any idea on how the material cost compares to the capex/machine time there? Because without it's little to go on, sadly. [05/01/2026 10:47] mithro_ This was talking about the material cost of the actual wire (according to the bond house), not anything else. [05/01/2026 10:48] namibj Yeah, I know. (It's just not at all actionable to any of us AFAIK without being able to see any perspective there.) [05/01/2026 10:49] namibj doesn't have to be for sure tho [05/01/2026 10:49] mithro_ Yes, but the current "standard" way of doing most structured ASICs / gate array devices has lead to them no longer being manufactured / killed them -- so following down that path seems like not the best idea ๐Ÿ™‚ [05/01/2026 15:37] zhekar1998 Hey folks! Quick GF180/wafer.space question: are there any usable on-chip NVM options for open submissions, like MTP/YMTP, or should I design assuming no embedded NVM and boot from external QSPI flash? Mostly looking for practical experience / gotchas, not an official commitment. Thanks! [05/01/2026 15:43] azonenberg Somebody made an OTP efuse compiler, iirc the first tapeout failed due to a missing power connection [05/01/2026 15:43] azonenberg i dont know if the next revision is back yet [05/01/2026 15:43] azonenberg but AFAIK gf supports fuses on this node [05/01/2026 15:43] azonenberg its the kind of thing you would use for trim settings not firmware [05/01/2026 16:00] zhekar1998 Oh yeah, sounds painful ๐Ÿ˜… are there any other options for rewritable NVM though? (not OTP) [05/01/2026 16:01] azonenberg Not to my knowledge. Flash etc needs a lot of extra masks that add significant cost [05/01/2026 16:01] azonenberg There may be a ROM compiler, i know folks were working on them but not sure what's been silicon proven so far [05/01/2026 16:02] azonenberg but if you need it field programmable just hang a spi flash off they're cheap [05/01/2026 16:03] zhekar1998 for me its some complicated to have 3 different flash, but for first demonstrator maybe its best option) [05/01/2026 17:12] egorxe It was me :). New revision is currently being wirebonded, so in a couple of weeks we'll see if it works. {Reactions} ๐Ÿ‘ [05/01/2026 17:49] namibj [05/01/2026 18:16] polyfractal what's the tl;dr here? Just not commercially viable vs taping out your own chip? I'm not super familiar with the history of these devices [05/01/2026 19:42] namibj AFAIK people use FPGAs and probably modern scaling's issues with leakage power discouraging from doing things the old way. {Reactions} ๐Ÿ‘ [05/01/2026 20:52] polyfractal Some photos of my COB chips {Attachments} 2026-05_media/AP1GczNsLvIhqq3bW5NvIpk9PRLMhN2czaZEgcWZID-EFBB3.png 2026-05_media/20260430_142938-DDA24.jpg 2026-05_media/20260430_160848-4D59A.jpg 2026-05_media/20260430_162031-A7440.jpg 2026-05_media/20260430_161806-3A307.jpg 2026-05_media/20260430_161850-36C20.jpg {Reactions} ๐Ÿ”ฅ (3) ๐ŸŽ‰ (6) waferspace [05/02/2026 02:38] tholin Iโ€™ve been trying to get charlib to work for me since last year, but its still crashing with impossible to interpret errors even though Iโ€™m sure Iโ€™m doing everything right {Attachments} 2026-05_media/image-D30B8.png [05/02/2026 02:42] mithro_ Very cool pictures! [05/02/2026 02:54] mithro_ My theories on why gate arrays went extinct are the following: * Gate arrays meant dealing with a silicon foundry. Once you have gone through the huge effort of dealing with a silicon foundry, then the performance improvements of going full custom seem higher ROI. * Most groups focused on trying to make gate arrays competitive with custom silicon design from a PPA rather than focus on time to market and customizability. * Foundries still wanted to own the customization step, not just the production of the starting gate array material. * Gate array refused to learn from what FPGA people where doing. * CPUs & FPGAs got a lot better. * The industry is so focused on volume and scaling that gate arrays don't make sense when you assume every project needs to sell 1 million units before it breaks even. * Maskless solutions in foundries never took off because again the industry is so focused on huge scale. * Everyone one was focused on the silicon side and did not invest in the software side. I haven't done an exhaustive search, but a lot of the gate array examples I have seen had the silicon wafers prepared to the end of FEOL and then used highest density metal for configuration. This (maybe) makes sense if you are trying to do gate arrays of transistors and form them into standard cells and SRAM blocks but also means they still take quite a long time to be made (IE O(months) rather than O(hours)). Basically, nobody was focused on: * How to I make gate arrays cheap and fast for the small run or even individual unit use case. * Providing prebuilt items like SRAM blocks, wide busses, etc. * Focused on enabling as many different solutions for programmability. [05/02/2026 04:25] egorxe I would say that gate arrays might be interesting if they'll be available with a rapid PCB prototyping kind of "programming" service. Something like a TinyTapeout, but with a turnaround time of about a week and a cost of around 200$/10 units might find its users. The gate array should have something like 20% of logic density if compared with a full custom layout on the same technology, so WS full slot based GA will be large enough to fit a decent design even with around half of the area reserved for the fixed logic like a CPU and SRAM. [05/02/2026 06:27] mithro_ @Egor Lukyanchenko - If we could prove a wafer.space die could be programmed using something like the HackerFab Stepper (which is like ~$10k USD) and each wafer.space die is $7 USD a part, then $200 USD for 10 units in 1-2 weeks kind of seems like something someone could have a small side business doing. (10*$7 == $70 USD for the die leaves $130 USD to cover the time and HackerFab stepper investment). [05/02/2026 07:08] egorxe @Tim 'mithro' Ansell > If we could prove a wafer.space die could be programmed using something like the HackerFab Stepper If the spatial resolution of the HackerFab machine for adding the top metal is known, the achievable logic density of such GA could be easily estimated. The software flow based on Yosys+OpenROAD appears to be doable, as the only truly custom step is constrained placement, which is closer to the FPGA than to ASIC. But designing a โ€œgoodโ€ GA architecture, which could achieve a reasonable density and speed, will take quite some time, I think. > (10*$7 == $70 USD for the die leaves $130 USD to cover the time and HackerFab stepper investment) That is where my 20$/piece price came from :). [05/02/2026 11:47] mithro_ Yeap, so it just needs someone to "do the work" ๐Ÿ™‚ {Reactions} ๐Ÿ™‚ [05/02/2026 13:44] dshadoff I agree - if there was a way to one-time program gate arrays (post-production), that would be popular and useful, and a good use for any excess capacity. [05/02/2026 13:49] namibj > The industry is so focused on volume and scaling that gate arrays don't make sense when you assume every project needs to sell 1 million units before it breaks even., Yeah this is overall sooooo endemic. Really hurts innovation, obviously. [05/02/2026 14:59] dorythecat_v2 afaik the biggest spenditure would actually be time, and space [05/02/2026 15:01] dorythecat_v2 You cannot guarantee a scalable chip if you don't have a reliable cleanroom, and you need to have not only the litography machine (which, granted, tens to be the most expensive machine), but also a way to bake the wafers, a way to supply said wafers, a way to deal with potentially dangerous chemicals, a way to inspect the chips, and you need to do all this with reproducibility always in mind [05/02/2026 15:03] dorythecat_v2 To be fair as they do advertise on the Hacker Fab website, they're quickly refining the process and the price to manage making low-volume chips is quickly going down [05/02/2026 15:04] dorythecat_v2 I myself know I want to make a Hacker Fab myself, for my low-volume ASICs, but I would never feel comfortable selling at any scale larger than 5 or 10 of them to individuals [05/02/2026 15:31] mithro_ I'm actually skeptical that a reliable cleanroom is needed when you are doing stuff on individual chips and something like a single 5um or 10um metal layer. Plus if you have a 1 in 10 failure rate, you have only lost like $7 USD for that failure. [05/02/2026 15:36] mithro_ A semiconductor fab wouldn't accept a 10% failure rate per metal layer because they need to do like 5 or more metal layers and on failure you just burnt a an almost complete wafer. But here you only have 1 layer to do and a failure is only negatively impacting a pretty cheap cost. [05/02/2026 15:38] dorythecat_v2 Hmmm that is fair [05/02/2026 15:38] dorythecat_v2 Afaik the Hacker Fab project actually got away with just using a plasma cleaner and execising caution [05/02/2026 15:39] dorythecat_v2 In practice a good solvent choice might even be abe to get rid of most meaningful aberrations [05/02/2026 15:39] mithro_ It's risk verse reward -- If I'm spending $X billions to build a fab, then I'm going to be a bit more demanding than if I'm just spending $10k USD ๐Ÿ™‚ [05/02/2026 15:40] dorythecat_v2 of course, that is fair! But you also have to take into account that the difference too is in the fact that the one assembling a billion-worth fab is a multibillion company, whilst the 10k fab is an individual [05/02/2026 15:41] dorythecat_v2 And the multibillion company already has a market and investors, so it can ensure that the projects will see the light of day [05/02/2026 15:41] dorythecat_v2 I can guarantee that if I also had investors and knew I'd make at least as much as I spend on making a fab setup, I would just, make the fab [05/02/2026 15:41] dorythecat_v2 But it's a bit of a risky gamble [05/02/2026 15:49] fossify_37988 Those minimal fabs try to solve this by fitting the equipment in a small, highly automated volume instead of maintaining a full cleanroom. I think you can make this idea work. [05/02/2026 15:51] dorythecat_v2 Hmmm yeah that definitely sounds like a pretty plausible idea [05/02/2026 15:51] dorythecat_v2 Yeah and the market can't be too hard to find [05/02/2026 15:52] namibj yeah single layer is not that intense cleanroom; also you just use essentially a line of laminar flow hoods; you don't need the humans in the clean part of the room [05/02/2026 15:52] mithro_ While it is a definitely a privileged position, I'm sure that there are a lot of people who have $10k spare compared to multibillion dollar companies willing to risk building semiconductor fab. [05/02/2026 15:52] dorythecat_v2 5 to 7$ for a chip, custom made with at most 6 weeks lead time, seems like a great offer I know I wouldn't pass on [05/02/2026 15:52] fossify_37988 Medical sensors need the analog capacity, and subthreshold design for ULP as well [05/02/2026 15:52] dorythecat_v2 Also small businesses might benefit from this [05/02/2026 15:53] dorythecat_v2 well there is a whole small business in and of itself [05/02/2026 15:54] fossify_37988 If we can find a way of doing heterogeneous packaging the opportunities will explode, which I know @namibj was interested in [05/02/2026 15:54] namibj hmmmm [05/02/2026 15:55] dorythecat_v2 It can probably be done by using "internal pads", kind of how PCB stacking was done during the transition to transistor logic [05/02/2026 15:56] dorythecat_v2 I've seen a few good PCBs, if on the older side, that used this to their advantage, so I don't see why it couldn't be done with silicon [05/02/2026 15:58] dorythecat_v2 My entrepenurial and experimental sides are coalescing too much over this idea and I feel the pull to make a crowdsupply campaign to try and get an "indie semiconductor fab" to be a real thing /hj [05/02/2026 16:03] namibj Share? [05/02/2026 16:04] fossify_37988 Check the link Tim sent, its something people are working on for sure [05/02/2026 16:04] dorythecat_v2 Uhhh I have one very good example on the workshop. It used to be on the innards of a locomotive when the whole thing about "electronic security" was starting to be a thing [05/02/2026 16:05] dorythecat_v2 Iirc they have various copper pillars that are bolted in between two PCBs and they're used to transmit data directly between the 2-layer PCBs [05/02/2026 16:05] dorythecat_v2 Well I say two later but it's just a one-sided copper substrate [05/02/2026 16:06] dorythecat_v2 Yeah I know and that's the thing, it's something I'm definitely interested on trying for myself anyways so might as well make my thesis and a business out of it xd [05/02/2026 16:17] mithro_ I'm trying to convince PCBA houses to offer wire bonding as part of their PCBA services which opens up a way to integrate a bunch of devices together. [05/02/2026 16:18] dorythecat_v2 Yeah the bad thing is that that would be a costly service not many at-scale clients would use [05/02/2026 16:18] dorythecat_v2 JLC for example earns most of their money off of medium-batch PCBA and large-scale PCB manufacture [05/02/2026 16:18] mithro_ PCBs where once a costly service ๐Ÿ™‚ [05/02/2026 16:18] dorythecat_v2 Everything else they offer is just either cheap to have running or can be easily made with the otherwise defunct machines involved [05/02/2026 16:19] dorythecat_v2 Yeah of course! But that didn't stop them from being popular! [05/02/2026 16:19] dorythecat_v2 Wire-bonding is still a very niche process except for very specific applications, and the companies that can afford to supply dies can already afford to bond and coat it themselves [05/02/2026 16:20] dorythecat_v2 So you try telling the JLC executives that if they drop a bunch of money at adding another service, it might be profitable after... Well, between a long time and never [05/02/2026 16:24] mithro_ @Dory - Don't know about JLC, but a number of other groups (like PCB Way) already have wire bonding machine -- they just don't offer access to those machines to non-chinese customers today because they don't have a way to do automated quoting like they can with PCB/PCBA. [05/02/2026 16:25] dorythecat_v2 Ahhh that is very fair [05/02/2026 16:25] dorythecat_v2 I wouldn't have thought that is the case, see [05/02/2026 16:25] dorythecat_v2 But then again it makes sense too [05/02/2026 16:26] dorythecat_v2 Though I'm guessing my argument for why you wouldn't do it small scale still applies [05/02/2026 16:27] dorythecat_v2 It's so costly to have a few bare dies shipped to china, pay full time engineer hours for operation of a machine that can easily take an hour to be done, and needs their full attention, and then to pot it an ensure it will last [05/02/2026 16:27] dorythecat_v2 But it'd be awesome to see it become a thing, so I'll pray for your success from the sidelines hehe [05/02/2026 16:30] namibj Workshop? [05/02/2026 16:32] namibj I'm happy the GaN are lateral devices, so unlike the SiC JFETs from (formerly) UnitedSiC, no need for silver sintering. [05/02/2026 16:35] namibj Though I should look at whether that (low temperature silver sintering) can do enough resolution to work for flip chip bonding of wafer.space dies without (much/expensive) post-processing. [05/02/2026 16:36] dorythecat_v2 Yeah I have a little workshop on the other side of town. Well it's my father's but we kinda share [05/02/2026 16:36] dorythecat_v2 It's more of a... Dump than anything else [05/02/2026 16:36] dorythecat_v2 I have a few old electronics and mechateonics stuff hanged up [05/02/2026 16:52] tholin https://github.com/AvalonSemiconductors/ws_multi_project_generator {Embed} https://github.com/AvalonSemiconductors/ws_multi_project_generator GitHub - AvalonSemiconductors/ws_multi_project_generator: A tool to... A tool to generate multi-project dies for wafer.space shuttles - AvalonSemiconductors/ws_multi_project_generator 2026-05_media/ws_multi_project_generator-8E612 {Reactions} ๐Ÿ‘ [05/02/2026 16:52] tholin Still needs docs, but it is functional [05/02/2026 16:53] tholin Allows for automatic generation of multi-project setups with all 50 GPIOs shared between the projects, up to 15 projects [05/02/2026 16:53] tholin Digital only [05/02/2026 16:54] tholin One possible application for this is it to further reduce tape-out cost by carrying multiple different peopleโ€™s projects on one die [05/02/2026 17:05] namibj [05/02/2026 17:05] namibj I'd probably be able to bankroll a single one of these dies worth of wafer.space next year if we have figured out a way to bond the gate drive current to the wafer.space die for it. I'd actually assume it should be possible to do without flip-chip but instead "just" using the kind of thick rectangular al bond "wire" they use for e.g. the TO-247 packages of the UnitedSiC Gen4 cascodes: [05/02/2026 17:06] namibj {Attachments} 2026-05_media/38314_2021_594_Fig1_HTML-FA4BD.jpg [05/02/2026 17:08] namibj That's a large SiC vertical jfet drain down with a 30V vertical silicon mosfet drain sintered to the SiC source; the SiC gate is the tiny pad off to the left; then the mosfet has a kelvin gate bonded out (two legs of the TO-247 for gate purposes, one is source the other gate) and ofc the fat source bonding for the load current. {Reactions} โค๏ธ [05/03/2026 03:28] mithro_ Very cool! I'm very on board with promoting this work and having people hiring your services to help people afford slots by sharing. [05/03/2026 03:34] mithro_ I would ***potentially*** be interested in exploring how a pattern like this on the top metal could be used for bonding directly rather than needing bond wires (IE provide free silicon if there is spare/leftover space on the shuttle). [05/03/2026 03:41] namibj non-wedge-bonding should likely be fine with active area underneath; for merely testing the flip-chip tactic(s) as-such it shouldn't really need more than.... wiring a normal IO pad to a suitably large pad in a more central location on the die? I don't know what non-customer-GDS slices you're planning to have for Run2, but later this month or possibly early next month I'd be up for making a more concrete proposal/"pitch deck" with the ESD aspects researched out for such an option/opportunity. If that's what you're approximately thinking of here? [05/03/2026 03:44] mithro_ I don't really care about being pitched too, I'm just interested in helping promote the exploration of ideas which might help reduce cost further by eliminating wire bonding and such. [05/03/2026 03:47] namibj no I mean regarding a concrete concept of how to potentially explore how such a pattern on top metal could be used for flip chip bonding, without having to dedicate the flip chip pad's top metal occupied area across all layers (e.g. it should only need a fraction of the active area underneath, unless we assume particularly advanced fine-pitch flip-chip techniques) [05/03/2026 03:48] namibj oh sorry, I again misread; I thought you said "I don't really recall being pitched to" [05/03/2026 03:51] namibj I won't have any of the analog PA things (needed to make integration with one of those GaN chips useful) ready in time for Run2, but there's other things that could be bonded to a Run2 die to trial the bonding process itself. [05/03/2026 03:51] mithro_ I also don't need to necessarily understand everything either :-). Throwing stuff against the wall and seeing what sticks is part of the idea behind trying to make things continually cheaper. [05/03/2026 03:54] mithro_ Filling the die with different types of silicon capacitors (MIM, MOS & MOM) and maybe even some efuses with a very simple 1-wire core so info about lot number, wafer number, wafer position could be burned into the device would be perfectly resonable to me. [05/03/2026 03:54] namibj Yeah, I thought to mean that for whoever would try to make more productive use of the lower layers in that area (those not used by the ESD structures), to "convince" them that this upper layer structure with a little bit of active pad structure underneath would be harmless enough to include. Could be with some new sram macro trial or something more experimental than normal slice usage, I'd assume. [05/03/2026 03:56] namibj Oh yeah it should be perfectly fine to trial efuse designs (well, EPROM as a general concept, I don't mean the specific UV-erasable variety) in the spare active area under such a pad. [05/03/2026 04:02] mithro_ Random Google doc with ideas @ https://docs.google.com/document/d/1ahoCTmPvKExYtk3qqxvjMpnq5XOcIQvVWMF84zgi82k/edit?tab=t.0 {Embed} https://docs.google.com/document/d/1ahoCTmPvKExYtk3qqxvjMpnq5XOcIQvVWMF84zgi82k/edit?tab=t.0 wafer.space - GF180MCU Silicon Capacitor GF180MCU Silicon Capacitor Goal Create software which is able to generate a "maximal silicon capacitor" for a given configuration. Specifications GDSFactory https://gdsfactory.github.io/gdsfactory/ Uses AI to tune the capacitor capacity (IE the shapes of structures). https://gdsfactory.github... 2026-05_media/AHkbwyJ3mkKHJ1Xog5XcPSWC3_N25-ihTOY7ivt3r2-9BDFD [05/03/2026 04:06] namibj in lieu of anything better I'd suggest an ice40ul1k-swg16 or a ice40up3k/ice40up5k (I heard they're the same; the former just isn't sold in the QFN48 package) {Attachments} 2026-05_media/image-49F29.png 2026-05_media/image-18EE3.png [05/03/2026 04:08] namibj but yeah silicon capacitor pinned raw out to the pads could be something; antenna diodes are used in avalanche connection to be reverse-biased in normal operation, right? [05/03/2026 04:13] namibj sorry this was the one for the up5k; the above ones were just the ultra lite vs. ultra [non-lite] {Attachments} 2026-05_media/image-D73E6.png [05/03/2026 05:16] mithro_ I'm currently working to source known-good-die of ice40up5k through my Lattice contacts. [05/03/2026 05:18] dnaltews I miss the days when those parts were $4-5 in handful quantities [05/03/2026 05:19] mithro_ @Brian Swetland - How much are they these days? I've generally gotten them at $1-$2 USD per part in the past (but I've been buying multiple full reels at a time). [05/03/2026 05:20] dnaltews looks like cut tape, single digits is $10-11 on digikey/mouser... down to $8-9 in the hundreds [05/03/2026 05:21] dnaltews I assume some combo of popularity and the parts crunch that kicked off a bit into the pandemic were contributing factors here [05/03/2026 05:22] dnaltews being able to buy 5-10 for ~$4 each was hobbyist fpga nirvana back when the yosys/nextpnr tooling was getting solid [05/03/2026 16:08] chips4makers I don't believe the reason for example eASIC in the end failed was technical but financial, e.g. investors driving it in the wrong direction. A lot of companies fail not because of technical unfitness. {Reactions} ๐Ÿ‘ (2) [05/03/2026 16:16] fossify_37988 Is there a feedback mechanism for the patterns between the dies? I am running into a problem where I need to generate data to train a model, and I don't want to grab people's work and throw it into a training dataset without explicit permission. [05/03/2026 16:46] namibj "patterns between the dies"? Can you rephrase that message, it's hard to understand what you're trying to say there. [05/03/2026 16:46] fossify_37988 There are test patterns in the spaces between the dies [05/03/2026 16:52] namibj If you don't need the extra IO get up3k (so I've heard; I'll try in some weeks, probably shortly after the Run2 deadline), the only way they could reasonably do the implied binning to lower fabric block/component availability would involve per-die PnR (even if only a reduced PnR, it's clearly gonna involve per-die bitstreams) and there's no sign in any of the dcumentation that they would burden the customers with such. At least in the open tooling I'm told it just doesn't apply the lower ressource limits, treating it essentially equivalent to a 30-ball WLCSP up5k and at worst setting a couple bits to mark the bitstream as "for up3k" to pacify possible validation. [05/03/2026 16:53] fossify_37988 you can get the latest gowin parts for a few bucks a piece, I believe they're supported by an open source toolchain [05/03/2026 21:54] polyfractal Yeah, it's actually pretty surprising what you can get away with at 1um and larger size. All my diy stuff was in open shop air and rarely had issues with particles. Solvent cleaning and thorough DI water rinses takes care of most particles at a size that matter to big features. Wouldnt be hard to automate in a little HEPA cell either. Single metal layer is just spincoater, hotplate, litho machine and sputter or evap. Man this is really tempting me ๐Ÿ˜… [05/03/2026 22:26] namibj for maskless metal I'd expect options beyond the traditional litho technique, such as perhaps laser machining. Like, the concept of laser trimming is officially supported on the gf180mcu open PDK... [05/03/2026 22:35] polyfractal Possibly, but could be a real challenge. Would probably want at least picosecond laser to limit thermal damage, and green or shorter wavelength to limit depth and focal spot size. Have to deal with debris. Have to be very careful about getting a full ablation and no shorts. End of the day might be harder than a simple 405nm direct write into resist and metal liftoff. ๐Ÿ˜• [05/03/2026 22:48] namibj Yeah. Thought picosecond sounds a little severe there, and you don't need green for spot size reasons there. Are (active, triggered) Q-switched Nd:YAG with their practical lower pulse lengths of about 5~10 ns that poorly suited to ablating "unwanted" intersections? Hmmm. Best not to get bogged down with those thoughts now though, I got a sky130 deadline to ship a bunch of MCML cells for. [05/03/2026 23:11] polyfractal Well spot size is limited by wavelength, so eventually you'll want a shorter wavelength to minimize ablation zone (even with a gaussian spot and only the middle ablating). And nanosecond pulses are deeply thermal because they are so slow, you get a ton of substrate and edge heating. In an ideal world you are in "cold" ablation regime (fs to low ps) where your breaking bonds faster than thermal diffusion I'm on the road at the moment, but can share some 1064nm ns pulse microscope shots of thin films when I get back. Hard to get sub 20um and they are very rough edges. 1064 absorption depth in Si is like a mm or something, easy to nuke other structures below the metal ๐Ÿ˜• [05/03/2026 23:13] namibj Oh hmm fair. Though I'd expect deeper penetration into substrate resulting in less damage to the substrate once/after the metal is gone. But yeah, fair, nano scale has sub-nano timescales ๐Ÿ˜„ [05/04/2026 00:24] tholin Update: will have my dies imaged with a scanning electron microscope by a hackerspace that has one. Raw dies ship out to them towards the end of next week (or this week, if youโ€™re in a timezone where its monday). [05/04/2026 02:14] mithro_ Waves silicon seductively...... {Reactions} ๐Ÿ˜‚ (2) [05/04/2026 14:09] namibj I'll clean the later version up once the looming deadlines (ttsky26a & WS Run2) stop threatening me; if anyone wants my preliminary/kinda-experimental tooling (which I'm still cooking rn, I hope it gets to jump into proper optimization/refining before Thursday 5am UTC) before then, _please **ask**_. {Attachments} 2026-05_media/extract_spice-7994D.py [05/04/2026 14:32] mithro_ For people who are interested in the state of run #1, here is a summary. Each wafer has 28 full reticle shots and a bunch of partial reticle shots which mean most designs end up with about ~34-36 full dies per wafer. The status of all 25 wafers from run #1 are: * 1 โœ• wafer was manually fully picked by Andrew, these are the sample / loose tape die people should have received. * 2 โœ• wafers where fully picked by Andrew, these are the die people should have received on a 7 inch reel. * 11 โœ• wafers had just the full reticle shots picked using an existing pick and sort house here in Singapore, meaning that we end up with 308 (11 * 28 == 308) being delivered on a wafer dicing frame and 11 โœ• "carcasses" with each about ~6 good versions of each project die on them (so another 66 chips). The carcasses will be going with Andrew to allow him to do testing on the custom die picking machine. * 6 โœ• wafers are diced but unpicked that will be going back with @Andrew Wingate to final testing of the custom die picking machine. * 1 โœ• wafer are with @stuart's alternative dicing, pick and sort house in China (~34 die). * 4 โœ• wafers where undiced and sent to people to use as display items. That should be the total 25 wafers manufactured in run #1 (which is a short run that required paid projects to be duplicated to two slots). Looking at how the numbers have finally shaken out a short run of only 25 wafers saved about 15% of the manufacturing run cost, so normal runs will be two lots -- IE 50 wafers. [05/04/2026 14:33] namibj Started a thread. [05/04/2026 14:39] anfroholic The people who don't get COB, their raw dies have shipped today. {Attachments} 2026-05_media/20260504_173439-B9292.jpg {Reactions} ๐Ÿ˜ฎ ๐Ÿ‘ [05/04/2026 14:42] 246tnt @Tim 'mithro' Ansell When will the next 11 wafers make their way to china for COB ? [05/04/2026 14:52] namibj Would it be possible/practical to have a tiny shared test harness on the reticle that would allow one (coarse?) probing contacting to that harness to the be mux'd to the individual dies pre-dicing to sort out bad dies without having to probe each one individually? Or would that not be relevant due to the large process node, very-sub-reticle sized individual dies, and the individual-die packaging allowing per-die post-packaging probing at e.g. the COB mezzanine plug? [05/04/2026 16:13] 246tnt Nothing can cross the seal ring {Reactions} โœ… [05/04/2026 18:11] namibj Me got nerdsniped. Internet says well resistor can and are occasionally used for wafer acceptance testing of like non-pinned-out bandgap references and the like? [05/04/2026 18:23] namibj (those can't power the DUT tho so it's not gonna work without "proper" pads inside the seal ring, hence COB-first test-after looking quite superior) [05/05/2026 00:36] mithro_ Well the 11 wafers don't exist anymore - they are now ~40 separate wafer dicing frames with dies mounted on them. Those have either been shipped to people who wanted only bare die or on their way to china for chip on board mounting. [05/05/2026 00:41] mithro_ GlobalFoundries puts process test structures into the margins of the reticle - this is where the "etest" data for the production run comes from -> https://docs.google.com/spreadsheets/d/10zQF_L-KsV-n5zMISB8C67llsldodtbSALWoNdpY17Y/edit?gid=940809968#gid=940809968 {Embed} https://docs.google.com/spreadsheets/d/10zQF_L-KsV-n5zMISB8C67llsldodtbSALWoNdpY17Y/edit?gid=940809968 wafer.space - WSRUN-1 - FAB3_ETEST_3SHE07245.1 2026-05_media/AHkbwyJVm0Gce5GdTasYNO7HY6s-UCaJ7ZkvZdYu-e-1A5D8 {Reactions} ๐Ÿ‘€ [05/05/2026 00:45] mithro_ Most "production scale" semiconductor chip stuff has a testing phase which is done before dicing. Creating the test harness and test routing is extremely expensive as you are generally aiming to test a whole reticle at a time. The die which fail the test generally get marked with a black dot. @bunnie will hopefully publish an interesting blog post about going through that experience recently for his BaoChip. {Reactions} ๐Ÿ‘ (3) [05/05/2026 14:49] tholin I have devastating news [05/05/2026 14:49] tholin I will not be able to bring up my chips [05/05/2026 14:49] tholin And idk when Iโ€™ll be able to [05/05/2026 14:49] tholin The dies are upside-down {Attachments} 2026-05_media/image-613E9.png {Reactions} ๐Ÿ™€ (3) [05/05/2026 14:49] tholin I donโ€™t know what to do now [05/05/2026 14:50] tholin Even if this is fixable by revision of the PCBs that the COBs plug in to, I have no money for that [05/05/2026 14:50] tholin So its gonna be a couple months, at least [05/05/2026 14:58] tholin afaik all remaining raw dies have been shipped out to me, so there is nothing that wafer.space can do on their end [05/05/2026 14:59] tholin @Tim 'mithro' Ansell If you DO still have raw dies of mine, I would be willing to pay for another set of COBs with the die rotated correctly, as I am 100% sure that this would be cheaper than me re-designing and re-building all 8 PCBs I designed for this bring-up [05/05/2026 15:01] tholin I am checking right now if the COBs as they are (flipped) are still usable [05/05/2026 15:02] tholin Nope. Theyโ€™re unusable. Power and ground are shorted to GPIOs all over the place. Most critically, two design select lines are shorted to ground, so can not be controlled. [05/05/2026 15:03] tholin If I had made the locations of the power and ground pads symmetrical in my padring layout, I would still be able to bring up one or two things today with the generic DIP breakout, but as it stands, the COBs I have are bricks. [05/05/2026 15:55] 246tnt Oh, the mosbius design on wafer space isn't public ? Can't find a link to the repo with gds and such ? [05/05/2026 16:40] tholin Who was the other person that had custom COBs? They may wanna check theirs too. [05/05/2026 16:47] 246tnt That's why I was asking about mosbius above. [05/05/2026 16:49] 246tnt Althugh when they posted their COB design they did note QR code should be in the NE corner so that should be correct. [05/05/2026 17:15] mithro_ I believe we have a bunch of your die still here at the bond house [05/05/2026 17:21] mithro_ @Tholin - I believe we should be able to get another 20 bonded for you tomorrow. So now is the right time to discover that issue. [05/05/2026 17:22] tholin Thank you [05/05/2026 17:22] tholin The PCBs are fine, you just need to somehow instruct them to rotate the die 180ยฐ [05/05/2026 17:42] tholin I wonder if a clear indicator of direction would help with preventing this in the future. Say, putting an arrow pointing outwards in one of the two remaining corners of the die, and a corresponding arrow pointing inwards on the PCB silkscreen? [05/05/2026 17:43] tholin Actually, better idea. How would people feel about a script that reads in a padring configuration from a project and generates a KiCad symbol for it? [05/05/2026 17:45] mole99 Yes, we are planning some changes around how the corners are filled. @Andrew Wingate suggested keeping the corner opposite of the QR code empty to make the orientation more visible. {Reactions} ๐Ÿ’œ [05/05/2026 17:45] mole99 That would be great :) We could even integrate it into the precheck. [05/05/2026 17:58] tholin One thing I *eventually* want to work on (no promises when) is a 3D renderer that produces images of a die as it would appear under a microscope. I donโ€™t think I can model all the quantum effects accurately, but I can approximate how things look specifically for gf180mcu. {Reactions} ๐Ÿ‘Œ [05/05/2026 17:58] tholin I realized Iโ€™m maybe the only person in here with practical experience with multiple 3D rendering techniques, so Iโ€™ve added this to my todo list. [05/05/2026 18:06] anfroholic I have been wanting to be able to make colorful images using refraction or other to generate the colors. [05/05/2026 18:07] tholin Iโ€™m experimenting with it [05/05/2026 18:07] tholin Iโ€™m preparing a layout that is just various dithering patterns in Metal5 and Metal4 {Reactions} ๐Ÿ’œ [05/05/2026 18:07] tholin To tape out on run2 [05/05/2026 18:07] tholin The amount of patterns I can do is limited due to DRC [05/05/2026 18:17] anfroholic Can't wait to see. Also Tim and I just landed in china. Tomoorw we will be visiting the bondhouse and believe you have more boards and die there @Tholin [05/05/2026 18:18] tholin Alright [05/05/2026 21:16] tholin I got this cool photo, at least {Attachments} 2026-05_media/20260505_143327-AA0CB.jpg {Reactions} ๐Ÿ‘ ๐Ÿ˜Ž [05/06/2026 07:01] 246tnt Could you still check bonding success rate checking for ESD diodes on the pins that are not shorted to GND/PWR. [05/06/2026 07:53] mithro_ @Tholin - your die are being inspected by @Andrew Wingate and @Lauri [05/06/2026 07:54] anfroholic {Attachments} 2026-05_media/rn_image_picker_lib_temp_98e5cf9a-d653-4e0-2968C.jpg {Reactions} โค๏ธ (5) [05/06/2026 07:54] mithro_ @Tholin - they are going to have like a couple 100mbs of photos of the die under different lighting and magnification for you. [05/06/2026 07:54] anfroholic Laptop cannot connect to discord from china [05/06/2026 07:54] anfroholic *GBs [05/06/2026 08:14] tholin Oh wow [05/06/2026 08:14] tholin That is going to be incredibly helpful [05/06/2026 10:42] mithro_ The verification of Tiny Tapeout GF0p2 projects can be seen at https://tinytapeout.com/chips/silicon-proven/#ttgf0p2 {Embed} https://tinytapeout.com/chips/silicon-proven/ Silicon proven projects - Tiny Tapeout Tiny Tapeout projects that have been taped out and verified in silicon. [05/06/2026 22:49] mithro_ @Tholin - Still working with @Andrew Wingate to figure out how to upload the photos somewhere. [05/06/2026 22:59] tholin How much is the total filesize combined? [05/06/2026 22:59] mithro_ @Tholin - I think about ~35G (but that includes other die captures too). [05/06/2026 23:27] tholin Ah, I see the problem [05/06/2026 23:47] namibj Make a torrent? Unless you have need for access restrictions, that is. [05/06/2026 23:53] mithro_ I think a random torrent is likely to have more issues with hotel WiFi and China internet than just using rsync to put them on a server I have. [05/06/2026 23:55] mithro_ Has anyone done simulation using the noise models in the GF180MCU PDK? If so, could you add any info you have to the thread @ https://discord.com/channels/1361349522684510449/1501344740350758992 [05/10/2026 02:20] mithro_ {Reactions} ๐ŸŽ‰ [05/10/2026 02:20] mithro_ So what can I do to get Zeptobars doing wafer.space silicon? ๐Ÿ˜› [05/10/2026 09:25] simi150500 The wafer.space gf180mcuD JKU multi-project chip is alive! ๐Ÿฅณ Last night, I wired up the DIP adapter PCB on a breadboard. I just supplied the board with 3V3 or 5V via decoupling capacitors, connected my AWG to the clock input and tied the reset input to high... and voila, the sanity bring-up test works. On one digital output, the Super Mario Bros. theme song is played via a buzzer through a PWM signal. ๐Ÿ™Œ Nothing fancy, just a quick breadboard build-up and test, but at least we can say that the chip is alive! ๐ŸŽ‰ Next, our students can come in and test their own projects. Some motivated students have also decided to build a PCB as part of a seminar work. ๐Ÿ™Œ I will also try to pour some dies into epoxy cubers. I have already received the materials for it. I just need to find some time for it. ๐Ÿ™‚ {Attachments} 2026-05_media/breadboard-64F98.mp4 2026-05_media/breadboard1-9A032.jpeg 2026-05_media/breadboard2-B5BD0.jpeg 2026-05_media/breadboard3-FC72B.jpeg {Reactions} ๐ŸŽ‰ (4) ๐Ÿฅณ [05/10/2026 09:38] mole99 Started a thread. [05/10/2026 10:27] mithro_ That is very cool! {Reactions} ๐Ÿ™Œ (2) [05/10/2026 13:31] tholin Iโ€™ve characterized my SCL at the ss_125C_3v00 corner, so all three corners are now done {Reactions} ๐Ÿ‘ (3) [05/10/2026 13:33] tholin Iโ€™m thinking of doing a 4th characterization at ss_080C_3v10 since that default slowest corner is kindof extreme. I donโ€™t think anybody here needs their chips to be running at 125ยฐC, so Iโ€™d like to offer an alternative maximum constraint of "just" 80ยฐC at 3.1V [05/10/2026 13:34] tholin So people can aim for a higher fmax at the tradeoff of a more constrained temperature and voltage range that the part is speced for. [05/10/2026 13:35] tholin (Iโ€™m pretty sure at 125ยฐC you start having other problems, like the epoxy on the COB melting) [05/11/2026 10:53] egorxe Hi, @Tholin! Thanks for your amazing work on 3.3V SCL! Do you plan to extend your library? Because if you do, I would like to ask you to add some kind of delay cell to improve hold fixing. Currently I have problems with increasing a hold margin for my Caravel port, which I would like to do for safety. OpenROAD generates thousands of buffer cells but with only ~100ps delay each it has a hard time and takes a huge area. [05/11/2026 12:40] tholin Iโ€™m currently working on making it easier for people to collaborate to the repo [05/11/2026 12:40] tholin Iโ€™m just one person, unfortunately [05/11/2026 12:48] mole99 A delay buffer appears to be simply two buffers in a trench coat, where the first three inverters have a narrow gate width. You might even want to experiment with the gate length for even larger delays. See here: https://gf180mcu-pdk.readthedocs.io/en/latest/digital/standard_cells/gf180mcu_fd_sc_mcu7t5v0/cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_1.html Adjusting Tholin's buffers would probably be a good start. {Reactions} ๐Ÿ‘ [05/11/2026 15:49] tholin Building SCL releases is now fully automated {Attachments} 2026-05_media/image-6CD5E.png {Reactions} ๐ŸŽ‰ (5) [05/11/2026 15:49] tholin {Attachments} 2026-05_media/image-3F73B.png [05/11/2026 15:50] tholin Just need to figure out how to actually generated repo releases from the actions output [05/11/2026 15:50] tholin Stretch goal: verify the SCL by building an example project as part of the pipeline [05/11/2026 15:50] tholin Currently blocked by LVS still locking up with the SCL [05/11/2026 22:22] wayfarer.technologies so help me out here... can I build an octocore 6502 with 64b addressing? [05/11/2026 22:22] wayfarer.technologies will that work here? [05/11/2026 22:22] wayfarer.technologies or similar 'weird stuff'? [05/11/2026 22:25] _mwelling_ the limitations are your imagination and silicon area [05/11/2026 22:26] _mwelling_ well that and money to pay to a slot on the shuttle [05/11/2026 22:27] _mwelling_ someone implemented 6502 on tinytapeout: https://tinytapeout.com/chips/ttihp26a/tt_um_chrismoos_6502_mcu {Embed} https://tinytapeout.com/chips/ttihp26a/tt_um_chrismoos_6502_mcu 163 m6502 Microcontroller - Tiny Tapeout Complete 6502 CPU with bus multiplexer, GPIO, Timer, and UART 2026-05_media/social-preview-2C419 [05/11/2026 22:27] wayfarer.technologies ok, so im only limited by pads (pins) and available 'cells'/transistors? [05/11/2026 22:28] _mwelling_ yeah pretty much [05/11/2026 22:28] wayfarer.technologies aye, I was talking to those guys, speed is limited to ~33mhz and a small number of pins [05/11/2026 22:28] _mwelling_ that and the knowhow to implement all of the things [05/11/2026 22:28] wayfarer.technologies i need 80-120 pins, and want to hit 800-1200mhz [05/11/2026 22:29] _mwelling_ I think the pad ring is not that big [05/11/2026 22:29] wayfarer.technologies it said 56-120+ pads [05/11/2026 22:30] wayfarer.technologies on the website, so im not sure if we mean different things, perhaps some are multiplexed [05/11/2026 22:30] _mwelling_ yeah the default isn't that big [05/11/2026 22:30] wayfarer.technologies im not sure yet [05/11/2026 22:30] wayfarer.technologies just getting some conceptual boundaries [05/11/2026 22:30] _mwelling_ you are on your own if you don't use the default [05/11/2026 22:30] wayfarer.technologies ok, 'can I make the whole thing SRAM'? [05/11/2026 22:30] _mwelling_ sure [05/11/2026 22:31] wayfarer.technologies how many 'cells'? [05/11/2026 22:31] wayfarer.technologies or transistors do i get? [05/11/2026 22:32] _mwelling_ depends on a lot of things [05/11/2026 22:34] _mwelling_ @Tim 'mithro' Ansell or @tnt might have some approximate numbers [05/11/2026 22:37] _mwelling_ https://mithro.github.io/gf180mcu-project-template/ [05/11/2026 22:38] kris____ there's some information here total cells used/% area used: https://github.com/wafer-space/ws-run1/blob/density-report/reticle_density_report.md {Embed} https://github.com/wafer-space/ws-run1/blob/density-report/reticle_density_report.md ws-run1/reticle_density_report.md at density-report ยท wafer-space/... wafer.space GF180MCU Run 1. Contribute to wafer-space/ws-run1 development by creating an account on GitHub. 2026-05_media/ws-run1-9B3DC [05/11/2026 22:39] fangameempire TIny Tapeout projects also show the number of cells used in the GDS github action [05/11/2026 22:39] _mwelling_ {Attachments} 2026-05_media/image-66358.png [05/11/2026 22:39] fangameempire Here's mine as an example for Tiny Tapeout https://github.com/FangameEmpire/ttsky26a_spacewar/actions/runs/25696603247 2200 cells ~= 70% of two tiles {Embed} https://github.com/FangameEmpire/ttsky26a_spacewar/actions/runs/25696603247 Merge bullet tests back into main ยท FangameEmpire/ttsky26a_spacewa... A scaled-down version of the classic PDP-1 game on a VGA display. - Merge bullet tests back into main ยท FangameEmpire/ttsky26a_spacewar@f151f17 2026-05_media/ttsky26a_spacewar-E9C06 [05/11/2026 22:40] fangameempire Or do you mean wafer.space as a whole [05/11/2026 22:40] _mwelling_ all of this is on the main page {Attachments} 2026-05_media/image-D8C6B.png [05/11/2026 22:43] dorythecat_v2 Read the little text down below [05/11/2026 22:44] dorythecat_v2 Those are theoretical, using the standard cells included in the temolate [05/11/2026 22:44] _mwelling_ not sure what you are expecting? [05/11/2026 22:45] dorythecat_v2 Oh sorry I am very sleepy and thought you were wayfarer [05/11/2026 22:45] dorythecat_v2 Wow I really need either new glasses or a few more than eight hours of sleep [05/11/2026 22:45] dorythecat_v2 Again really sorry [05/11/2026 22:45] _mwelling_ it is fine just giving the basic idea [05/11/2026 22:46] wayfarer.technologies looks like its fine for some basic ideas. creating a large sram array with embedded processor is not trivial however [05/11/2026 22:47] wayfarer.technologies i wasnt sure if the SRAM listed was 'if its all ram' or in addition to some other components [05/11/2026 22:48] wayfarer.technologies i have some 65xx variations/other architectures im interested in developing, including ML algorithms in vhdl [05/11/2026 22:48] _mwelling_ yeah those are estimates based on the area of a cell and the user area [05/11/2026 22:49] wayfarer.technologies an octocore 6502 that can chain handle 64b is certainly a goal, as is some math coprocessor for 6502/816 etc [05/11/2026 22:50] _mwelling_ since the tools are free you can run some experiments and get an idea of what you can do [05/11/2026 22:50] wayfarer.technologies i even have a 4bit 6404 microslice design i might test out someday, as well as a coprocessor for the 6502 that increases address space and some other functions [05/11/2026 22:51] wayfarer.technologies i mean, im starting on an fpga, i have some ideas for a hardware company and might try to build some custom stuff, presales/crowdsourcing etc to get funded [05/11/2026 22:52] _mwelling_ cool [05/11/2026 22:52] wayfarer.technologies does a 'smart digital drawing tablet/e-reader' need a 64bit cpu? what if it uses expired patents from the wacom intuous2 line? [05/11/2026 22:53] _mwelling_ probably not. not a lawyer. ๐Ÿ™‚ [05/11/2026 23:01] wayfarer.technologies well, not a legal question, more a theoritical one [05/11/2026 23:01] wayfarer.technologies there are some cool devices well served by simple hardware [05/11/2026 23:03] _mwelling_ yes it could probably work on a 8 bit processor ๐Ÿ™‚ [05/11/2026 23:05] wayfarer.technologies now wafer.space just burns the silicon, it has to go to packaging afterwards? [05/11/2026 23:05] _mwelling_ well it does wire bonding to COB if you pay a little extra [05/11/2026 23:06] _mwelling_ but yeah it is a very minimal process [05/11/2026 23:07] _mwelling_ notice the cost ๐Ÿ™‚ [05/11/2026 23:09] _mwelling_ I think if you want QFN then chipfoundary might be easier path https://chipfoundry.io/ {Embed} https://chipfoundry.io/ ChipFoundry ChipFoundry 2026-05_media/hj0vk05j0kemus1i-B05D9.png [05/11/2026 23:13] wayfarer.technologies it will all depend on time, energy and money [05/11/2026 23:14] wayfarer.technologies they want 15K usd [05/11/2026 23:17] _mwelling_ yeah it is a newer process and packaging is not cheap [05/11/2026 23:33] namibj Unless I forgot, they are (almost?) stricter on the pad ring than the WS COB seems to be, and packaging is _not_ anywhere near 150$/QFN. [05/11/2026 23:33] wayfarer.technologies i mean, if i have volume its probably worth it, though they seem big around risc-v [05/11/2026 23:35] namibj (IIRC they run the entire lot through the same packaging and just make sure they know afterwards which of the designs that share the reticle ended up in the particular QFN, such that they can keep them sorted.) [05/11/2026 23:35] namibj WS is comparatively affordable. iirc the early bird pricing was 4$/chip @ 1k [05/11/2026 23:36] namibj iiuc that assumes packaged via COB onto the mezzazine socketable package/board and the standard pad ring. [05/11/2026 23:39] _mwelling_ yeah this is way cheaper [05/11/2026 23:39] _mwelling_ per chip [05/11/2026 23:39] wayfarer.technologies like, maybe i can explain... I dream of owning an electronics company. and building ruggedized electronics for hobbyists, education, farmers, truckers and the trade industry... games and art stuff. my mom has this little "50-in-1" color video game on the back of the bathroom door. it plays pong and a racecar game and checkers and such... its like, 8bit. you can buy these a dime a dozen on 'the bay' or 'the rainforest (amazon)' none are made i America. I want to be the guy with an American factory that makes these, and e-readers, trail computers, gps, digital logbooks for truckers, a nice 16b drawing tablet. a retro console you can hook up to modern tvs, construction site computers, AR/VR headsets, etc. "I wanna be the guy" ... who picks red or blue, and makes jobs for some really talented people, while building hardware and software I think it cool. [05/11/2026 23:40] wayfarer.technologies so, if this is a step towards that, I still have years until Im retirement age [05/11/2026 23:40] wayfarer.technologies and Ill probably want to run this company long after that [05/11/2026 23:41] wayfarer.technologies im ok, not being the biggest, most profitable. I like open hardware design. [05/11/2026 23:41] wayfarer.technologies its going to take 'economy of scale' for any of it to work out at all [05/11/2026 23:42] wayfarer.technologies i probably should have gone for an MBA in finance huh? [05/11/2026 23:49] namibj ambitious..... like, a lot. [05/11/2026 23:56] wayfarer.technologies yeah, so i want to start small, with some open hardware designs and sell kits [05/11/2026 23:56] wayfarer.technologies i have a masters in instructional design and technology, I was a year away from a phd in computer engineering when my advisor retired [05/11/2026 23:57] wayfarer.technologies im published on a paper about technical risk, the project was a simple 6502 based computer kit for education [05/11/2026 23:57] wayfarer.technologies i plan to open source the design and try to market it to schools, colleges etc, hobbyists [05/11/2026 23:58] wayfarer.technologies i have the parts for the prototype on my desk over there [05/11/2026 23:58] wayfarer.technologies its <$100 usd, and has a lot of support on the 6502 forums [05/11/2026 23:59] wayfarer.technologies beyond this, I want to improve the design to Mk2, and see if I can get it to function as a good calculator/solver [05/11/2026 23:59] wayfarer.technologies maybe, in the next 2 years [05/12/2026 00:00] fossify_37988 id recommend studying a bit of economics and maybe doing an online business course if you're dead set on this idea [05/12/2026 00:00] fossify_37988 there are many reasons why things aren't all made in the US, most of them benefit the US more broadly [05/12/2026 00:01] wayfarer.technologies yeah indeed. I have an incomplete in markov processes and I just got into a grad certificate program in nuclear nonproliferation to keep status as a degree seeking student [05/12/2026 00:01] wayfarer.technologies so many people need jobs, and education is really lacking here, Im hoping to address both concerns [05/12/2026 00:02] fossify_37988 well, you're not going to address both concerns without first knowing the stomping ground yourself [05/12/2026 00:02] wayfarer.technologies if I will accept 'not making millions per year personally', I think I can stay competitive [05/12/2026 00:03] fossify_37988 thats not really how this work [05/12/2026 00:03] wayfarer.technologies yeah my bachelors is interdisciplinary studies, I took a lot of business courses in grad school too, mostly management though... I collect books and recently got a bunch of stuff on economics.. MIT opencourseware might be a good place to look for classes [05/12/2026 00:04] wayfarer.technologies its more an expression of humility, and acknowlegement that manufacturing is all but dead in the US. I thnk it could see a revival though, if Im willing to compete for *market share* instead of *market dominance*, I think ive got some disruptive ideas here [05/12/2026 00:05] fossify_37988 you cant run a business without making profit [05/12/2026 00:05] wayfarer.technologies though, maybe im just being optimistic. do you have a background in business? [05/12/2026 00:05] fossify_37988 manufacturing fights for thin margins {Reactions} ferristhumbsup [05/12/2026 00:06] wayfarer.technologies well, a nonprofit is a business, profit is its own thing, Im not saying I want to run __this business__ as a non profit, though low margins were more what I was thinking. you cant run a business without being *solvent*, Im aiming for solvency, profit would be great. [05/12/2026 00:09] wayfarer.technologies for example, we quit making tvs in America some years ago. to understand why, is multifold, though comes down to profit margin, it was just way cheaper to make them in mexico and china, etc. these days india is surging ahead in manufacturing. environmental regulations, workplace safety, and employee expectations are all a factor. the thing I can change, is to reduce executive compensation, reduce greed, and focus on other things [05/12/2026 00:09] wayfarer.technologies like, theres a guy, CEO, and instead of making millions a year, they make 70k like the rest of their managers [05/12/2026 00:10] wayfarer.technologies im fine with that, if it creates a sustainable process [05/12/2026 00:10] wayfarer.technologies yet I understand, my willingness to take a smaller check, is only one factor [05/12/2026 00:10] wayfarer.technologies do you have much experience running or starting a business? [05/12/2026 00:38] fossify_37988 yes [05/12/2026 00:39] fossify_37988 india is surging in part because theyve been so impoverished for such a long time, and they're being massively impacted by gas shortages right now... [05/12/2026 00:42] wayfarer.technologies awesome. Ive not done a lot of manufacturing. i have some grad certificates relating to entrepreneurship and innovation, though in life sciences, it was a lot of health device regulations, and a grad certificate in organization change and consulting, which is mostly management org psych. Ive run a small business off and on for decades, though mostly just me providing services to others, computer repair, web design and landscaping/lawn care a far cry from manufacturing electronics, though some stuff is practical experience. like I said I was a year off from a phd in computer engineering (my advisor retired for health reasons). i do what I can here and there. [05/12/2026 00:43] wayfarer.technologies i would honestly say a few courses in finance/accounting would be very close to an MBA. [05/12/2026 00:44] wayfarer.technologies ive got the management and regulatory stuff, just not the money side, nor a lot on manufacturing. selling crafts on a small scale yes, not making thousands of units per week or such [05/12/2026 00:44] wayfarer.technologies now I do think if I move towards used equipment, niche markets and simple designs, I might do ok [05/12/2026 00:45] wayfarer.technologies ive written a few business plans and work plans over the years. do you work in semiconductors? [05/12/2026 06:59] mithro_ If you want open source semiconductors manufactured in the US, the ChipFoundry.io is your current only choice. wafer.space is a Singaporean company which provides access to silicon that is manufactured in Singapore by GF. [05/12/2026 07:01] mithro_ If you want to build your own "budget silicon foundry" then you might want to check out the HackerFab group. They are doing some interesting stuff but it is more late 1980s / early 1990s level at the moment and definitely not cost competitive for anything in volume. {Reactions} ๐Ÿ‘ (2) [05/12/2026 15:04] wayfarer.technologies why open source? do you just mean open access? i have no problem using a company in singapore, Im not sure why thats important at some point, if I could get my own machines in house to do this in the US, it would be really cool. [05/12/2026 15:18] dshadoff Pretty sure "open source" here means that you get access to a PDK without having to sign NDAs, and effectively getting married to the platform [05/12/2026 15:22] wayfarer.technologies gotcha, ok. its just a different use of the jargon many of these platforms (small business fabrication) want you to use 'their chips' or 'their shell',, and using a template is helpful to some. I just happen to be looking for a place I can have specific control of what Im building [05/12/2026 15:23] dshadoff Well, that also depends on what's in their PDK - which is also good if you can access it before signing a contract [05/12/2026 15:23] wayfarer.technologies likem the ISAAC/ISAc,, its an ISA/AT-bus controller for small platforms, and it has specifc requirements, so finding a good fit is important [05/12/2026 15:24] wayfarer.technologies is that 'product development kit'? [05/12/2026 15:24] wayfarer.technologies process design kit? [05/12/2026 15:25] dshadoff Maybe more like "process". Not sure what it stands for exactly, but it's a definition of things like standard cells and all the nitty gritty that you would need in order to simulate [05/12/2026 15:26] wayfarer.technologies right, so atm, to get started, today Im looking for a white label company to put my brand name on flashlights [05/12/2026 15:26] dshadoff I'm not an expert on the space; just trying to answer a couple of the simpler questions. [05/12/2026 15:26] wayfarer.technologies as I move forward, I have a couple of small devices that require unique silicon [05/12/2026 15:27] wayfarer.technologies no totally, just a 'today I am', how Im trying to generate capital/revenue [05/12/2026 15:30] wayfarer.technologies ISAAC is an 8b AT/ISA bus controller. it pairs with a 6502, an lcd driver (like an EVE or Epson SD chip), and similar chips plus we are looking for an audio driver/processor for a set of small handheld devices so Tiny Tapeout might be a good choice for that audio chip, they cant handle an ISA controller (not enough pins) their VGA experiments are rudimentary, and so wafer.space seems more our speed for a couple of these [05/12/2026 15:31] wayfarer.technologies tiny tapeouot is 'very cool', they just dont have the 'oomph' in terms of capabilities for a lot of stuff. maybe for a 4bit microslice or 8b math coprocessor, etc wafer.space, seems 'bigger', though its 1000 'units' at $4000+ [05/12/2026 15:33] polyfractal TinyTapeout is just a multi-project-per-die system for getting onto multi-project wafers. I.e. the last wafer.space run also had a TinyTapeout as one of the projects. Think of it like a multi-board PCB house, and TinyTapeout is splitting one of the boards amongst friends who are all sharing the same physical PCB [05/12/2026 15:34] polyfractal meaning the wafer.space and the tinytapeout projects that ran on GF180 had the same capabilities (made in the same fab etc), just different amount of silicon to work with [05/12/2026 15:37] wayfarer.technologies ok gotcha, it just seems like they are more limited overall another place I looked required riscV in some manner. finding the right fabricator is certainly going to be an important step. I just dont want to get locked into 'building for a system and its constraints' [05/12/2026 15:39] wayfarer.technologies so far, wafer.space seems to be 'the most open' or 'blank slate' I can find [05/12/2026 15:41] polyfractal It will be more limited mainly because you're sharing silicon and pins with other projects, yes. If you are mostly in "digital" land, RTL (the programming language for hardware) is mostly portable. You can take the RTL for a RISC processor and tape it out on both Sky130 and GF180 (or TSMC 65 etc etc) without too much fuss. The trick is that most fabs require you to sign an NDA to get the process kit that lets you actually "synthesize" the transistors. So without that NDA, you're limited to the handful of open fabs like Sky130, GF180, and whatever the IHP one is That said, you're still going to have to build for a system in mind. I.e. older nodes aren't very efficient for SRAM so it ends up eating a ton of space and you're design will reflect that. Newer nodes are trickier with analog, etc etc [05/12/2026 15:41] wayfarer.technologies so 'standard cells', is this like fpga LUTs? i see it thrown around, its ~4-20 transistors right? [05/12/2026 15:43] wayfarer.technologies im a vhdl guy, and yes, a lot of this is new jargon. i think i see what yo are saying though at least to some degree [05/12/2026 15:45] polyfractal a "standard cell" will be basic components like AND, OR, NOT, NAND etc as well as things like buffers, inverters, delay cells, flip flops. You can see the full list here for gf180: https://gf180mcu-pdk.readthedocs.io/en/latest/digital/standard_cells/standard_cells.html But yeah each is like 3-10 transistors depending on complexity Your VHDL gets synthesized to this base list of standard cells, then OpenRoad (or proprietary software) places and routes connections to all those cells like a PCB autorouter [05/12/2026 15:46] wayfarer.technologies ok, gotcha. so 'standard cell' ~= 'gate or feature' [05/12/2026 15:46] polyfractal yep pretty much ๐Ÿ™‚ so if you switch fabs, you get a new PDK with a new set of standard cells, but the synth -> place -> route process is mostly automated. Hit recompile and essentially rebuild the same logic on a new fab process [05/12/2026 15:47] wayfarer.technologies how many cells do i get for a 1x1 die? [05/12/2026 15:48] polyfractal scroll down to "Theoretical maximum standard cell density" on the wafer.space website and Tim has some numbers, as well as real numbers from the first Run [05/12/2026 15:49] polyfractal most dense real design was ~316k logic cells it looks like [05/12/2026 15:50] wayfarer.technologies i found it, so it will vary based on routing/complexity [05/12/2026 15:50] polyfractal yep! [05/12/2026 15:50] wayfarer.technologies im getting '100k cells average' at a glance, more if you are optimized, maybe 150k [05/12/2026 15:51] wayfarer.technologies so it is certainly realistic to consider "an 8 core 6502, that has a 64b mode" or similar levels of complexity.... you could put an 80386 on here ok [05/12/2026 15:52] wayfarer.technologies i think this is probably a good fit for me in the long run, once I have a more concrete design. [05/12/2026 15:56] polyfractal couldn't say, outside my experience ๐Ÿ™‚ but someone taped out a Z80, and iirc the 6502 was a really old fab node (like 10um or something?) so probably very doable. For me at least, the biggest hurdle was just SRAM size because I didn't want to deal with off-chip flash. there's gobs of space if you're just doing digital logic without much need for memory [05/12/2026 15:56] polyfractal (work time, bbl!) [05/12/2026 15:56] wayfarer.technologies yeah 6502 had no on chip ram, though adding some is certainly a goal [05/12/2026 15:57] wayfarer.technologies have a good day, Im hunting drop shipping suppliers here for some working money [05/12/2026 16:06] dshadoff Well, also keep in mind that 6502 was NMOS, not CMOS - everything nowadays is CMOS. But wafer.space does have 5V logic standard cells available. [05/12/2026 16:06] dshadoff (I expect most places would concentrate on 3.3V logic and I/Os) [05/12/2026 16:06] wayfarer.technologies 65c02 and 65ce02 were cmos [05/12/2026 16:06] wayfarer.technologies they still make the 65c02 today [05/12/2026 16:06] wayfarer.technologies iu just want custom chips [05/12/2026 16:07] wayfarer.technologies i should say '6502 based' [05/12/2026 16:07] dshadoff Yes, I'm just mentioning it in case you were planning on making a plug-in replacement, threshold levels and so on would need to be considered [05/12/2026 16:08] wayfarer.technologies no, im more looking at the ce02 variant and going my own direction while maintaing the overall Instruction Set [05/12/2026 16:08] wayfarer.technologies 6509 is a cool design, it had more memory/address space and better conforms to the AT bus [05/12/2026 16:09] wayfarer.technologies i have a portable 8b game platform that can plug into a tv and upscale from 480x270 or so to fHD built for the 8b style of games. marketed at hobbyists, enthusiasts etc [05/12/2026 16:10] wayfarer.technologies it needs either a 'full 6502 based SoC', or the ISAAC I mentioned and such [05/12/2026 16:11] wayfarer.technologies im almost certain if I could fab out some 6502s (based systems) with onboard ram and better i/o I could sell a few thousand, its just getting everything lined up [05/12/2026 16:11] wayfarer.technologies beyond these designs, Im looking at ML algorithms implemented in hardware, in-memory and near-memory computing etc [05/12/2026 16:12] wayfarer.technologies 6502 stuff is my playground though, how Ill learn the basics [05/12/2026 20:48] rebelmike I finally got back to collect my bare dies! The quarter slot ones are very small. https://hachyderm.io/@rebelmike/116563528101924895 {Embed} Mike Bell https://hachyderm.io/@rebelmike/116563528101924895 Mike Bell (@rebelmike@hachyderm.io) Attached: 1 image I received some silicon from wafer space run 1! These are just for display purposes - weโ€™re still working on getting a board together to allow some to be bonded. But they are a version of my TinyQV SoC in a โ€œquarter sizeโ€ wafer space slot. 2026-05_media/eb3de0b8c7d22d36-583B1.jpeg {Reactions} ๐Ÿ‘ (2) ๐ŸŽ‰ [05/13/2026 08:30] ravenslofty those look so small you could accidentally inhale one [05/13/2026 09:00] rebelmike Yes, they are tiny! [05/13/2026 14:24] tholin Update: the dies are right side up this time {Attachments} 2026-05_media/as03-161A7.mp4 {Reactions} ๐ŸŽ‰ (4) [05/13/2026 14:24] tholin You can tell I designed this back in december [05/13/2026 14:29] 246tnt Is that a centurion emulator ? ๐Ÿ™‚ [05/13/2026 14:58] namibj EPC-co does N"MOS" (for practical intents it's basically a 5V node with very good support for extended drains) [05/13/2026 15:01] dshadoff Yeah, I don't know all the differences, but it's just important to understand if something is being designed as replacement. [05/13/2026 15:03] 246tnt I actually have plans to make a 6502 nmos in gf180. I got the original netlist remapped to gf180 transistors ๐Ÿ˜… And I got it running basic instructions in a spice sims. [05/13/2026 15:04] 246tnt (ok, well I'm cheating a bit, I had to remap the depletion loads as pull-ups implemented by pmos wired as diodes ... ) [05/13/2026 15:11] namibj Ok, so, gf18mcud I understand to have unusual routing density relative to transistor size that's clear when looking at routed digital standard cell section when zoomed in enough to fit only around a dozen or so cells on screen? I heard about as much? And the minimum 3.3V transistors have as minimum available threshold voltage still at healthily-low 0.53/0.63/0.73 (min/typ/max)? I really should look at how complex that lets MCML gates get without making them unusably slow... (I should at least get a VCO+serializer cell ready for the Run2 deadline, better hurry while there's still time.) [05/13/2026 15:11] namibj They used negative threshold voltage nmos there? [05/13/2026 15:12] namibj Oh they don't do it in silicon, just _on_ silicon substrates ๐Ÿ˜„ [05/13/2026 15:12] 246tnt Yeah they were using , depletion nmos. [05/13/2026 15:16] tholin DACs work, surprisingly {Attachments} 2026-05_media/20260513_171529-0CDB5.jpg 2026-05_media/20260513_171532-26FF2.jpg [05/13/2026 15:19] 246tnt I assume you have opamp / buffer in the path ? [05/13/2026 15:19] tholin On the chip, yes [05/13/2026 15:20] 246tnt Not on the board ? [05/13/2026 15:20] 246tnt Then yeah, I'm surprised it works because your wires were looking awefully thin for a 75R load ๐Ÿ˜… [05/13/2026 15:34] tholin The opamps I built are rated for a 1Kohm load *at best* [05/13/2026 15:34] tholin At least, according to simulation [05/13/2026 15:34] tholin Was the sim wrong? [05/13/2026 15:34] tholin Maybe? [05/13/2026 16:13] namibj how do you mean, "rated"? Also note that the screen probably does AGC and especially including shelf-based DC offset correction, by sensing the black level left and right of the painted area. That part is actually electrically trivial. [05/13/2026 16:13] tholin Look! 24-bit color! {Attachments} 2026-05_media/20260513_181242-71F4F.jpg {Reactions} ๐ŸŽ‰ [05/13/2026 16:13] namibj yay [05/13/2026 16:13] namibj (how? 8bit on-die DAC?) [05/13/2026 16:13] tholin Something's off here {Attachments} 2026-05_media/20260513_181250-2508F.jpg [05/13/2026 16:13] tholin On-die DAC, yeah [05/13/2026 16:14] namibj doesn't look like analog artifacting though. Code broken? [05/13/2026 16:15] tholin There are no latches between the combinatorial color-generating logic and the DACs, so we're seeing some intermediary states make it to the display. Wild. [05/13/2026 16:15] namibj huh [05/13/2026 16:15] tholin Because its analog, the signal is continuous and this can happen [05/13/2026 16:15] namibj I question the why [05/13/2026 16:16] tholin This also means the DACs can switch way faster than 25MHz. Incredible. [05/13/2026 16:16] namibj assuming you have a sense of a pixel clock ofc [05/13/2026 16:16] tholin We're seeing intermediary states as the combinatorial logic settles [05/13/2026 16:23] tholin ! [05/13/2026 16:23] tholin I completely forgot! [05/13/2026 16:23] tholin All of the VGA demos were build using my custom, high speed D-flip-flop standard cell {Reactions} ๐ŸŽ‰ (2) [05/13/2026 16:23] tholin Replacing the PDKโ€™s DFF [05/13/2026 16:23] tholin I did not even realize it was working this whole time [05/13/2026 16:39] namibj is the PDK one's (that) bad? [05/13/2026 17:04] tholin Its optimized for area, not speed [05/13/2026 17:04] tholin So it depends on what your needs are [05/13/2026 17:06] tholin The NTSC video generator also works {Attachments} 2026-05_media/20260513_185907-72D80.jpg 2026-05_media/20260513_185915-A8B0E.jpg {Reactions} ๐Ÿ‘ [05/13/2026 17:06] tholin All the gray levels! {Attachments} 2026-05_media/20260513_185949-17C2A.jpg [05/13/2026 17:07] tholin It should also be able to do PAL, I'll test that next [05/13/2026 17:07] tholin But this is a VERY cheap video out option [05/13/2026 17:07] tholin A single analog pin and the little area for the DAC [05/13/2026 17:19] namibj a single? you mean for the composite mode? [05/13/2026 17:20] tholin Its only greyscale video [05/13/2026 18:06] tholin I am using my GFMPW-1 chip to help bring up this one. I think that means I've come full circle. {Attachments} 2026-05_media/20260513_200605-B1627.jpg ============================================================== Exported 432 message(s) ==============================================================