wafer.space Community

Helo (edited)

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@Leo Moser (mole99) @Tim 'mithro' Ansell Spammer to ban ...

ewen

https://support.discord.com/hc/en-us/articles/205369668-How-do-I-set-up-a-Role-Exclusive-announcements-channel Tl;DR: set up group of users who are to have permissions to post announcements, change channel permissions to remove "send message" from the "Everyone" group, and add "send message" permission for the group of users that should be allowed to post.

^^^^ perhaps it'd be a good idea to limit who can post to #welcome-and-rules, #announcements etc, so that at least the spam doesn't end up there? (Howto link in the message I'm replying to, from February 2026.)

2

tnt

@Leo Moser (mole99) @Tim 'mithro' Ansell Spammer to ban ...

Thanks

ewen

^^^^ perhaps it'd be a good idea to limit who can post to #welcome-and-rules, #announcements etc, so that at least the spam doesn't end up there? (Howto link in the message I'm replying to, from February 2026.)

@Tim 'mithro' Ansell

ewen

https://support.discord.com/hc/en-us/articles/205369668-How-do-I-set-up-a-Role-Exclusive-announcements-channel Tl;DR: set up group of users who are to have permissions to post announcements, change channel permissions to remove "send message" from the "Everyone" group, and add "send message" permission for the group of users that should be allowed to post.

I think I've make that happen for the #welcome-and-rules and #announcements channels now?

@Noritsuna Imamura - Cool to see you updated the repo @ https://github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1 with pictures of the real die!

GitHub - ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1: IS...

ISHI-KAI's Multiple Projects Wafer for Wafer.Sapce GF180 Run 1. - ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1

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Tim 'mithro' Ansell

I think I've make that happen for the #welcome-and-rules and #announcements channels now?

LGTM. In #welcome-and-rules I now see "you do not have permission to post" and in #announcements I see "follow for updates in your server" (which is the normal "this is a read-only announcements channel). Thanks for sorting that out.

I had a bit of an idea

What was the max ram/cache we can have?

A full die* with the new (untested) 3v3 SRAM is like 44-54 KB depending on how much padding you include for routing.. The 5v SRAM is like 21-24 KB iirc *inside the pad ring. You can probably fit more with a custom pad ring. (edited)

5:05 p.m.

(and that's the entire usable die area filled with sram macros, and basically no space for logic)

Ok. So still too small for full addressing of a 6502(64k)

5:20 a.m.

Im wanting to test something like, a 'minicpu' spaced every few hundred MB of RAM

Can we have dram? Would we get more?

5:43 a.m.

I guess sram is better... And I could structure a 6502 core to use a large amount of on die ram cache, and still use external address space. Not sure yet. I guess the ram makers have their own tricks

Wayfarer

Can we have dram? Would we get more?

Using external COTS PSRAM is probably the easist option. Atleast one person has done a external SRAM interface.

Yeah PSRAM and "HyperRAM"/octal PSRAM should be pretty straightforward. They are all SPI, QuadSPI or a small parallel interface. I was looking at SDRAM chips but the need like 50 pins and are much more involved with refreshes and such

Hirosh's SoC uses an external SDRAM

https://github.com/splinedrive/gf180mcu-kianv-rv32ima-sv32

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Tim 'mithro' Ansell

Using external COTS PSRAM is probably the easist option. Atleast one person has done a external SRAM interface.

Thanks, the notion is a "minicpu" every few MB of RAM, so a massively distributed system across a multi GB array. Prototyping this at small scale may be advantageous. My other notion is to put a 6502, 6522 and a ton of cache on a single die. Then have external connections to other memory and devices. (Mmio based architecture)

2:27 a.m.

I think I'll focus on the later for now, as well as my "geometric" computer/coprocessor.

2:27 a.m.

Thanks

So, because a 6502 with megabytes of ram is impractical at this point, I'm going to focus on a math coprocessor for the 6502 family.

4:28 p.m.

I also have an isa bus dma control chip I'm working on. If there is volume, can we get a discount?

4:30 p.m.

Oh. You get 1000 chips here. Ok.

4:30 p.m.

That actually works out to less than $10 a chip yeah?

4:31 p.m.

So totally worth a crowd funding campaign. And a 6502 math coprocessor would probably sell well

Wayfarer

So totally worth a crowd funding campaign. And a 6502 math coprocessor would probably sell well

You're not gonna crowd fund your first ASIC tapeout with that as the goal.

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namibj

You're not gonna crowd fund your first ASIC tapeout with that as the goal.

You seem confident in this statement.

4:44 p.m.

I don't appreciate the discouraging words. Take care.

The problem is that testing is HARD and without experience the risk of the dies being DoA is substantial. And in that scenario it'd be the crowd that suffers. If you can use appropriate techniques to mitigate that risk it'd be fine.

Wayfarer

I don't appreciate the discouraging words. Take care.

Namibj is right. Additionally, if you want to sell, you need to find market fit first

There is a massive 6502 community that will support a reasonably priced coprocessor

That's not really what I'm talking about

8:07 p.m.

It's hard to sell even 1000 units of something, and you need to sell for way, way more than the cost of the chips if the goal is to make money

Solvency is important

8:08 p.m.

I'm happy to break even

Break even will still be above $100/chip though

Like, you can technically do it but it's unlikely you find something that's straight forward enough to be both low enough tapeout risk and enough market to fill that volume. There's a reason AFAIK zero of the Run2 slots are crowd funded if you don't count tiny tapeout which works differently as it's not a "product".

Especially on my first few rounds

Wayfarer

Especially on my first few rounds

You need to be prepared to not break even for several iterations

Christopher

Break even will still be above $100/chip though

Counting your own hours or how are you that pessimistic?

What level of verification is offered here?

8:09 p.m.

Surely there is some testing and simulation

Wayfarer

What level of verification is offered here?

Whatever you do yourself.

namibj

Counting your own hours or how are you that pessimistic?

Hours, ATE, market research, distribution, documentation, etc

Verilator and Xyce will help you.

Christopher

Hours, ATE, market research, distribution, documentation, etc

"ATE"?

Hi. I’m currently on my third attempt to tape out a digital approximation of the SID in GlobalFoundries silicon and I still have yet to get it right. Its not easy. I suggest using TinyTapeout for prototyping.

Oh functional testing gear/setup?

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TT is on my list

8:13 p.m.

What is cost per chip, packaged?

8:13 p.m.

Ready to solder or mount in a socket?

Wayfarer

What is cost per chip, packaged?

$6 for cost of manufacturing alone

8:15 p.m.

(half width)

That on a PCB with pins or vias?

Yeah, thats bonded on CoB

8:17 p.m.

That doesnt include the rest of the pcb to make it work, just to attach it to something else without diy wirebonding

Chip on board?

Yes

Kk

8:17 p.m.

I can sell these for $20

You wont break even at $20

My users would jump at these

Not for only 1k units

It's 3x what you just said

Yes, thats literally just for manufacturing lol

I'll do the VHDL myself

Your NREs and overhead are not included in that

Nre?

Oh boy

Not sure what that abbreviation is

https://www.7pcb.com/blog/nre-tooling-costs

Non-Recurring Engineering (NRE) and Tooling Costs - Bittele Electro...

At Bittele, we understand the importance of transparency concerning PCB manufacturing and assembly costs, including what they cover in production expenses and how they can be minimized to your benefit.

Christopher

Your NREs and overhead are not included in that

Tbf the power cost for openlane on spare HW isn't that substantial... And at that quantity shipping doesn't have to be that much. It's still ambitious to break even on "retail" with that, though.

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Ok. Thanks. That's an odd abbreviation to me. Appreciate you.

This is aimed at PCBs, you have all the other design + v/v and documentation stuff on top of that

$20+shipping is reasonable

Wayfarer

Ok. Thanks. That's an odd abbreviation to me. Appreciate you.

Yeah you're definitely not gonna crowd fund this tapeout this year if you're doing this anywhere close to alone.

Probably not this year, no

Learn get experience then do it though!

Dev will be a long time coming. Then marketing

8:23 p.m.

I might have ,80% of the VHDL and an fpga by end of year

How many PCBs with >=4 layers have you designed and gotten manufactured?

I'm not a PCB designer

8:24 p.m.

I write VHDL

Wayfarer

I'm not a PCB designer

How are you going to test your chips

I don't think you're crowdfunding alone next year, but if you find someone to respect the "hardware hard" part of such a project, it could happen.

Christopher

How are you going to test your chips

Breadboard right now. I am planning to tinker with PCB, I prefer to stay focused on vlsi

8:26 p.m.

6502 are pretty simple to work with (edited)

8:26 p.m.

Such is why it's chosen

Wayfarer

Such is why it's chosen

Yeah tho the market for play gadgets is not large especially such types. I'm looking forward to trying to use a tall half slot to drive a couple parallel EPC-co GaN "mosfets" (5V gate drive, very fast) in optically controlled floating nature (the mosfets are directly attached to the gf180mcuD die, that controller is optically communicating with a central brain) for stacking the mosfet modules in series for more voltage. That requires them to be carefully driven to switch all together or one module will see too much drain voltage and immediately blow a crater into the GaN die from the resulting avalanche discharge. But it also should be efficient and fast, hence the reach for an ASIC that can provide per-"mosfet"-die tuned gate drive waveforms to a DAC and then an integrated efficiency-optimized (very distorting) amplifier that drives the actual "mosfet" gate. It's just not really done otherwise, because who'd willingly burden themselves with such severe dV/dt (in other words, such high frequencies at those spicy voltages). The only thing I know that goes near that is the inbuilt rectifier/voltage multiplier of a CRT flyback transformer. And that's barely still audible to mildly ultrasonic, not several MHz.

9:14 p.m.

Shy of specialty things that need/want integration, few things actually want this type of process taped out. I good you can replace some smaller FPGA applications, at the cost of programmability.

The CoB option gives you a breakout to a mezzanine connector. You will need another assembled PCB to adapt this to DIP. Then, you need to factor in costs for shipping and import duties (of the parts to you), VAT, probably other taxes and business upkeep costs, shipping (to the customers) and, for international customers (which you will have in this market) even more duties and tariffs! $20 is not realistic.

9:17 p.m.

I played with the idea of selling my chips extensively, but gave up on doing it alone (for now)

9:18 p.m.

US tariffs are particularly brutal right now, which is what ultimately made me go "Nah, screw this"

Tholin

I played with the idea of selling my chips extensively, but gave up on doing it alone (for now)

I think there are some niches where it could make sense, especially because you have access to those LDMOS fets

Tholin

The CoB option gives you a breakout to a mezzanine connector. You will need another assembled PCB to adapt this to DIP. Then, you need to factor in costs for shipping and import duties (of the parts to you), VAT, probably other taxes and business upkeep costs, shipping (to the customers) and, for international customers (which you will have in this market) even more duties and tariffs! $20 is not realistic.

I got a batch of 50 boards with voltage regulator capacitors and one LGA package fabbed at JLC around last Christmas for 25€ each of which iirc like 16€ each was that LGA. At QTY 1k and unless I missed some new tariffs it'd be possibly to get DIP'd w.s. COBs into domestic bubble mailers and posted, unless that e-waste recycling law happens to get in the way there, not sure I'm not selling retail. But yeah it'd be barely and no profit.

Christopher

I think there are some niches where it could make sense, especially because you have access to those LDMOS fets

Especially once we figure an economic flip chip "power stage contacts" packaging.

9:29 p.m.

(Inductance mainly.)

I do wonder how companies like THAT can produce their chips relatively affordably on tiny (~100 mm) wafers

Christopher

I do wonder how companies like THAT can produce their chips relatively affordably on tiny (~100 mm) wafers

What kinda chips?

Audio

9:31 p.m.

Same with Sound Semiconductor, but I believe they're fabless

9:31 p.m.

https://cabintechglobal.com/ssi2130 for ex

Ahhh hmmm

https://thatcorp.com/that-6261-6263-6266-dual-low-noise-programmable-gain-preamplifier-adc-driver-ic/

cksong

THAT 6261/6263/6266 Dual Low Noise Programmable-Gain Preamplifier-A...

regarding pricing, I just ordered some PCB + assembly to test my chip a little easier than breadboard. Relatively simple 4 layer board (micro, headers, few level shifters, caps, resistors, only expensive part was a PSRAM module), moderate size.

$17.90 for 5pc
$159.75 for assembly
$46.47 for shipping
$78.84 for tariffs and taxes

all up that's $60 per board, plus $8.5 for the chip and COB. At qty 1000 and a better PCB that price could be brought down. But to hit $20 price point for PCB + chip COB, you'd probably have to assemble your own and keep the board ultra simple (edited)

Christopher

https://thatcorp.com/that-6261-6263-6266-dual-low-noise-programmable-gain-preamplifier-adc-driver-ic/

Ehhhh, look at parallax propeller 2 for example, that's 130nm on semi "fabless" and fairly big (iirc the die could fit about 1.2~1.5 MiB SRAM from it's area; they only have 512 kiB shared plus 8 cores @4 kiB local each, but it's extremely powerful IO wise. E.g. each core could drive individual 180~250 MHz pixel clock VGA (256 pallet or fixed LUT optional, but it could sustain true color just no framebuffer to match). Each GPIO (64 of them) has 3 8-bit DACs, one 3ns VGA-class, ~123 Ohm, one ~600 Ohm, and one iirc ~15 kOhm (that one is used for the level comparator and some select related feedback modes of the pad "drivers"). It literally lets you set (sadly only 4 bit resolution) a "high" and a "low" code for the fast DAC to use for digital GPIO output state emission, so you can directly handle e.g. 1.2V CMOS levels, together with the input comparator.

BreakingTaps

regarding pricing, I just ordered some PCB + assembly to test my chip a little easier than breadboard. Relatively simple 4 layer board (micro, headers, few level shifters, caps, resistors, only expensive part was a PSRAM module), moderate size.

$17.90 for 5pc
$159.75 for assembly
$46.47 for shipping
$78.84 for tariffs and taxes

all up that's $60 per board, plus $8.5 for the chip and COB. At qty 1000 and a better PCB that price could be brought down. But to hit $20 price point for PCB + chip COB, you'd probably have to assemble your own and keep the board ultra simple (edited)

Where in that breakdown are the "misc" components? The *assembly cost"?

9:48 p.m.

Propeller 2 is 12$ in quantity

9:49 p.m.

(last I looked)

9:50 p.m.

It's by far the fanciest "GPIO pad" of any microcontroller. (edited)

namibj

Where in that breakdown are the "misc" components? The *assembly cost"?

yeah lumped into assembly cost. Lemme find the BOM vs actual assembly breakdown

BreakingTaps

yeah lumped into assembly cost. Lemme find the BOM vs actual assembly breakdown

Just checking otherwise I'd have called out your choice of expensive assembly.

9:53 p.m.

I should sleep now.

some of this would fall under NRE that amortizes over a lot of parts for sure, just expensive at such low quantity.

9:56 p.m.

but yeah, cost is mostly not the physical PCB or components. all in assembly, fixturing, setup fees, non-standard parts being loaded etc

Fancy board to need fixture

‍♂️ I'm a PCB newbie and just yolo'd it, but it is double sided so that's probably why

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Ohh yeah

My serv based chip from run 1 is toggling GPIOs. With the help of a sacrificial iCEBreaker board (FTDI + QSPI + 12MHz oscillator already populated and connected)

8

4

3:24 a.m.

Greg

My serv based chip from run 1 is toggling GPIOs. With the help of a sacrificial iCEBreaker board (FTDI + QSPI + 12MHz oscillator already populated and connected)

what that chip (good) for?

An experiment with the serv + spram wrapper. It's an array of 23 seperate cores, plus some basic peripherals. A SPI loader on boot pre-loads each cores memory. (the above trace)

Greg

An experiment with the serv + spram wrapper. It's an array of 23 seperate cores, plus some basic peripherals. A SPI loader on boot pre-loads each cores memory. (the above trace)

Sorry, "serv" is too generic a term to make me confident to Google it and get the right thing. Got a link perhaps or such?

https://github.com/olofk/serv

GitHub - olofk/serv: SERV - The SErial RISC-V CPU

SERV - The SErial RISC-V CPU. Contribute to olofk/serv development by creating an account on GitHub.

Ahh sorry. Yes, not very googlable. "SErial Risc V" CPU.

Are the commands for manually running klayout DRC and antenna rule check on a GDSII file documented anywhere?

Leo Moser (mole99) started a thread. 2026-06-09 4:31 p.m.

Leo Moser (mole99)

As for why it is the way it currently is, you would have to ask Mabrains as they created the original rule deck :) What I found in the docs:

https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_03.html

3.4 Consistent layout all designs on a 0.005μm grid will avoid off-grid and snapping issues during database fracturing.

https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_02.html

The design grid must be an integer multiple of 0.005μm.

Given the wording of the second statement, and that DRC errors in the design can lead to a back and forth with GF, it is probably safer and simpler to assume that all shapes on all layers need to be on the 5nm grid. As for the angle checks, I would actually love to be able to draw arbitrary angles (except for acute and as long as all points are on-grid). However, given the wording in the docs I'm not sure about this.

https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_05_1.html

SH.2: Avoid any COMP, poly and metal shapes with acute angles (angles <90 deg). Exceptions are only for pre-tested metal inductors with IND_MK mark layers and lettering (non circuit elements).

This would tell me that arbitrary angles (except acute) are allowed on these layers. However this is contradicted by: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_03.html

3.6 Only 90 deg and 45 deg bends are allowed for poly and metal lines.

I wouldn't even dare to guess what this means for other layers

‍♂️

"pre-tested metal inductors"? Do we have any? SH.1 says circular inductors are theoretically supported?

namibj

"pre-tested metal inductors"? Do we have any? SH.1 says circular inductors are theoretically supported?

As far as I know, no. However, we might see some inductors with 45-degree angles taped out on ws-run #2.

Leo Moser (mole99)

As far as I know, no. However, we might see some inductors with 45-degree angles taped out on ws-run #2.

If I can cook some suitable ones in the next few hours I expect to use some simple and some T-coil ones in the serializer. Would be nice to have those much sharper clock edges at the final MUX.

This seems like it might easily enough be adapted to our (gf18mcuD instead of that file's SG13G2) layer stack and would unlock generic "linear network" PEX one could hook up to SPICE (Xyce's easy way seems locked to harmonic balance aka large-signal (non-linear, with harmonics and intermodulation!) AC, but it shouldn't be too hard to make an analog behavioral model out of it (README.md "The resulting S-parameters can be used for simulation, but you can also extract a narrowband lumped element pi model using the pi-from-s2p tool.")) workflow/run_generic_nport.py:

# Model comments
# 
# This is a generic model running port excitation for all ports defined below, 
# to get full [S] matrix data.
# Output is stored to Touchstone S-parameter file. 
# No data plots are created by this script.

SG13G2.xml

5.52 KB

@Ghaith Al Sabagh has already ported the XML to gf180mcuD for the IEEE Chipathon. He will tape out some inductors on ws-run #2.

Hi @namibj You would find the needed xml files for openEMS and palace AWS here: https://github.com/EngGhaith/The-Silent-Owl-GF180MCU-WB-LNA/tree/main/EM-Flow

The-Silent-Owl-GF180MCU-WB-LNA/EM-Flow at main · EngGhaith/The-Sil...

The Silent Owl is an open-source LNA designed in GF180MCU for Chipathon 2026 - EngGhaith/The-Silent-Owl-GF180MCU-WB-LNA

Ghaith Al Sabagh

Hi @namibj You would find the needed xml files for openEMS and palace AWS here: https://github.com/EngGhaith/The-Silent-Owl-GF180MCU-WB-LNA/tree/main/EM-Flow

Ohh great! Are there any inductors already designed for that 2.4 GHz target I could maybe use as stand-in reference for my 2.5 GHz (design target, looks possible with (either) minor peaking into the final 4:1 MUX or (alternatively) employing 3-tap FIR between the mux node and the limiting amplifier acting as pre-driver for a current-mode adjustable-current (FIR tap) output driver (the tap's "PA")) clock tree buffers? Before specializing any further on serializer architecture and speed; I'd like to have physically feasible clock signal reference waveforms for designing (2:1 and the final 4:1) MUX cells, latch cells, and then doing a bit of floorplan "preliminary PnR" to know that overall design can fit into the ttgf0p3 tile I got.

https://ieeexplore.ieee.org/document/11092168 ahh, yes, paywalls but it does sound like it has already scripted the port interfacing stuffs between OpenEMS and Xyce there, and it kinda sounds like they're bypassing the native Xyce limitation of it's YLIN device.

Hmm I synthesized our design with AS 3v3 SCL, and it synthesized a dfxtp_4 cell but it isn't in the Verilog models

the _4 is just drive strength though?

Jason Yang

Hmm I synthesized our design with AS 3v3 SCL, and it synthesized a dfxtp_4 cell but it isn't in the Verilog models

You can open an issue or pull request in this repository: https://github.com/AvalonSemiconductors/gf180mcu_as_sc_mcu7t3v3

Leo Moser (mole99)

You can open an issue or pull request in this repository: https://github.com/AvalonSemiconductors/gf180mcu_as_sc_mcu7t3v3

opened up an issue

namibj

the _4 is just drive strength though?

I believe you have to duplicate the Verilog cell model for each drive strength as well

The new KLayout DRC setup is not messing around, I see

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Needs more ram consumption

I found it worthwhile to run proper DRC jobs by spinning up an AWS r6i.2xlarge instance (8 vCPU, 64 GiB memory) -- it's $0.5 / hr in us-east-1 on demand, and my (fairly complex, analog) design generally takes <30 minutes. It's all scripted to spin up, copy over the changes to test, execute, wait to retrieve logs, and turn off. I kept hitting OOM issues on my (18GiB) laptop, 40 minutes in, so these sanity checks are worth the quarter per validation for me.

3

dmv

I found it worthwhile to run proper DRC jobs by spinning up an AWS r6i.2xlarge instance (8 vCPU, 64 GiB memory) -- it's $0.5 / hr in us-east-1 on demand, and my (fairly complex, analog) design generally takes <30 minutes. It's all scripted to spin up, copy over the changes to test, execute, wait to retrieve logs, and turn off. I kept hitting OOM issues on my (18GiB) laptop, 40 minutes in, so these sanity checks are worth the quarter per validation for me.

yeah I'm so lucky I got plenty spare ram in my workstation

1

Kind of unrelated to wafer.space, but I can't seem to open Magic with OpenGL as the display driver.

7:42 p.m.

I'm using Magic bundled with the current flake in the project template

7:43 p.m.

Cairo and X11 works fine