============================================================== Guild: wafer.space Community Channel: Information / general Topic: Welcome to [wafer.space](https://wafer.space/) - documentation at [wafer.space github](https://github.com/wafer-space) - buy at [buy.wafer.space](https://buy.wafer.space) - archives at [discord.wafer.space](https://discord.wafer.space/) After: 2026-05-31 11:59 p.m. Before: 2026-07-01 12:00 a.m. ============================================================== [2026-06-01 6:39 p.m.] .pogeg Helo {Reactions} 👋 (2) [2026-06-03 9:42 a.m.] 246tnt @Leo Moser (mole99) @Tim 'mithro' Ansell Spammer to ban ... [2026-06-03 9:47 a.m.] ewenmcneill ^^^^ perhaps it'd be a good idea to limit who can post to #welcome-and-rules, #announcements etc, so that at least the spam doesn't end up there? (Howto link in the message I'm replying to, from February 2026.) {Reactions} 💯 (2) [2026-06-03 9:58 a.m.] mole99 Thanks [2026-06-03 9:58 a.m.] mole99 @Tim 'mithro' Ansell [2026-06-04 12:08 a.m.] mithro_ I think I've make that happen for the #welcome-and-rules and #announcements channels now? [2026-06-04 12:52 a.m.] mithro_ @Noritsuna Imamura - Cool to see you updated the repo @ https://github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1 with pictures of the real die! {Embed} https://github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1 GitHub - ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1: IS... ISHI-KAI's Multiple Projects Wafer for Wafer.Sapce GF180 Run 1. - ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1 2026-06_media/ISHI-KAI_Multiple_Projects_WaferSapce-GF18-50CAA {Reactions} 😎 (2) 💜 [2026-06-04 6:59 a.m.] ewenmcneill LGTM. In #welcome-and-rules I now see "you do not have permission to post" and in #announcements I see "follow for updates in your server" (which is the normal "this is a read-only announcements channel). Thanks for sorting that out. [2026-06-05 4:26 p.m.] wayfarer.technologies I had a bit of an idea [2026-06-05 4:36 p.m.] wayfarer.technologies What was the max ram/cache we can have? [2026-06-05 5:03 p.m.] polyfractal A full die* with the new (untested) 3v3 SRAM is like 44-54 KB depending on how much padding you include for routing.. The 5v SRAM is like 21-24 KB iirc *inside the pad ring. You can probably fit more with a custom pad ring. [2026-06-05 5:05 p.m.] polyfractal (and that's the entire usable die area filled with sram macros, and basically no space for logic) [2026-06-06 5:19 a.m.] wayfarer.technologies Ok. So still too small for full addressing of a 6502(64k) [2026-06-06 5:20 a.m.] wayfarer.technologies Im wanting to test something like, a 'minicpu' spaced every few hundred MB of RAM [2026-06-06 5:41 a.m.] wayfarer.technologies Can we have dram? Would we get more? [2026-06-06 5:43 a.m.] wayfarer.technologies I guess sram is better... And I could structure a 6502 core to use a large amount of on die ram cache, and still use external address space. Not sure yet. I guess the ram makers have their own tricks [2026-06-06 6:53 a.m.] mithro_ Using external COTS PSRAM is probably the easist option. Atleast one person has done a external SRAM interface. [2026-06-06 3:40 p.m.] polyfractal Yeah PSRAM and "HyperRAM"/octal PSRAM should be pretty straightforward. They are all SPI, QuadSPI or a small parallel interface. I was looking at SDRAM chips but the need like 50 pins and are much more involved with refreshes and such [2026-06-06 3:51 p.m.] mole99 Hirosh's SoC uses an external SDRAM 👌 https://github.com/splinedrive/gf180mcu-kianv-rv32ima-sv32 {Reactions} 👍 [2026-06-07 2:26 a.m.] wayfarer.technologies Thanks, the notion is a "minicpu" every few MB of RAM, so a massively distributed system across a multi GB array. Prototyping this at small scale may be advantageous. My other notion is to put a 6502, 6522 and a ton of cache on a single die. Then have external connections to other memory and devices. (Mmio based architecture) [2026-06-07 2:27 a.m.] wayfarer.technologies I think I'll focus on the later for now, as well as my "geometric" computer/coprocessor. [2026-06-07 2:27 a.m.] wayfarer.technologies Thanks [2026-06-08 4:27 p.m.] wayfarer.technologies So, because a 6502 with megabytes of ram is impractical at this point, I'm going to focus on a math coprocessor for the 6502 family. [2026-06-08 4:28 p.m.] wayfarer.technologies I also have an isa bus dma control chip I'm working on. If there is volume, can we get a discount? [2026-06-08 4:30 p.m.] wayfarer.technologies Oh. You get 1000 chips here. Ok. [2026-06-08 4:30 p.m.] wayfarer.technologies That actually works out to less than $10 a chip yeah? [2026-06-08 4:31 p.m.] wayfarer.technologies So totally worth a crowd funding campaign. And a 6502 math coprocessor would probably sell well [2026-06-08 4:37 p.m.] namibj You're not gonna crowd fund your first ASIC tapeout with that as the goal. {Reactions} 👍 [2026-06-08 4:44 p.m.] wayfarer.technologies You seem confident in this statement. [2026-06-08 4:44 p.m.] wayfarer.technologies I don't appreciate the discouraging words. Take care. [2026-06-08 5:05 p.m.] namibj The problem is that testing is HARD and without experience the risk of the dies being DoA is substantial. And in that scenario it'd be the crowd that suffers. If you can use appropriate techniques to mitigate that risk it'd be fine. [2026-06-08 8:04 p.m.] fossify_37988 Namibj is right. Additionally, if you want to sell, you need to find market fit first [2026-06-08 8:05 p.m.] wayfarer.technologies There is a massive 6502 community that will support a reasonably priced coprocessor [2026-06-08 8:05 p.m.] fossify_37988 That's not really what I'm talking about [2026-06-08 8:07 p.m.] fossify_37988 It's hard to sell even 1000 units of something, and you need to sell for way, way more than the cost of the chips if the goal is to make money [2026-06-08 8:07 p.m.] wayfarer.technologies Solvency is important [2026-06-08 8:08 p.m.] wayfarer.technologies I'm happy to break even [2026-06-08 8:08 p.m.] fossify_37988 Break even will still be above $100/chip though [2026-06-08 8:08 p.m.] namibj Like, you can technically do it but it's unlikely you find something that's straight forward enough to be both low enough tapeout risk and enough market to fill that volume. There's a reason AFAIK zero of the Run2 slots are crowd funded if you don't count tiny tapeout which works differently as it's not a "product". [2026-06-08 8:08 p.m.] wayfarer.technologies Especially on my first few rounds [2026-06-08 8:08 p.m.] fossify_37988 You need to be prepared to not break even for several iterations [2026-06-08 8:09 p.m.] namibj Counting your own hours or how are you that pessimistic? [2026-06-08 8:09 p.m.] wayfarer.technologies What level of verification is offered here? [2026-06-08 8:09 p.m.] wayfarer.technologies Surely there is some testing and simulation [2026-06-08 8:09 p.m.] namibj Whatever you do yourself. [2026-06-08 8:09 p.m.] fossify_37988 Hours, ATE, market research, distribution, documentation, etc [2026-06-08 8:10 p.m.] namibj Verilator and Xyce will help you. [2026-06-08 8:10 p.m.] namibj "ATE"? [2026-06-08 8:11 p.m.] tholin Hi. I’m currently on my third attempt to tape out a digital approximation of the SID in GlobalFoundries silicon and I still have yet to get it right. Its not easy. I suggest using TinyTapeout for prototyping. [2026-06-08 8:11 p.m.] namibj Oh functional testing gear/setup? {Reactions} 👍 [2026-06-08 8:12 p.m.] wayfarer.technologies TT is on my list [2026-06-08 8:13 p.m.] wayfarer.technologies What is cost per chip, packaged? [2026-06-08 8:13 p.m.] wayfarer.technologies Ready to solder or mount in a socket? [2026-06-08 8:14 p.m.] fossify_37988 $6 for cost of manufacturing alone [2026-06-08 8:15 p.m.] fossify_37988 (half width) [2026-06-08 8:15 p.m.] wayfarer.technologies That on a PCB with pins or vias? [2026-06-08 8:16 p.m.] fossify_37988 Yeah, thats bonded on CoB [2026-06-08 8:17 p.m.] fossify_37988 That doesnt include the rest of the pcb to make it work, just to attach it to something else without diy wirebonding [2026-06-08 8:17 p.m.] wayfarer.technologies Chip on board? [2026-06-08 8:17 p.m.] fossify_37988 Yes [2026-06-08 8:17 p.m.] wayfarer.technologies Kk [2026-06-08 8:17 p.m.] wayfarer.technologies I can sell these for $20 [2026-06-08 8:18 p.m.] fossify_37988 You wont break even at $20 [2026-06-08 8:18 p.m.] wayfarer.technologies My users would jump at these [2026-06-08 8:18 p.m.] fossify_37988 Not for only 1k units [2026-06-08 8:18 p.m.] wayfarer.technologies It's 3x what you just said [2026-06-08 8:18 p.m.] fossify_37988 Yes, thats literally just for manufacturing lol [2026-06-08 8:18 p.m.] wayfarer.technologies I'll do the VHDL myself [2026-06-08 8:18 p.m.] fossify_37988 Your NREs and overhead are not included in that [2026-06-08 8:18 p.m.] wayfarer.technologies Nre? [2026-06-08 8:19 p.m.] fossify_37988 Oh boy [2026-06-08 8:19 p.m.] wayfarer.technologies Not sure what that abbreviation is [2026-06-08 8:20 p.m.] fossify_37988 https://www.7pcb.com/blog/nre-tooling-costs {Embed} https://www.7pcb.com/blog/nre-tooling-costs Non-Recurring Engineering (NRE) and Tooling Costs - Bittele Electro... At Bittele, we understand the importance of transparency concerning PCB manufacturing and assembly costs, including what they cover in production expenses and how they can be minimized to your benefit. [2026-06-08 8:21 p.m.] namibj Tbf the power cost for openlane on spare HW isn't that substantial... And at that quantity shipping doesn't have to be that much. It's still ambitious to break even on "retail" with that, though. {Reactions} 👍 [2026-06-08 8:21 p.m.] wayfarer.technologies Ok. Thanks. That's an odd abbreviation to me. Appreciate you. [2026-06-08 8:21 p.m.] fossify_37988 This is aimed at PCBs, you have all the other design + v/v and documentation stuff on top of that [2026-06-08 8:22 p.m.] wayfarer.technologies $20+shipping is reasonable [2026-06-08 8:22 p.m.] namibj Yeah you're definitely not gonna crowd fund this tapeout this year if you're doing this anywhere close to alone. [2026-06-08 8:22 p.m.] wayfarer.technologies Probably not this year, no [2026-06-08 8:22 p.m.] namibj Learn get experience _then_ do it though! [2026-06-08 8:22 p.m.] wayfarer.technologies Dev will be a long time coming. Then marketing [2026-06-08 8:23 p.m.] wayfarer.technologies I might have ,80% of the VHDL and an fpga by end of year [2026-06-08 8:23 p.m.] namibj How many PCBs with >=4 layers have you designed and gotten manufactured? [2026-06-08 8:24 p.m.] wayfarer.technologies I'm not a PCB designer [2026-06-08 8:24 p.m.] wayfarer.technologies I write VHDL [2026-06-08 8:24 p.m.] fossify_37988 How are you going to test your chips [2026-06-08 8:25 p.m.] namibj I don't think you're crowdfunding alone next year, but if you find someone to respect the "hardware hard" part of such a project, it could happen. [2026-06-08 8:26 p.m.] wayfarer.technologies Breadboard right now. I am planning to tinker with PCB, I prefer to stay focused on vlsi [2026-06-08 8:26 p.m.] wayfarer.technologies 6502 are pretty simple to work with [2026-06-08 8:26 p.m.] wayfarer.technologies Such is why it's chosen [2026-06-08 9:12 p.m.] namibj Yeah tho the market for play gadgets is not large especially such types. I'm looking forward to trying to use a tall half slot to drive a couple parallel EPC-co GaN "mosfets" (5V gate drive, very fast) in optically controlled floating nature (the mosfets are directly attached to the gf180mcuD die, that controller is optically communicating with a central brain) for stacking the mosfet modules in series for more voltage. That requires them to be carefully driven to switch all together or one module will see too much drain voltage and immediately blow a crater into the GaN die from the resulting avalanche discharge. But it also should be efficient and fast, hence the reach for an ASIC that can provide per-"mosfet"-die tuned gate drive waveforms to a DAC and then an integrated efficiency-optimized (very distorting) amplifier that drives the actual "mosfet" gate. It's just not really done otherwise, because who'd willingly burden themselves with such severe dV/dt (in other words, such high frequencies at those spicy voltages). The only thing I know that goes near that is the inbuilt rectifier/voltage multiplier of a CRT flyback transformer. And that's barely still audible to mildly ultrasonic, not several MHz. [2026-06-08 9:14 p.m.] namibj Shy of specialty things that need/want integration, few things actually want this type of process taped out. I good you can replace some smaller FPGA applications, at the cost of programmability. [2026-06-08 9:16 p.m.] tholin The CoB option gives you a breakout to a mezzanine connector. You will need *another* assembled PCB to adapt this to DIP. Then, you need to factor in costs for shipping and import duties (of the parts to you), VAT, probably other taxes and business upkeep costs, shipping (to the customers) and, for international customers (which you will have in this market) even more duties and tariffs! $20 is not realistic. [2026-06-08 9:17 p.m.] tholin I played with the idea of selling my chips extensively, but gave up on doing it alone (for now) [2026-06-08 9:18 p.m.] tholin US tariffs are particularly brutal right now, which is what ultimately made me go "Nah, screw this" [2026-06-08 9:25 p.m.] fossify_37988 I think there are some niches where it could make sense, especially because you have access to those LDMOS fets [2026-06-08 9:27 p.m.] namibj I got a batch of 50 boards with voltage regulator capacitors and one LGA package fabbed at JLC around last Christmas for 25€ each of which iirc like 16€ each was that LGA. At QTY 1k and unless I missed some new tariffs it'd be possibly to get DIP'd w.s. COBs into domestic bubble mailers and posted, unless that e-waste recycling law happens to get in the way there, not sure I'm not selling retail. But yeah it'd be _barely_ and no profit. [2026-06-08 9:28 p.m.] namibj Especially once we figure an economic flip chip "power stage contacts" packaging. [2026-06-08 9:29 p.m.] namibj (Inductance mainly.) [2026-06-08 9:30 p.m.] fossify_37988 I do wonder how companies like THAT can produce their chips relatively affordably on tiny (~100 mm) wafers [2026-06-08 9:30 p.m.] namibj What kinda chips? [2026-06-08 9:31 p.m.] fossify_37988 Audio [2026-06-08 9:31 p.m.] fossify_37988 Same with Sound Semiconductor, but I believe they're fabless [2026-06-08 9:31 p.m.] fossify_37988 https://cabintechglobal.com/ssi2130 for ex [2026-06-08 9:31 p.m.] namibj Ahhh hmmm [2026-06-08 9:32 p.m.] fossify_37988 https://thatcorp.com/that-6261-6263-6266-dual-low-noise-programmable-gain-preamplifier-adc-driver-ic/ {Embed} cksong https://thatcorp.com/that-6261-6263-6266-dual-low-noise-programmable-gain-preamplifier-adc-driver-ic/ THAT 6261/6263/6266 Dual Low Noise Programmable-Gain Preamplifier-A... 2026-06_media/626x-1-6C52A.png [2026-06-08 9:42 p.m.] polyfractal regarding pricing, I just ordered some PCB + assembly to test my chip a little easier than breadboard. Relatively simple 4 layer board (micro, headers, few level shifters, caps, resistors, only expensive part was a PSRAM module), moderate size. - $17.90 for 5pc - $159.75 for assembly - $46.47 for shipping - $78.84 for tariffs and taxes all up that's $60 per board, plus $8.5 for the chip and COB. At qty 1000 and a better PCB that price could be brought down. But to hit $20 price point for PCB + chip COB, you'd probably have to assemble your own and keep the board ultra simple [2026-06-08 9:46 p.m.] namibj Ehhhh, look at parallax propeller 2 for example, that's 130nm on semi "fabless" and fairly big (iirc the die could fit about 1.2~1.5 MiB SRAM from it's area; they only have 512 kiB shared plus 8 cores @4 kiB local each, but it's extremely powerful IO wise. E.g. each core could drive individual 180~250 MHz pixel clock VGA (256 pallet or fixed LUT optional, but it could sustain true color just no framebuffer to match). Each GPIO (64 of them) has 3 8-bit DACs, one 3ns VGA-class, ~123 Ohm, one ~600 Ohm, and one iirc ~15 kOhm (that one is used for the level comparator and some select related feedback modes of the pad "drivers"). It literally lets you set (sadly only 4 bit resolution) a "high" and a "low" code for the fast DAC to use for digital GPIO output state emission, so you can directly handle e.g. 1.2V CMOS levels, together with the input comparator. [2026-06-08 9:48 p.m.] namibj Where in that breakdown are the "misc" components? The *assembly cost"? [2026-06-08 9:48 p.m.] namibj Propeller 2 is 12$ in quantity [2026-06-08 9:49 p.m.] namibj (last I looked) [2026-06-08 9:50 p.m.] namibj It's by far the fanciest "GPIO pad" of any microcontroller. [2026-06-08 9:52 p.m.] polyfractal yeah lumped into assembly cost. Lemme find the BOM vs actual assembly breakdown [2026-06-08 9:53 p.m.] namibj Just checking otherwise I'd have called out your choice of expensive assembly. [2026-06-08 9:53 p.m.] namibj I should sleep now. [2026-06-08 9:55 p.m.] polyfractal some of this would fall under NRE that amortizes over a lot of parts for sure, just expensive at such low quantity. {Attachments} 2026-06_media/image-075A6.png [2026-06-08 9:56 p.m.] polyfractal but yeah, cost is mostly _not_ the physical PCB or components. all in assembly, fixturing, setup fees, non-standard parts being loaded etc [2026-06-08 10:02 p.m.] namibj Fancy board to need fixture [2026-06-08 10:03 p.m.] polyfractal 🤷‍♂️ I'm a PCB newbie and just yolo'd it, but it is double sided so that's probably why {Reactions} 💯 [2026-06-08 10:03 p.m.] namibj Ohh yeah [2026-06-09 3:24 a.m.] greg.hashtag.9468 My serv based chip from run 1 is toggling GPIOs. With the help of a sacrificial iCEBreaker board (FTDI + QSPI + 12MHz oscillator already populated and connected) 🎉 {Reactions} 🎉 (8) 🥳 (4) [2026-06-09 3:24 a.m.] greg.hashtag.9468 {Attachments} 2026-06_media/IMG_3684.CR2-019FF.jpg [2026-06-09 3:24 a.m.] greg.hashtag.9468 {Attachments} 2026-06_media/blinky_trace-C58A3.png [2026-06-09 10:28 a.m.] namibj what that chip (good) for? [2026-06-09 11:04 a.m.] greg.hashtag.9468 An experiment with the serv + spram wrapper. It's an array of 23 seperate cores, plus some basic peripherals. A SPI loader on boot pre-loads each cores memory. (the above trace) [2026-06-09 11:06 a.m.] namibj Sorry, "serv" is too generic a term to make me confident to Google it and get the right thing. Got a link perhaps or such? [2026-06-09 11:07 a.m.] 246tnt https://github.com/olofk/serv {Embed} https://github.com/olofk/serv GitHub - olofk/serv: SERV - The SErial RISC-V CPU SERV - The SErial RISC-V CPU. Contribute to olofk/serv development by creating an account on GitHub. 2026-06_media/9610be80-68d3-11eb-98c5-a009a9574b91-19A3F [2026-06-09 11:09 a.m.] greg.hashtag.9468 Ahh sorry. Yes, not very googlable. "SErial Risc V" CPU. [2026-06-09 3:41 p.m.] tholin Are the commands for manually running klayout DRC and antenna rule check on a GDSII file documented anywhere? [2026-06-09 4:31 p.m.] mole99 Started a thread. [2026-06-09 4:37 p.m.] namibj "pre-tested metal inductors"? Do we have any? SH.1 says circular inductors are theoretically supported? [2026-06-09 4:43 p.m.] mole99 As far as I know, no. However, we might see some inductors with 45-degree angles taped out on ws-run #2. [2026-06-09 5:04 p.m.] namibj If I can cook some suitable ones in the next few hours I expect to use some simple and some T-coil ones in the serializer. Would be nice to have those much sharper clock edges at the final MUX. [2026-06-10 10:50 a.m.] namibj [2026-06-10 11:06 a.m.] namibj This _seems_ like it might easily enough be adapted to our (gf18mcuD instead of that file's SG13G2) layer stack and would unlock generic "linear network" PEX one could hook up to SPICE (Xyce's easy way seems locked to harmonic balance aka large-signal (non-linear, with harmonics and intermodulation!) AC, but it shouldn't be too hard to make an analog behavioral model out of it (`README.md` "The resulting S-parameters can be used for simulation, but you can also extract a narrowband lumped element pi model using the pi-from-s2p tool.")) `workflow/run_generic_nport.py`: >>> ```python # Model comments # # This is a generic model running port excitation for all ports defined below, # to get full [S] matrix data. # Output is stored to Touchstone S-parameter file. # No data plots are created by this script. ``` {Attachments} 2026-06_media/SG13G2-68217.xml 2026-06_media/Screenshot_2026-06-10-12-59-58-96-E8EEB.jpg [2026-06-10 11:18 a.m.] mole99 @Ghaith Al Sabagh has already ported the XML to gf180mcuD for the IEEE Chipathon. He will tape out some inductors on ws-run #2. [2026-06-10 2:14 p.m.] ghaithalsabagh Hi @namibj You would find the needed xml files for openEMS and palace AWS here: https://github.com/EngGhaith/The-Silent-Owl-GF180MCU-WB-LNA/tree/main/EM-Flow {Embed} https://github.com/EngGhaith/The-Silent-Owl-GF180MCU-WB-LNA/tree/main/EM-Flow The-Silent-Owl-GF180MCU-WB-LNA/EM-Flow at main · EngGhaith/The-Sil... The Silent Owl is an open-source LNA designed in GF180MCU for Chipathon 2026 - EngGhaith/The-Silent-Owl-GF180MCU-WB-LNA 2026-06_media/The-Silent-Owl-GF180MCU-WB-LNA-E5725 [2026-06-10 4:29 p.m.] namibj Ohh great! Are there any inductors already designed for that 2.4 GHz target I could maybe use as stand-in reference for my 2.5 GHz (design target, looks possible ||with (either) minor peaking into the final 4:1 MUX or (alternatively) employing 3-tap FIR between the mux node and the limiting amplifier acting as pre-driver for a current-mode adjustable-current (FIR tap) output driver (the tap's "PA")||) clock tree buffers? Before specializing any further on serializer architecture and speed; I'd like to have physically feasible clock signal reference waveforms for designing (2:1 and the final 4:1) MUX cells, latch cells, and then doing a bit of floorplan "preliminary PnR" to know that overall design can fit into the ttgf0p3 tile I got. [2026-06-10 8:30 p.m.] namibj https://ieeexplore.ieee.org/document/11092168 ahh, yes, _paywalls_ but it does sound like it has already scripted the port interfacing stuffs between OpenEMS and Xyce there, and it kinda sounds like they're bypassing the native Xyce limitation of it's `YLIN` device. [2026-06-11 2:07 a.m.] .pogeg Hmm I synthesized our design with AS 3v3 SCL, and it synthesized a dfxtp_4 cell but it isn't in the Verilog models [2026-06-11 5:28 a.m.] namibj the _4 is just drive strength though? [2026-06-11 7:29 a.m.] mole99 You can open an issue or pull request in this repository: https://github.com/AvalonSemiconductors/gf180mcu_as_sc_mcu7t3v3 [2026-06-11 10:14 a.m.] .pogeg opened up an issue 👍 [2026-06-11 10:15 a.m.] .pogeg I believe you have to duplicate the Verilog cell model for each drive strength as well [2026-06-12 11:13 a.m.] tholin The new KLayout DRC setup is not messing around, I see {Attachments} 2026-06_media/image-C429D.png {Reactions} 🚀 [2026-06-12 7:36 p.m.] .pogeg Needs more ram consumption [2026-06-13 1:03 a.m.] .dmv I found it worthwhile to run proper DRC jobs by spinning up an AWS r6i.2xlarge instance (8 vCPU, 64 GiB memory) -- it's $0.5 / hr in us-east-1 on demand, and my (fairly complex, analog) design generally takes <30 minutes. It's all scripted to spin up, copy over the changes to test, execute, wait to retrieve logs, and turn off. I kept hitting OOM issues on my (18GiB) laptop, 40 minutes in, so these sanity checks are worth the quarter per validation for me. {Reactions} 👍 (3) [2026-06-15 12:56 p.m.] namibj yeah I'm so lucky I got plenty spare ram in my workstation {Reactions} 👍 [2026-06-15 7:42 p.m.] .pogeg Kind of unrelated to wafer.space, but I can't seem to open Magic with OpenGL as the display driver. [2026-06-15 7:42 p.m.] .pogeg I'm using Magic bundled with the current flake in the project template [2026-06-15 7:43 p.m.] .pogeg Cairo and X11 works fine [2026-06-16 3:59 p.m.] georgehoffmann428 {Attachments} 2026-06_media/image-B39C1.jpg 2026-06_media/image-38933.jpg ============================================================== Exported 152 message(s) ==============================================================