wafer.space Community

1:26 p.m.

There's just something so funny about this

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Such a cute little core!

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Do you really need 4 ground pins ?

That's ~1mm^2? Makes it obvious why I was wondering about just having pins on a single side, you could probably fit 11 of the 12 pins while massively increasing the core area

tnt

Do you really need 4 ground pins ?

Who doesn't?

No, that was just a quick chip for creating a reproducible for Tim E.

RebelMike

That's ~1mm^2? Makes it obvious why I was wondering about just having pins on a single side, you could probably fit 11 of the 12 pins while massively increasing the core area

Yes, the ratio between padring and core is massive in this case. You might be able to use the LibreLane padring script as a starting point to adjust the padring to only a single side. If this is already possible in OpenROAD today, I can then adjust the default script to allow this directly.

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Needing this is a little way off as we'd need to have options to subdivide the dies first, but it's on my list of things to play with at some point

Well, you can already subdivide a die yourself and submit several of your sub-dies at once. The individual dies won't be separated, of course, but we should still be able to bond the ones around the edges

Leo Moser (mole99)

Click to see attachment 🖼️

Even though it is super funny, it is also super cool!

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Chip with just 4 pads. Power, ground, two bidir (clock provided by ring oscillator).

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Tholin

Chip with just 4 pads. Power, ground, two bidir (clock provided by ring oscillator).

I think you can team up with @RebelMike and share a subdivided die

I don't know what I would even put on there

7:37 p.m.

Something I²C, I guess?

USB

That sounds like a challenge. Doesn't that require precise timing? Out of a ring oscillator?

(Precisely Clocking 12 MHz internally is a challenge left to the reader)

I mean, how does the USB protocol work? Surely, there is some pre-defined discovery packet that is sent by the host? That could be used to tune the ring oscillator.

ATtiny85's internal RC osc can somehow manage USB

Oh, yeah, USB packets literally start with a bunch of even pulses as a clock sync.

7:42 p.m.

But not sure how you'd tune a ring oscilator off of that

7:42 p.m.

THAT I will leave as a challenge to the reader

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I guess you could also try to get a clock through VDD somehow

7:44 p.m.

like swing it between 3V and 3V3 at 12MHz (or whatever you need), and then use that internally to generate the clock

7:45 p.m.

an easy-ish way to create it would be to connect the VDD pin to the power supply through a FET in parallel with a diode

7:45 p.m.

then you feed the clock to the FET, and whenever the FET is off, the voltage will drop by the diode forward voltage drop

We have OTP, right? So, you first start in a mode where you can blow OTP bits somehow to tune the ring oscillator. Then once that's within tolerances you blow a bit that permanently turns the device into a USB

One way a ring oscillator could be made tuneable is by using transmission gates to bypass some of the inverters. Have one path that goes through the inverters and one path that goes around them. I'm not sure if that'll provide ultra fine control, but it doesn't need to be perfect. The clock only needs to line up with the USB data bits for one packet before the next one re-tunes the oscillator.

7:48 p.m.

Okay, now I'll stop!

7:49 p.m.

(The idea of using a NFET and DAC as a digitally controllable impedance to speed down the oscillator also occured to me, but I'm not sure how well that'd work, actually) (edited)

RebelMike

We have OTP, right? So, you first start in a mode where you can blow OTP bits somehow to tune the ring oscillator. Then once that's within tolerances you blow a bit that permanently turns the device into a USB

Not really feasible, since you need to dynamically account for drift of the oscillator by supply voltage and temperature.

urish

I guess you could also try to get a clock through VDD somehow

Reminds me of some very old 4 pin PIC10F devices which had a shared GPIO/VDD pin and a large internal capacitor with specs of how long you could pull the GPIO line low.....

Tholin

Not really feasible, since you need to dynamically account for drift of the oscillator by supply voltage and temperature.

PLL on the USB packet with oscillator as initial frequency input is how the SiLab HappyGecko parts are able to meet spec without an external crystal

Tim 'mithro' Ansell

Reminds me of some very old 4 pin PIC10F devices which had a shared GPIO/VDD pin and a large internal capacitor with specs of how long you could pull the GPIO line low.....

I finished developing a software network stack to run on my RISC-V core on my GFMPW-1 chips.

7:22 p.m.

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7:25 p.m.

Powering on the board does this

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7:26 p.m.

I need to turn this around and make it capable of accepting incoming TCP connections.

7:26 p.m.

Will I be the first person to get open-source custom silicon connected to the internet? Or host a website with it? (edited)

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7:30 p.m.

I went the extra mile to support both IPv4 and IPv6 and auto-configuration for both.

Tholin

I need to turn this around and make it capable of accepting incoming TCP connections.

This is impressive.

https://github.com/AvalonSemiconductors/gfmpw1-multi-bringup/tree/main/TholinRISCV/Software/Ethernet

gfmpw1-multi-bringup/TholinRISCV/Software/Ethernet at main · Avalo...

Bring-up of GFMPW-1 multi-project submission. Contribute to AvalonSemiconductors/gfmpw1-multi-bringup development by creating an account on GitHub.

10:07 p.m.

The source code is here, btw

@Tholin - That is super cool!

Tholin

Will I be the first person to get open-source custom silicon connected to the internet? Or host a website with it? (edited)

I guess depends on how you define that -- @carlfk put the Tiny Tapeout board on the internet but I think that is cheating. I wonder if you could run ppp over the uart to the Linux core.....

Due to the fact that dial-up modems once existed, you can actually pipe a network connection over UART to this day with some basic Linux utilities.

@Tholin - I think the Tiny Tapeout Linux core might be too slow? I think there are some real time requirements for PPP? I've forgotten what was the thing that we used before PPP.

10:19 p.m.

Also, I wouldn't say your work above is particularly off-topic, seems very much on topic to me.

Well, its more software dev on a RISC-V core

10:27 p.m.

Its just that the core happens to be custom silicon

Tim 'mithro' Ansell

I guess depends on how you define that -- @carlfk put the Tiny Tapeout board on the internet but I think that is cheating. I wonder if you could run ppp over the uart to the Linux core.....

The original one only supports 8mb PSRAM, so it's not sufficient to run the TCP/IP stack

3:52 a.m.

I recently patched it to support 16mb so the future version (on ttsky25a/ttihp25b) might be able to

@urish - Cool!

Hirosh is also currently working on adding FIFO to the UART to make it more reliable

Tim 'mithro' Ansell

@Tholin - I think the Tiny Tapeout Linux core might be too slow? I think there are some real time requirements for PPP? I've forgotten what was the thing that we used before PPP.

Are you thinking of SLIP? I remember THOSE good ol’ days

8:38 a.m.

Btw @Tholin , awesome and exciting work as usual

What I really want to know is how you managed to crack the usual limit of 24 hours per day in order to get all of this done

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algofoogle (Anton Maurovic)

Are you thinking of SLIP? I remember THOSE good ol’ days

SLIP is still very much alive. The ESP32 uses it to communicate with its bootloader, for example.

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Oh cool, and unexpected

Probably!

40000 / 3600 11.11111111111111

2:09 a.m.

11 hours for 40,000 seconds? I thought it was nore like 20 hours?

2:10 a.m.

or mayb eit was 3 sec per die = 33 hours

carlfk

40000 / 3600 11.11111111111111

You may have had part of my calculation in your head when it was 28 reticles * 40 projects * 50 wafers = 56000 dies 56000/3600 = 15.55

that sounds about right

Tholin

Click to see attachment 🖼️

https://testing.tholin.dev/

8:00 p.m.

Now hosting a website on my custom silicon

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8:00 p.m.

It'll remain online for as long as the 18650 powering it lasts.

it's kinda meta

I'm curious what people here make of this: https://tenstorrent.com/vision/tenstorrent-announces-open-chiplet-atlas-ecosystem

Tenstorrent Announces Open Chiplet Atlas™ Ecosystem | Tenstorrent

Tenstorrent is launching the Open Chiplet Atlas™ (OCA™) Ecosystem — including the open standard OCA Architecture — aimed at creating a truly open chiplet market.

@HardWall - Multiple people have attempted this - none have succeeded. https://antmicro.com/blog/2020/10/open-chiplet-initiative/

zGlue teams up with Antmicro and Google in Open Chiplet Initiative

It's true until it's not. I have a bit of a bias since I'm kind of a keller fanboy, but I really don't understand the industry enough to make an educated guess.

8:24 p.m.

My understanding though is that chiplet designs will be by their nature inferior to the same design but integrated on the same die. But more composable and faster turnaround. ( again, i'm not sure I even understand properly what I'm talking about)

Wow, threw Claude a request to do some research, You weren't kidding, the world is littered with the bodies of chiplet interconnect initiatives.

HardWall

I'm curious what people here make of this: https://tenstorrent.com/vision/tenstorrent-announces-open-chiplet-atlas-ecosystem

If this were ever to be a thing, I think the first step would be an open source SerDes for ASIC design. I was speaking with @carlfk the other day about putting HDMI on an ASIC design and he said this part was still a current hurdle. Chiplets--at least the current versions from AMD--all communicate over SerDes.

SerDes

A Serializer/Deserializer (SerDes) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction. The term "SerDes" generically refers to interfaces used in various technologies and applications. The primary...

HardWall

My understanding though is that chiplet designs will be by their nature inferior to the same design but integrated on the same die. But more composable and faster turnaround. ( again, i'm not sure I even understand properly what I'm talking about)

The problem turns out to be economics -- at the moment chiplets makes sense when things are very expensive -- but to get an ROI you need to sell a lot of units, thus if you are selling lots of units you want the chiplets to be customized for your use case.....

Tim 'mithro' Ansell

The problem turns out to be economics -- at the moment chiplets makes sense when things are very expensive -- but to get an ROI you need to sell a lot of units, thus if you are selling lots of units you want the chiplets to be customized for your use case.....

I was under the impression that some of the economics came from just yield gains? I also personally think some of the coolest stuff (other than wafer.space) happening right now is in the packaging space. @HardWall I do see a potential case maybe where the design for the opposing interconnect would be designed by the one party. And the second party can put that into their design. Also something else, is if you start to think of things like PCBs where you have a series of components on a PCB, a similar concept would be a series of dies on a silicon interposer.

Andrew Wingate

I was under the impression that some of the economics came from just yield gains? I also personally think some of the coolest stuff (other than wafer.space) happening right now is in the packaging space. @HardWall I do see a potential case maybe where the design for the opposing interconnect would be designed by the one party. And the second party can put that into their design. Also something else, is if you start to think of things like PCBs where you have a series of components on a PCB, a similar concept would be a series of dies on a silicon interposer.

@Andrew Wingate - Below 5nm, chiplets do make sense for making these high end chips (for yield and other cost reasons). The problem is the chiplet marketplace / reuse idea. Basically, the people working on these high end nodes need to make a large number of parts to recoup the cost of the design. When you go, "I'm going to need to make 1 million of these parts" then it pretty much always makes sense to customize the chiplet for that part.

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