wafer.space Community

https://antmicro.com/blog/2026/04/simulating-active-cooling-using-a-cfd-based-flow is pretty cool

Simulating active cooling using a Computational Fluid Dynamics-base...

I love it when system just breaks and you have to try and fix things when just wanting to take a lunch break...

running again, at least

Leon

Do people here have opinions on the best way to get started with FPGA/ASIC design? My background is that I have a Master's degree in computer science, but it contained almost no courses in this direction (only one course where we created a simple RISC-V core in VHDL that ran on an FPGA, which was a lot of fun, but I still feel like I know nothing and should start learning from scratch). I love reading about TinyTapeout and wafer.space and what people do there, and would love to learn about this, but every time I try to get started I get lost trying to figure out the best way to start, and lose motivation. I would like to create some designs that I can send to TinyTapeout (and maybe even wafer.space, but that's probably a too large investment for a hobby for me), and they don't need to have a practical purpose. I know the Zero to ASIC course exists, but it's fairly expensive at $700, and I think I'd rather learn from a book/text than videos. But I could afford it and it seems to be the most popular resource aimed at beginners that don't want to study for years before getting something done, does anyone have any opinions if it's worth the price? And are there any other recommended resources? Should I simply find a book about Verilog and read that, and if so, which? (edited)

I'd recommend https://www.crowdsupply.com/1bitsquared/icebreaker-fpga since they have great tutorials https://docs.icebreaker-fpga.org/getting-started/, also lots of resources https://www.fpga4fun.com/

iCEBreaker FPGA

An open source iCE40 FPGA development board designed for teachers and students

21:44

apparently this "tang" fpga also is supported with open tools, and looks pretty cheap https://github.com/twied/TangPrimer-20K-example

GitHub - twied/TangPrimer-20K-example: Examples for the Sipeed Tang...

Examples for the Sipeed Tang Primer 20K FPGA using Open Source tools under Linux - twied/TangPrimer-20K-example

strictly speaking, «tang» is not the name of a fpga, it's the name of sipeed's family of fpga devboards, they're based on gowin fpgas

Leon

Do people here have opinions on the best way to get started with FPGA/ASIC design? My background is that I have a Master's degree in computer science, but it contained almost no courses in this direction (only one course where we created a simple RISC-V core in VHDL that ran on an FPGA, which was a lot of fun, but I still feel like I know nothing and should start learning from scratch). I love reading about TinyTapeout and wafer.space and what people do there, and would love to learn about this, but every time I try to get started I get lost trying to figure out the best way to start, and lose motivation. I would like to create some designs that I can send to TinyTapeout (and maybe even wafer.space, but that's probably a too large investment for a hobby for me), and they don't need to have a practical purpose. I know the Zero to ASIC course exists, but it's fairly expensive at $700, and I think I'd rather learn from a book/text than videos. But I could afford it and it seems to be the most popular resource aimed at beginners that don't want to study for years before getting something done, does anyone have any opinions if it's worth the price? And are there any other recommended resources? Should I simply find a book about Verilog and read that, and if so, which? (edited)

any specialties from your compsci degree you may consider relevant to being able to do something more interesting than the average FPGA/ASIC "beginner after having finished a master's in compsci" perhaps? There is of course the potential to work towards a demoscene entry for the spring 2027 competition I'd predict there to be on/with TT? Unfortunately copyright of early video games (of the arcade era) might be in the way of doing a "remake" of such a game, perhaps using modern extensions/gamemodes to go along with the old.

zyp

strictly speaking, «tang» is not the name of a fpga, it's the name of sipeed's family of fpga devboards, they're based on gowin fpgas

was wondering why it didn't sound like any familiar fpga family; but gowin explains that well. Yeah, they do have quite good price/performance and I've heard them to not demand $$$$ vendor tooling to utilize.

I would also say that teaching software engineers hardware design has been significantly easier than teaching hardware engineers software design.

02:58

There is also the Fomu workshop -> https://workshop.fomu.im -- And if you are at an event I'm also at, then I'll happily give you one of the Fomu boards for free if you show me that you have installed the toolchain.

namibj

any specialties from your compsci degree you may consider relevant to being able to do something more interesting than the average FPGA/ASIC "beginner after having finished a master's in compsci" perhaps? There is of course the potential to work towards a demoscene entry for the spring 2027 competition I'd predict there to be on/with TT? Unfortunately copyright of early video games (of the arcade era) might be in the way of doing a "remake" of such a game, perhaps using modern extensions/gamemodes to go along with the old.

Not sure, I haven't been able to come up with something, but currently I'm more worried about learning the basics than figuring out to do once I have. Demoscene sounds cool, though spring 2027 is quite some time away (and speculative, if I understand your message correctly?).

@Leon - I think there is currently a demoscene competition open right now? https://tinytapeout.com/competitions/demoscene-ttsky26a-announce/

TTSKY26a Demoscene Competition - Tiny Tapeout

Build a sound and graphics demo on 130nm ASIC

06:32

The infrastructure that Tiny Tapeout has which lets you see the simulated VGA output in the browser is super cool.

Tim 'mithro' Ansell

@Leon - I think there is currently a demoscene competition open right now? https://tinytapeout.com/competitions/demoscene-ttsky26a-announce/

As far as I understand, the deadline for submissions is about a week from now, this is too soon for me

(edited)

Leon

As far as I understand, the deadline for submissions is about a week from now, this is too soon for me

(edited)

hence me suggesting to aim calmly for the one we'd expect a year after.

The best time to plant a tree was 30 years ago, the next best time is today

2

https://discord.com/channels/1361349522684510449/1361349523724570941/1500181556608635151 Honestly doesn't even need to be that huge, but I don't think the thin 0.8 mil wire is appropriate for a 5V output gate consuming on the order of 2~5 W (in what I assume to be mostly the gate "poly" of the GaN die). Yes that's supposed to be a class-B power amplifier output stage on the wafer.space die into an impedance matching network (on consideration of the capacitive load and trying to be less wasteful, and not melting the wafer.space die). It'd serve as PoC of the drive so that together with extensive simulation of the larger topology it should be far less risky to get someone to pay for the approximately 4-ish MW of fixed 1:2 ratio (but bidirectional current support) DC/DC converter that one would get out of a single tall-type wafer.space slice. (The assumed 5x parallel EPC2019 per die amount to just over 9$ per such 5 in quantity. And that's just the semiconductors for the converter; it also needs a bunch of capacitors subjected to about 1% voltage ripple at a (possibly few) dozen MHz. Sadly not really "cheap" but for reference, substation transformers in that power range had 2019 pricing around 100~150 kUSD. But those are able to do higher ratios so feel free to adjust that by 4x for more comparable scale (assuming the DC/DC unit is segmented into 4 equal-power chunks with one set up for one W.S die in parallel in the stacks, and the others with 2/4/8 in parallel, to create an overall 1:16 voltage ratio). There's a different topology for higher voltage ratios I have to look at again with the W.S driven EPC-co 200V GaN dies as assumption. That's technically capable of buck-like down-regulation of operating voltage and the more complex phase-shift control would nominally give full suft-switching at least under compatible load. I had meant to try a prototype of the topology for a microwave oven to do a monolithic boost-APFC & HVDC regulator (take in grid frequency or "alirack DC" at European voltages, emulate an ohmic resistor to the grid, turn the power into something the magnetron likes, provide good control over magnetron output power over at least a 100:1 range with over 10 dB of PSRR at DC w.r.t. targeted output power, to have an ability for accurate radiation dose control), ...but then I had to move and am now back on TinyTapeout MCML after I found out the project survived the efabless.

@peterkinget @xianglin_pu Nice logo!

1

07:10

Beautiful @Tholin!! -# @kris

1

Do you see this fill pattern in the background of my art? That’s not metal. I turned off all metal fills around my art. That is the COMP layer. Its diffusion. Somehow, you can see all the way down to the silicon behind the art. (edited)

Tholin

Do you see this fill pattern in the background of my art? That’s not metal. I turned off all metal fills around my art. That is the COMP layer. Its diffusion. Somehow, you can see all the way down to the silicon behind the art. (edited)

Yes, you can see that also around the wafer.space logo. Good to know for the next run :)

Indeed. I wonder if P and N type look different.

Andrew Wingate

@peterkinget @xianglin_pu Nice logo!

Credit goes to Cade Gleekel (see https://mosbius.org) who developed the logo.

Tholin

Do you see this fill pattern in the background of my art? That’s not metal. I turned off all metal fills around my art. That is the COMP layer. Its diffusion. Somehow, you can see all the way down to the silicon behind the art. (edited)

SiO2 is glass so transparent

I’m trying to get the SCL characterization scripts to work in a nix shell instead of the iic-osic-tools container and its failing because numpy won’t load

17:10

But

Its because I need to install lctime from my fork on git

18:01

And I don’t know how to properly do that in this context

18:04

Adding git+https://codeberg.org/TholinVali/lctime.git to extra-python-packages had no effect

Tholin

Adding git+https://codeberg.org/TholinVali/lctime.git to extra-python-packages had no effect

extra-python-packages expects a Nix derivation, not a git URL. So you first need to create lctime.nix that uses your fork, and then you can use it in the Nix flake, afaik. You can find some examples at nix-eda: https://github.com/fossi-foundation/nix-eda/tree/main/nix Best to ask that question on FOSSi Chat, by the way. Donn, our Nix expert, might be able to help you :)

nix-eda/nix at main · fossi-foundation/nix-eda

Nix flake for more up-to-date versions of EDA tools - fossi-foundation/nix-eda

Tholin

Adding git+https://codeberg.org/TholinVali/lctime.git to extra-python-packages had no effect

(I have come to have feelings about lctime...)

I tried not using nix and just installing the required packages directly into the ubuntu container

21:53

Since very few are required for this

21:54

But the version of magic that installs through apt is too old

21:54

And if I build magic from source, it somehow behaves differently than the version from the package manager?

21:56

I don’t think its parsing the environment variables in this

Tholin

And if I build magic from source, it somehow behaves differently than the version from the package manager?

This actually happened to me on Fedora too. Turns out the magic repo for the package managers is a different repo than the "normal" one

21:56

God knows why but the artifacts are built from what's effectively a different branch

21:57

For Ubuntu just follow the instructions on Magic's website, it's your safest bet. I ended up doing an Ubuntu distrobox and that worked

I was missing the tcl and tk dev packages, I think

Look! No nix!

22:09

Characterization is next, I already did all the prerequisite work

1

23:49

Its taking a bit

I almost accidentally made a broken DAC ferrisBallSweatSpin

01:20

deviated from binary radix in the wrong direction.... good thing alarm bells rung while trying to validate drive strength of SCL latches for use as bit feeds