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      "content": "Last night, I thought I'd try taking @Matt Venn's R2R DAC he just submitted on TT 0p3 and add it to TinyQV.  I've got the macro in and the digital inputs + ground are connected OK (could probably do with buffers on the input, but one thing at a time).\nHowever, librelane won't route the output from the DAC to the analog pin - possibly quite sensibly as in general it probably shouldn't touch analog things.  How should I deal with making that connection?  I guess I could add it manually to the gds after the librelane flow has finished, but that seems not ideal.  Can I add a step to the flow to describe the connection?  Or can I just tell the router to connect it somehow?\nMy repo is here, see the `dac` branch: https://github.com/MichaelBell/ws02-tinyQV/tree/dac",
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      "content": "Interested to see how you solve it!",
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      "content": "This is an issue I encountered last run as well, give me a minute to remember the fix",
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      "content": "Librelane does not like that the pad’s layout does not have a port named \"PAD\". That’s it.",
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      "content": "That’s all I did. Copy the files for the analog pad and define a port named \"PAD\" in magic",
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      "content": "https://github.com/AvalonSemiconductors/ws-submission-2025/tree/main/macros/Analog/AnalogPad",
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      "content": "Its not even different electrically. The analog pad just provides a straight connection to the outside, the ports \"ASIG5V\" and \"PAD\" are electrically shorted, but LibreLane needs \"PAD\" to exist.",
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      "content": "Otherwise it goes \"whoa, this is useless!\" and optimizes it out, since all it sees is a cell with only an input and no output (I *believe*)",
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      "content": "The issue is that OpenROAD's detailed router does not route any pins with the `SPECIAL` attribute. This makes sense for power supplies, as they are handled by a dedicated pdngen call.",
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      "content": "Here you can see that ASIG5V has SPECIAL set to True.",
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      "content": "Looking at the LEF for `gf180mcu_fd_io__asig_5p0.lef`, I don't see the `SPECIAL` attribute set for ASIG5V. However, OpenROAD probably sets it when making the bondpad a BTerm (top-level pin) with [`place_io_terminals`](https://openroad.readthedocs.io/en/latest/main/src/pad/README.html#place-io-terminals).",
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      "content": "I had a similar issue with [HeiChips](https://github.com/FPGA-Research/heichips25-tapeout): in IHP, the bondpads are separate from the I/O cells and [place_bondpad](https://openroad.readthedocs.io/en/latest/main/src/pad/README.html#place-wirebond-pads) also makes the pin SPECIAL. My solution (workaround) was to edit the LEF to add a second port for the core-facing pin of the I/O cell.",
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      "content": "afaik sky130 doesn't have this issue since the I/O cells have separate ports for bondpad and core side.",
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      "content": "I noticed that SPECIAL appeared in the def on the OpenROAD.PadRing step, and suspected that might be the reason the router ignored it",
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      "content": "But couldn't work out where that was coming from (or even if it was sensible to try and avoid it!)",
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      "content": "iirc @tnt recently found a workaround that doesn't require to edit the LEF file? It involves placing a macro with two ports, which is essentially just a short, next to the core-facing pin of the I/O cell.",
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      "content": "However, Tholin's solution is also fine.",
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      "content": "Yesh, I putting a small macro doing the split connection which works better for me than editing the pads in the PDK :\n* No need for modifying PDK\n* Because the short is in a separate block with just that in it, it actually doesn't mess with full LVS/GDS check, both the \"schematic\" and \"layout\" side of that block will have a single 0R resistor in them, no ambiguity.\n* That also allowed me to connect all the split `Metal2` traces on the core side, join them together for better connection and bring them to `Metal3` where I needed them, avoiding me to have to deal with via at all when routing them \uD83D\uDE05",
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      "content": "Ends up looking like this :",
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      "content": "Cool, that sounds like a good solution.  I assume I can find that in the TT gf0p3 project?",
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      "content": "But the routing is still done manually though ODB scripts, I don't leave it up to the auto-router.",
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      "content": "You can't find it anywhere, that's WIP which is not pushed publically anywhere yet.",
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      "content": "But the macro is 2 squares of metal with via between them \uD83D\uDE05  just positioned right where it needs to be.",
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      "content": "And *if* you want to leave it up to the auto-router, you can now add NDRs directly via the LibreLane config \uD83D\uDE09 \n\nhttps://github.com/FPGA-Research/heichips25-tapeout/blob/d555bbc58aad6cc54e0bc9ce81b75936db2df0d8/librelane/config.yaml#L253",
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      "content": "Thanks all, I’ve got tnt’s solution working and it’s building with no errors \uD83D\uDE42",
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