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Guild: wafer.space Community
Channel: Information / questions / Generate clean padring
After: 11/30/2025 23:59
Before: 01/01/2026 00:00
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[12/02/2025 01:05] xintingjiang_36756
Hi all,
I am trying to generate a clean pad frame for manual top level connections following the script here: https://github.com/wafer-space/gf180mcu-project-template/pull/29/commits/34fc81fc1c3d354f5d73af2510585641c9bfa93c

Since for a clean pad frame, we don't have the chip_core, just chip_top, what is the proper way of providing the config pins of these instantiated pads? I've tried
 1) '0/'1: leads to magic-klayout XOR errors and some lvs errors of the pad frame
2) VSS/VDD: leads to lvs errors for short-connect the power grids.

Thanks for your help!

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2025-12_media/image-91E0C.png


[12/02/2025 07:31] mole99
Since you do manual top-level connections the padring is streamed out before any of the stdcells are placed and routed. Therefore you cannot connect any constants to the pins (you can, but there will be no connections).
You need to manually tie these pins after the GDS for the padring has been generated.


[12/02/2025 16:44] xintingjiang_36756
Got it, thanks!


[12/06/2025 19:54] xintingjiang_36756
Just to double check, this clean pad ring generator script is still valid after the project template update right?


[12/06/2025 20:03] mole99
Yes, I merged the PR into main. You can create a standalone padring via `make librelane-padring`.

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