Hi all,
I running the lvs check using klayout 0.30.2 and use the latest gf180mcuD version. What is weird is that I can pass lvs check for the same design using an earlier version of the gf180mcu pdk and failed when I use the updated one. The lvs report is attached.
My question is it seems that the root of the problem is the pin order and number of pins do not match for std cell in .cdl file(schematic) and in .cir file(layout extracted).
I attached the screen shot for the nor gate for instance. The subckt in cdl has 7 pins defined and in layout there are 9 pins. The extra two pins are VPW and VNW which were not there in earlier version. I've tried tight VPW to VSS and VNW to VDD and define gf180mcu_gnd and the VSS as the same net. These errors were still not resolved.
I was wondering has anyone met similar problem before or is there any workaround about this?
Many thanks in advance!