wafer.space Community - Is there a DRC violation waiver system?

Is passing DRC strictly required to tapeout? Is there any waiver system? For example I want to make topmetal "pads" smaller than design rule pad sizes, as I want to post-process dies/wafers to add additional layers to the design.

@Matt Venn your comments were helpful

18:25

Though I assume your "yes" was in regards to "strictly must pass DRC"

I thought I was in the tt discord

18:33

Where the answer is no, but I don't know for wafer.space

For last run, they wouldn't even waive the antenna rule

that makes sense though, because of charging during plasma steps

20:59

a discharge event will cause spallation and can cover not only your wafer with particles, but the entire chamber... leading to later batches to get particle contam

1

Tim wants wsrun-2 to follow the DRC rules much more strictly, as per the PDK docs. The only rule I can find for the pad layer is for the top metal overlap: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_1.html All the other rules are guidelines: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_2.html However, as there is no mention of a minimum pad width anywhere, wafer.space has to assume a minimum width of 40x40 according to PAD.1.

Passing DRC is strictly required for tapeout, there is no waiver system and there won't be any support for waivers. (edited)

06:48

@Leo Moser (mole99) - What about the rules @ https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_4_3.html and https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_4_5.html ?

Leo Moser (mole99)

Tim wants wsrun-2 to follow the DRC rules much more strictly, as per the PDK docs. The only rule I can find for the pad layer is for the top metal overlap: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_1.html All the other rules are guidelines: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_2.html However, as there is no mention of a minimum pad width anywhere, wafer.space has to assume a minimum width of 40x40 according to PAD.1.

Oh i thought 4 microns was allowed (some rule or guideline about "gold") (edited)

06:48

But that still is larger than ideal for "a via" to an additional layer

06:49

Ideally we'd know exactly the fab minimum CD limit

Tim 'mithro' Ansell

@Leo Moser (mole99) - What about the rules @ https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_4_3.html and https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_4_5.html ?

It looks like there's 4 different bonding processes...

06:56

Which one is offered for "bare wafer" purchase option needs clarification though (edited)

nmz787

Which one is offered for "bare wafer" purchase option needs clarification though (edited)

None of these bonding processes are really on offer, we are using an external wire bonding house.

Tim 'mithro' Ansell

@Leo Moser (mole99) - What about the rules @ https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_4_3.html and https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_4_5.html ?

Unfortunately, they don't apply to our use case and specify different numbers. While the solder bump (solder ball) rules specify a min. passivation opening of 40um, the probe guidelines specify min. probe passivation opening of 50um. There's an interesting note in the bond pad guidelines:

These are just default numbers for DRC purpose only, however, these are VARIABLE and the customer is advised to use the appropriate value acceptable to their assembly house.

So I suppose there's no min. limit for the passivation opening specified, because they assume that you are going to use sane numbers anyway, in order to do the bonding process.

Do you see a maximum size for the passivation opening?

No, I haven't seen one.

Tim 'mithro' Ansell

Do you see a maximum size for the passivation opening?

Minimum is likely more important for the litho operating point for that layer

nmz787

Minimum is likely more important for the litho operating point for that layer

Well, if there is no maximum, then you could just have a completely open top of the chip with no passivation.

Tim 'mithro' Ansell

Well, if there is no maximum, then you could just have a completely open top of the chip with no passivation.

Wouldn't "Min Probe pad top layer metal overlap of pad opening" flag?

nmz787

Wouldn't "Min Probe pad top layer metal overlap of pad opening" flag?

Dunno, that is why I was asking.

Even if there's no rule against it, I'm not sure if that doesn't lead to planarity issues at any of the processing steps.