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      "content": "Is passing DRC strictly required to tapeout? Is there any waiver system? For example I want to make topmetal \"pads\" smaller than design rule pad sizes, as I want to post-process dies/wafers to add additional layers to the design.",
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      "content": "@Matt Venn  your comments were helpful \ud83d\ude42",
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      "content": "Though I assume your \"yes\" was in regards to \"strictly must pass DRC\"",
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      "content": "I thought I was in the tt discord",
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      "content": "Where the answer is no, but I don't know for wafer.space",
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      "content": "For last run, they wouldn't even waive the antenna rule \ud83d\ude05",
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      "content": "that makes sense though, because of charging during plasma steps",
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      "content": "a discharge event will cause spallation and can cover not only your wafer with particles, but the entire chamber... leading to later batches to get particle contam",
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      "content": "Tim wants wsrun-2 to follow the DRC rules much more strictly, as per the PDK docs.\n\nThe only rule I can find for the pad layer is for the top metal overlap: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_1.html\nAll the other rules are guidelines: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_2.html\nHowever, as there is no mention of a minimum pad width anywhere, wafer.space has to assume a minimum width of 40x40 according to PAD.1.",
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      "content": "Passing DRC is strictly required for tapeout, there is no waiver system and there won't be any support for waivers.",
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      "content": "@Leo Moser (mole99) - What about the rules @ https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_4_3.html and https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_4_5.html ?",
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      "content": "Oh  i thought 4 microns was allowed (some rule or guideline about \"gold\")",
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      "content": "But that still is larger than ideal for \"a via\" to an additional layer",
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      "content": "Ideally we'd know exactly the fab minimum CD limit",
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      "content": "It looks like there's 4 different bonding processes...",
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      "content": "Which one is offered for \"bare wafer\" purchase option  needs clarification though",
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      "content": "None of these bonding processes are really on offer, we are using an external wire bonding house.",
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      "content": "Unfortunately, they don't apply to our use case and specify different numbers. While the solder bump (solder ball) rules specify a min. passivation opening of 40um, the probe guidelines specify min. probe passivation opening of 50um.\n\nThere's an interesting note in the bond pad guidelines:\n\n> These are just default numbers for DRC purpose only, however, these are VARIABLE and the customer is advised to use the appropriate value acceptable to their assembly house.\n\nSo I suppose there's no min. limit for the passivation opening specified, because they assume that you are going to use sane numbers anyway, in order to do the bonding process.",
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      "content": "Do you see a maximum size for the passivation opening?",
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      "content": "No, I haven't seen one.",
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      "content": "Minimum is likely more important for the litho operating point for that layer",
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      "content": "Well, if there is no maximum, then you could just have a completely open top of the chip with no passivation.",
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      "content": "Wouldn't \"Min Probe pad top layer metal overlap of pad opening\" flag?",
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      "content": "Dunno, that is why I was asking.",
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      "content": "Even if there's no rule against it, I'm not sure if that doesn't lead to planarity issues at any of the processing steps.",
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