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Between 10/31/2025 23:59 and 12/01/2025 00:00
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Is there some special trick define to use the verilog models ? sim/gf180mcuD/gf180mcu_fd_sc_mcu7t5v0.v:9975: error: Net MGM_P0 is not defined in this context. sim/gf180mcuD/gf180mcu_fd_sc_mcu7t5v0.v:9977: error: Net MGM_D0 is not defined in this context. sim/gf180mcuD/gf180mcu_fd_sc_mcu7t5v0.v:9979: error: Net IQ1 is not defined in this context. sim/gf180mcuD/gf180mcu_fd_sc_mcu7t5v0.v:9979: error: Output port expression is not valid. sim/gf180mcuD/gf180mcu_fd_sc_mcu7t5v0.v:9979: : Output port of gf180mcu_fd_sc_mcu7t5v0__udp_n_iq_ff is Q. This is what I'm getting when just including gf180mcu_fd_sc_mcu7t5v0.v and primitives.v and using -DUSE_POWER_PINS=1 -DFUNCTIONAL=1 -DUNIT_DELAY=#1 like for sky130
16:59
Nevermind ... the models use implicit wire definition everywhere so gotta use default_nettype wire ... 🤢
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