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Information / questions / Magic DRC waving
Between 10/31/2025 23:59 and 12/01/2025 00:00
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Egor Lukyanchenko 11/30/2025 14:54
@Leo Moser (mole99) Will it be possible to wave some Magic DRC errors in precheck as long as all KLayout checks are fine? The problem is I'm inconsistently getting Magic DRC errors in factory provided SRAMs. There are several SRAM macros in our testchip design and sometimes weird "Can't overlap those layers" DRC errors are reported inside one or two SRAMs, while others are fine. There is nothing else besides the SRAM internals and dummy fill metals in the DRC area, so it looks like a Magic DRC issue. I'll report the issue itself later, for now I just would like to know if it'll be possible to wave some errors while uploading final GDS to the platform, as I doubt that it'll be possible to debug and fix the issue prior to deadline. (edited)
SRAM and eFUSE testchip for wafer.space MPW runs using the gf180mcu PDK - ZeduloTech/gf180mcu-testchip2025
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Egor Lukyanchenko
@Leo Moser (mole99) Will it be possible to wave some Magic DRC errors in precheck as long as all KLayout checks are fine? The problem is I'm inconsistently getting Magic DRC errors in factory provided SRAMs. There are several SRAM macros in our testchip design and sometimes weird "Can't overlap those layers" DRC errors are reported inside one or two SRAMs, while others are fine. There is nothing else besides the SRAM internals and dummy fill metals in the DRC area, so it looks like a Magic DRC issue. I'll report the issue itself later, for now I just would like to know if it'll be possible to wave some errors while uploading final GDS to the platform, as I doubt that it'll be possible to debug and fix the issue prior to deadline. (edited)
Leo Moser (mole99) 11/30/2025 16:07
Hi Egor, how did you run DRC? Did you use the Nix shell in the template or did you use custom versions of the tools and the PDK? For the final check you should use https://github.com/wafer-space/gf180mcu-precheck, since it will run in the online precheck. Other designs haven't had issues with the SRAMs so far, but you need to flatten a number of cells in magic. Normally, you need to pass both the magic and KLayout DRC deck. Neither DRC deck is a complete implementation and therefore we run both for better coverage. We will likely waive some magic DRC checks (e.g. CO.3 and CO.4) since they were verified to be slightly inaccurate implementations.
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Egor Lukyanchenko 11/30/2025 16:11
I'm running inside the nix environment from the precheck, nothing custom. You could check it yourself with the GDS from the link if you have time, but you have to skip zero polygon check as it will fail on this GDS revision :).
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Leo Moser (mole99) 11/30/2025 18:14
I'll check it tomorrow, no worries about the zero area polygons for now :)
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Leo Moser (mole99)
I'll check it tomorrow, no worries about the zero area polygons for now :)
Egor Lukyanchenko 11/30/2025 18:57
Thanks, Leo! I've fixed zero area polygons in the next revision anyway. Also I saw your review request for the python DRC script, but all my free time is going towards finishing GDS for the tapeout :). I'll try to review the script thoughtfully tomorrow, sorry for the delay.
SRAM and eFUSE testchip for wafer.space MPW runs using the gf180mcu PDK - ZeduloTech/gf180mcu-testchip2025
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