wafer.space Community - Magic error: non-integer magnification

Hi, I was running some prechecks for a multiproject chip and it is failing at certain instance throwing this error: Non-integer magnification (0.2) in transform. Rounding to 0. Has anyone faced something similiar?, and have an idea how to solve it? Thanks, Luighi

@Leo Moser (mole99) / @Tim Edwards - Any ideas on this error?

@LuighiV can you post a link to the layout?

Hi @Leo Moser (mole99) @Tim 'mithro' Ansell this is the link https://drive.google.com/file/d/1GgmRQ5E_GbQYZFp6ogSY1hEyT46GxshO/view?usp=sharing

16:14

In the meantime I was doing some tests, and I think I found the root cause of the issue (seemed to have some empty subhierarchies inside A3) I deleted those empty hierarchies and right now I'm running the pre-checks again to confirm if those were the responsible of raising the error

That's great! However I see some other issues:

16:24

The SRAMs from the default template were not correctly deleted. Their PR_bndry layers still exist and their instances can be found in the cell tree.

1

16:25

The seal ring (guard ring) is missing around the outer padring. (edited)

Leo Moser (mole99)

The SRAMs from the default template were not correctly deleted. Their PR_bndry layers still exist and their instances can be found in the cell tree.

Oh... didn't noticed it, I guessed I have deleted it completely, going to update it, thanks for noticing

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Leo Moser (mole99)

The seal ring (guard ring) is missing around the outer padring. (edited)

regarding the seal ring, do you have a Pcell or script I can use to add it?

I'm adding a check to the precheck to ensure there are some shapes on GUARD_RING_MK: https://github.com/wafer-space/gf180mcu-precheck/pull/36 This way we should catch such issues earlier :)

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LuighiV

regarding the seal ring, do you have a Pcell or script I can use to add it?

This is the PCell: https://github.com/wafer-space/gf180mcu/tree/main/gf180mcuD/libs.tech/klayout/tech/pymacros/sealring_cells

16:38

Did you create the padring using make librelane-padring?

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16:39

This script adds the sealring to the padring: https://github.com/wafer-space/gf180mcu-project-template/blob/01d1540414fefce2d3c8fca2086c425688fe389a/scripts/padring.py#L59

Leo Moser (mole99)

Did you create the padring using make librelane-padring?

yes, I have created it using that instruction

Maybe you deleted it accidentally?

16:42

For me it works fine:

Leo Moser (mole99)

Maybe you deleted it accidentally?

yeah, that's probably the reason, let me generate it again here, thanks for the advice

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You're welcome!

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Hi @Leo Moser (mole99) thanks for your feeback, now the padframe has the sealring and I deleted completly the SRAM devices:

however now I'm facing an issue with DRC errors, because as I'm following the embedded approach, I use a previous padframe we were using for Chipathon, however, that padframe seems to have some issues with CUP DRC. Do you know how can I fix it? (edited)

02:40

this is the report I got:

drc1216.klayout.lyrdb

811.38 KB

@LuighiV - I guess the chipathon padframe needs to be updated with the fixed cells that Leo updated for wafer.space shuttle.

03:11

In theory you should just be able to drop in a replacement?

Hi @Tim 'mithro' Ansell, thanks for the advice

. Yes, I think I can do that, I'm trying right now to update the library from Leo's repo in my environment so it could get the fixed cells. Hope it goes fine

@LuighiV Yes exactly, the bondpad cells have been updated. You need to replace the bondpads in the chipathon padframe with the bondpads in: https://github.com/wafer-space/gf180mcu/blob/main/gf180mcuD/libs.ref/gf180mcu_fd_io/gds/gf180mcu_fd_io.gds Note: only the "Bondpad_5LM" cell has been changed.

Hi @Leo Moser (mole99) thanks for the comment. I've tried to replace the main pads by the new ones in your repo, however, when I run again, it is violating other rules with metal spacing, and the corner pads, have you modified them as well?

LuighiV

Hi @Leo Moser (mole99) thanks for the comment. I've tried to replace the main pads by the new ones in your repo, however, when I run again, it is violating other rules with metal spacing, and the corner pads, have you modified them as well?

No, I didn't modify any other cells. Did you perhaps delete some of the I/O filler cells? The errors always seem to be at the boundary of I/O cells (well, except for the corner cells). (edited)

Hi Leo, I don't think so, I mean, I haven't delete the fills, what I did was just replace the old pads by the new ones by using the Replace cell option in the Cells panel

That sounds like the correct approach. Could you share the current GDS so I can take a look?

yes!, please, give me a moment

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13:03

this is the link: https://drive.google.com/file/d/1GgmRQ5E_GbQYZFp6ogSY1hEyT46GxshO/view?usp=drive_link

chiptop_A_track_ws_embedded__exported.gds

13:04

and this was the report

drc1217.klayout.lyrdb

1.67 MB

@LuighiV - It would be good to load your latest GDS into the platform even if it is currently failing the precheck.

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Something happened when you swapped out the bondpad cells:

13:19

This is the top right corner of the outer padring.

13:19

13:20

And this is the top right corner of the inner padring (chipathon).

13:24

These manual edits are dangerous and error prone. How about we create a KLayout script to merge the GDS files and swap the bondpads? :) Can you share the separate GDS of the empty template project, and the GDS of the chipathon?

Tim 'mithro' Ansell

@LuighiV - It would be good to load your latest GDS into the platform even if it is currently failing the precheck.

sure, I'm going to upload it, thanks

Leo Moser (mole99)

These manual edits are dangerous and error prone. How about we create a KLayout script to merge the GDS files and swap the bondpads? :) Can you share the separate GDS of the empty template project, and the GDS of the chipathon?

that would be great

, let me restore the previous version of the chipathon then, and going to share both

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Hi @Tim 'mithro' Ansell I'm having issues to upload from Google Drive. I was using this link https://drive.google.com/file/d/1GgmRQ5E_GbQYZFp6ogSY1hEyT46GxshO/view but it says it has size 0. I've tried with github but it has more than 100Mb so doesn't allow me to upload there

chiptop_A_track_ws_embedded__exported.gds

@LuighiV Tim is currently asleep. You need a direct link to your layout. However you can compress it, if you didn't already?

Leo Moser (mole99)

@LuighiV Tim is currently asleep. You need a direct link to your layout. However you can compress it, if you didn't already?

that's a good point, let me try it here

LuighiV

that would be great

, let me restore the previous version of the chipathon then, and going to share both

Hi @Leo Moser (mole99) regarding this point, these are the links for :

LuighiV

that's a good point, let me try it here

It worked! thanks, now it is running the checks

LuighiV

Hi @Leo Moser (mole99) regarding this point, these are the links for :

It seems I got it working, but there is something very strange going on, as you can see: