DRC Run Report at drc: script='/home/luighi/mosbius-project/gf180mcu-precheck/gf180mcu/gf180mcuD/libs.tech/klayout/tech/drc/gf180mcu.drc' chip_top DF.1a_LV DF.1a_LV : Min. COMP Width. : 0.22µm DF.1a_MV DF.1a_MV : Min. COMP Width. : 0.3µm DF.1c DF.1c : Min. COMP Width for MOSCAP. : 1µm DF.2a_LV DF.2a_LV : Min Channel Width. : 0.22µm DF.2a_MV DF.2a_MV : Min Channel Width. : nil,0.3µm DF.2b DF.2b : Max. COMP width for all cases except those used for capacitors, marked by 'MOS_CAP_MK' layer: 100um DF.3a_LV DF.3a_LV : Min. COMP Space is : 0.28µm. [P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same] DF.3a_MV DF.3a_MV : Min. COMP Space is : 0.36µm. [P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same] DF.3b DF.3b : Min./Max. NCOMP Space to PCOMP in the same well for butted COMP (MOSCAP butting is not allowed): 0 um DF.3c_LV DF.3c_LV : Min. COMP Space in BJT area (area marked by DRC_BJT layer). : 0.32µm DF.3c_MV DF.3c_MV : Min. COMP Space in BJT area (area marked by DRC_BJT layer) hasn't been assessed. DF.4a_LV DF.4a_LV : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.12µm DF.4a_MV DF.4a_MV : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.16µm DF.4b_LV DF.4b_LV : Min. DNWELL overlap of NCOMP well tap. : 0.62µm DF.4b_MV DF.4b_MV : Min. DNWELL overlap of NCOMP well tap. : 0.66µm DF.4c_LV DF.4c_LV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.43µm DF.4c_MV DF.4c_MV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.6µm DF.4d_LV DF.4d_LV : Min. (Nwell overlap of NCOMP) outside DNWELL. : 0.12µm DF.4d_MV DF.4d_MV : Min. (Nwell overlap of NCOMP) outside DNWELL. : 0.16µm DF.4e_LV DF.4e_LV : Min. DNWELL overlap of PCOMP. : 0.93µm DF.4e_MV DF.4e_MV : Min. DNWELL overlap of PCOMP. : 1.1µm DF.5_LV DF.5_LV : Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. : 0.12µm DF.5_MV DF.5_MV : Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. : 0.16µm DF.6_LV DF.6_LV : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.24µm DF.6_MV DF.6_MV : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.4µm DF.7_LV DF.7_LV : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.43µm DF.7_MV DF.7_MV : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.6µm DF.8_LV DF.8_LV : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.43µm DF.8_MV DF.8_MV : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.6µm DF.9 DF.9 : Min. COMP area (um2). : 0.2025µm² DF.10 DF.10 : Min. field area (um2). : 0.26µm² DF.11 DF.11 : Min. Length of butting COMP edge. : 0.3µm DF.12 DF.12 : COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking). DF.13_LV DF.13_LV : Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell): 20um DF.13_MV DF.13_MV : Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell): 15um DF.14_LV DF.14_LV : Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell): 20um DF.14_MV DF.14_MV : Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell): 15um DF.16_LV DF.16_LV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.43µm DF.16_MV DF.16_MV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.6µm DF.17_LV DF.17_LV : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.12µm DF.17_MV DF.17_MV : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.16µm DF.18 DF.18 : Min. DNWELL space to (PCOMP outside Nwell and DNWELL). : 2.5µm DF.19_LV DF.19_LV : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.2µm DF.19_MV DF.19_MV : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.28µm CO.1 CO.1 : Min/max contact size. : 0.22µm CO.2a CO.2a : min. contact spacing : 0.25µm CO.2b CO.2b : Space in 4x4 or larger contact array. : 0.28µm CO.3 CO.3 : Poly2 overlap of contact. : 0.07µm CO.4 CO.4 : COMP overlap of contact. : 0.07µm CO.5a CO.5a : Nplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). : 0.1µm CO.5b CO.5b : Pplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). : 0.1µm CO.6 CO.6 : Metal1 overlap of contact >= 0.005 um CO.6a CO.6a : (i) Metal1 (< 0.34um) end-of-line overlap contact (Applies to all < 0.34µm wide metal lines, excluding metal branches shorter than 0.24µm) : 0.06µm CO.6b CO.6b : (ii) If Metal1 overlaps contact by < 0.04um on one side, adjacent metal1 edges overlap : 0.06µm CO.7 CO.7 : Space from COMP contact to Poly2 on COMP. : 0.15µm CO.8 CO.8 : Space from Poly2 contact to COMP. : 0.17µm CO.9 CO.9 : Contact on NCOMP to PCOMP butting edge is forbidden (contact must not straddle butting edge). CO.10 CO.10 : Contact on Poly2 gate over COMP is forbidden. CO.11 CO.11 : Contact on field oxide is forbidden. DN.1 DN.1 : Min. DNWELL Width : 1.7µm DN.2a DN.2a : Min. DNWELL Space (Equi-potential), Merge if the space is less than : 2.5µm DN.2b DN.2b : Min. DNWELL Space (Different potential) : 5.42µm DN.3 DN.3 : Each DNWELL shall be directly surrounded by PCOMP guard ring tied to the P-substrate potential. BJT.1 BJT.1 : Min. DRC_BJT overlap of DNWELL for NPN BJT: 0um BJT.2 BJT.2 : Min. DRC_BJT overlap of PCOM in Psub: 0um BJT.3 BJT.3 : Minimum space of DRC_BJT layer to unrelated COMP. : 0.1µm DV.1 DV.1 : Min. Dualgate enclose DNWELL. : 0.5µm DV.2 DV.2 : Min. Dualgate Space. Merge if Space is less than this design rule. : 0.44µm DV.3 DV.3 : Min. Dualgate to COMP space [unrelated]. : 0.24µm DV.5 DV.5 : Min. Dualgate width. : 0.7µm DV.6 DV.6 : Min. Dualgate enclose COMP (except substrate tap). : 0.24µm DV.7 DV.7 : COMP (except substrate tap) can not be partially overlapped by Dualgate. DV.8 DV.8 : Min Dualgate enclose Poly2. : 0.4µm DV.9 DV.9 : 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL. EF.01 EF.01 : Min. (Poly2 butt PLFUSE) within EFUSE_MK and Pplus: 0um EF.02 EF.02 : Min./Max. PLFUSE width: 0.18µm EF.03 EF.03 : Min. Max. PLFUSE length: 1.26µm EF.04a EF.04a : Min. Max. PLFUSE overlap Poly2 (coinciding permitted) and touch cathode and anode. EF.04b EF.04b : PLFUSE must be rectangular. EF.04c EF.04c : Cathode Poly2 must be rectangular. EF.04d EF.04d : Anode Poly2 must be rectangular. EF.05 EF.05 : Min./Max. LVS_Source overlap Poly2 (at Anode): 0um EF.06 EF.06 : Min./Max. Cathode Poly2 width: 2.26µm EF.07 EF.07 : Min./Max. Cathode Poly2 length: 1.84µm EF.08 EF.08 : Min./Max. Anode Poly2 width: 1.06µm EF.09 EF.09 : Min./Max. Anode Poly2 length: 2.43µm EF.10 EF.10 : Min. Cathode Poly2 to Poly2 space: 0.26µm EF.11 EF.11 : Min. Anode Poly2 to Poly2 space: 0.26µm EF.12 EF.12 : Min. Space of Cathode Contact to PLFUSE end. EF.13 EF.13 : Min. Space of Anode Contact to PLFUSE end. EF.14 EF.14 : Min. EFUSE_MK enclose LVS_Source. EF.15 EF.15 : NO Contact is allowed to touch PLFUSE. EF.16a EF.16a : Cathode must contain exact number of Contacts at each ends: 4µm EF.16b EF.16b : Anode must contain exact number of Contacts at each ends: 4µm EF.17 EF.17 : Min. Space of EFUSE_MK to EFUSE_MK: 0.26µm EF.18 EF.18 : PLFUSE must sit on field oxide (NOT COMP), no cross with any COMP, Nplus, Pplus, ESD, SAB, Resistor, Metal1, Metal2. EF.19 EF.19 : Min. PLFUSE space to Metal1, Metal2. EF.20 EF.20 : Min. PLFUSE space to COMP, Nplus, Pplus, Resistor, ESD, SAB: 2.73µm EF.21 EF.21 : Min./Max. eFUSE Poly2 length: 5.53µm EF.22a EF.22a : Min./Max. Cathode Poly2 overlap with PLFUSE in width direction: 1.04µm EF.22b EF.22b : Min./Max. Anode Poly2 overlap with PLFUSE in width direction: 0.44µm ESD.1 ESD.1 : Minimum width of an ESD implant area. : 0.6µm ESD.2 ESD.2 : Minimum space between two ESD implant areas. (Merge if the space is less than 0.6um). : 0.6µm ESD.3a ESD.3a : Minimum space to NCOMP. : 0.6µm ESD.3b ESD.3b : Min/max space to a butted PCOMP. ESD.4a ESD.4a : Extension beyond NCOMP. : 0.24µm ESD.4b ESD.4b : Minimum overlap of an ESD implant edge to a COMP. : 0.45µm ESD.5a ESD.5a : Minimum ESD area (um2). : 0.49µm² ESD.5b ESD.5b : Minimum field area enclosed by ESD implant (um2). : 0.49µm² ESD.6 ESD.6 : Extension perpendicular to Poly2 gate. : 0.45µm ESD.7 ESD.7 : No ESD implant inside PCOMP. ESD.8 ESD.8 : Minimum space to Nplus/Pplus. : 0.3µm ESD.pl ESD.pl : Minimum gate length of 5V/6V gate NMOS. : 0.8µm ESD.9 ESD.9 : ESD implant layer must be overlapped by Dualgate layer (as ESD implant option is only for 5V/6V devices). ESD.10 ESD.10 : LVS_IO shall be drawn covering I/O MOS active area by minimum overlap. comp_OFFGRID OFFGRID : OFFGRID vertex on comp comp_angle ACUTE : non 45 degree angle comp dnwell_OFFGRID OFFGRID : OFFGRID vertex on dnwell dnwell_angle ACUTE : non 45 degree angle dnwell nwell_OFFGRID OFFGRID : OFFGRID vertex on nwell nwell_angle ACUTE : non 45 degree angle nwell lvpwell_OFFGRID OFFGRID : OFFGRID vertex on lvpwell lvpwell_angle ACUTE : non 45 degree angle lvpwell dualgate_OFFGRID OFFGRID : OFFGRID vertex on dualgate dualgate_angle ACUTE : non 45 degree angle dualgate poly2_OFFGRID OFFGRID : OFFGRID vertex on poly2 poly2_angle ACUTE : non 45 degree angle poly2 nplus_OFFGRID OFFGRID : OFFGRID vertex on nplus nplus_angle ACUTE : non 45 degree angle nplus pplus_OFFGRID OFFGRID : OFFGRID vertex on pplus pplus_angle ACUTE : non 45 degree angle pplus sab_OFFGRID OFFGRID : OFFGRID vertex on sab sab_angle ACUTE : non 45 degree angle sab esd_OFFGRID OFFGRID : OFFGRID vertex on esd esd_angle ACUTE : non 45 degree angle esd resistor_OFFGRID OFFGRID : OFFGRID vertex on resistor resistor_angle ACUTE : non 45 degree angle resistor fhres_OFFGRID OFFGRID : OFFGRID vertex on fhres fhres_angle ACUTE : non 45 degree angle fhres fusetop_OFFGRID OFFGRID : OFFGRID vertex on fusetop fusetop_angle ACUTE : non 45 degree angle fusetop fusewindow_d_OFFGRID OFFGRID : OFFGRID vertex on fusewindow_d fusewindow_d_angle ACUTE : non 45 degree angle fusewindow_d polyfuse_OFFGRID OFFGRID : OFFGRID vertex on polyfuse polyfuse_angle ACUTE : non 45 degree angle polyfuse mvsd_OFFGRID OFFGRID : OFFGRID vertex on mvsd mvsd_angle ACUTE : non 45 degree angle mvsd mvpsd_OFFGRID OFFGRID : OFFGRID vertex on mvpsd mvpsd_angle ACUTE : non 45 degree angle mvpsd nat_OFFGRID OFFGRID : OFFGRID vertex on nat nat_angle ACUTE : non 45 degree angle nat comp_dummy_OFFGRID OFFGRID : OFFGRID vertex on comp_dummy comp_dummy_angle ACUTE : non 45 degree angle comp_dummy poly2_dummy_OFFGRID OFFGRID : OFFGRID vertex on poly2_dummy poly2_dummy_angle ACUTE : non 45 degree angle poly2_dummy schottky_diode_OFFGRID OFFGRID : OFFGRID vertex on schottky_diode schottky_diode_angle ACUTE : non 45 degree angle schottky_diode zener_OFFGRID OFFGRID : OFFGRID vertex on zener zener_angle ACUTE : non 45 degree angle zener res_mk_OFFGRID OFFGRID : OFFGRID vertex on res_mk res_mk_angle ACUTE : non 45 degree angle res_mk opc_drc_OFFGRID OFFGRID : OFFGRID vertex on opc_drc opc_drc_angle ACUTE : non 45 degree angle opc_drc ndmy_OFFGRID OFFGRID : OFFGRID vertex on ndmy ndmy_angle ACUTE : non 45 degree angle ndmy pmndmy_OFFGRID OFFGRID : OFFGRID vertex on pmndmy pmndmy_angle ACUTE : non 45 degree angle pmndmy v5_xtor_OFFGRID OFFGRID : OFFGRID vertex on v5_xtor v5_xtor_angle ACUTE : non 45 degree angle v5_xtor cap_mk_OFFGRID OFFGRID : OFFGRID vertex on cap_mk cap_mk_angle ACUTE : non 45 degree angle cap_mk mos_cap_mk_OFFGRID OFFGRID : OFFGRID vertex on mos_cap_mk mos_cap_mk_angle ACUTE : non 45 degree angle mos_cap_mk ind_mk_OFFGRID OFFGRID : OFFGRID vertex on ind_mk ind_mk_angle ACUTE : non 45 degree angle ind_mk diode_mk_OFFGRID OFFGRID : OFFGRID vertex on diode_mk diode_mk_angle ACUTE : non 45 degree angle diode_mk drc_bjt_OFFGRID OFFGRID : OFFGRID vertex on drc_bjt drc_bjt_angle ACUTE : non 45 degree angle drc_bjt lvs_bjt_OFFGRID OFFGRID : OFFGRID vertex on lvs_bjt lvs_bjt_angle ACUTE : non 45 degree angle lvs_bjt mim_l_mk_OFFGRID OFFGRID : OFFGRID vertex on mim_l_mk mim_l_mk_angle ACUTE : non 45 degree angle mim_l_mk latchup_mk_OFFGRID OFFGRID : OFFGRID vertex on latchup_mk latchup_mk_angle ACUTE : non 45 degree angle latchup_mk guard_ring_mk_OFFGRID OFFGRID : OFFGRID vertex on guard_ring_mk guard_ring_mk_angle ACUTE : non 45 degree angle guard_ring_mk otp_mk_OFFGRID OFFGRID : OFFGRID vertex on otp_mk otp_mk_angle ACUTE : non 45 degree angle otp_mk mtpmark_OFFGRID OFFGRID : OFFGRID vertex on mtpmark mtpmark_angle ACUTE : non 45 degree angle mtpmark neo_ee_mk_OFFGRID OFFGRID : OFFGRID vertex on neo_ee_mk neo_ee_mk_angle ACUTE : non 45 degree angle neo_ee_mk sramcore_OFFGRID OFFGRID : OFFGRID vertex on sramcore sramcore_angle ACUTE : non 45 degree angle sramcore lvs_rf_OFFGRID OFFGRID : OFFGRID vertex on lvs_rf lvs_rf_angle ACUTE : non 45 degree angle lvs_rf lvs_drain_OFFGRID OFFGRID : OFFGRID vertex on lvs_drain lvs_drain_angle ACUTE : non 45 degree angle lvs_drain hvpolyrs_OFFGRID OFFGRID : OFFGRID vertex on hvpolyrs hvpolyrs_angle ACUTE : non 45 degree angle hvpolyrs lvs_io_OFFGRID OFFGRID : OFFGRID vertex on lvs_io lvs_io_angle ACUTE : non 45 degree angle lvs_io probe_mk_OFFGRID OFFGRID : OFFGRID vertex on probe_mk probe_mk_angle ACUTE : non 45 degree angle probe_mk esd_mk_OFFGRID OFFGRID : OFFGRID vertex on esd_mk esd_mk_angle ACUTE : non 45 degree angle esd_mk lvs_source_OFFGRID OFFGRID : OFFGRID vertex on lvs_source lvs_source_angle ACUTE : non 45 degree angle lvs_source well_diode_mk_OFFGRID OFFGRID : OFFGRID vertex on well_diode_mk well_diode_mk_angle ACUTE : non 45 degree angle well_diode_mk ldmos_xtor_OFFGRID OFFGRID : OFFGRID vertex on ldmos_xtor ldmos_xtor_angle ACUTE : non 45 degree angle ldmos_xtor plfuse_OFFGRID OFFGRID : OFFGRID vertex on plfuse plfuse_angle ACUTE : non 45 degree angle plfuse efuse_mk_OFFGRID OFFGRID : OFFGRID vertex on efuse_mk efuse_mk_angle ACUTE : non 45 degree angle efuse_mk mcell_feol_mk_OFFGRID OFFGRID : OFFGRID vertex on mcell_feol_mk mcell_feol_mk_angle ACUTE : non 45 degree angle mcell_feol_mk ymtp_mk_OFFGRID OFFGRID : OFFGRID vertex on ymtp_mk ymtp_mk_angle ACUTE : non 45 degree angle ymtp_mk dev_wf_mk_OFFGRID OFFGRID : OFFGRID vertex on dev_wf_mk dev_wf_mk_angle ACUTE : non 45 degree angle dev_wf_mk comp_label_OFFGRID OFFGRID : OFFGRID vertex on comp_label comp_label_angle ACUTE : non 45 degree angle comp_label poly2_label_OFFGRID OFFGRID : OFFGRID vertex on poly2_label poly2_label_angle ACUTE : non 45 degree angle poly2_label mdiode_OFFGRID OFFGRID : OFFGRID vertex on mdiode mdiode_angle ACUTE : non 45 degree angle mdiode contact_OFFGRID OFFGRID : OFFGRID vertex on contact contact_angle ACUTE : non 45 degree angle contact metal1_OFFGRID OFFGRID : OFFGRID vertex on metal1 metal1_angle ACUTE : non 45 degree angle metal1 metal1_slot_OFFGRID OFFGRID : OFFGRID vertex on metal1_slot metal1_slot_angle ACUTE : non 45 degree angle metal1_slot metal1_blk_OFFGRID OFFGRID : OFFGRID vertex on metal1_blk metal1_blk_angle ACUTE : non 45 degree angle metal1_blk metal1_label_OFFGRID OFFGRID : OFFGRID vertex on metal1_label metal1_label_angle ACUTE : non 45 degree angle metal1_label via1_OFFGRID OFFGRID : OFFGRID vertex on via1 via1_angle ACUTE : non 45 degree angle via1 metal2_OFFGRID OFFGRID : OFFGRID vertex on metal2 metal2_angle ACUTE : non 45 degree angle metal2 metal2_label_OFFGRID OFFGRID : OFFGRID vertex on metal2_label metal2_label_angle ACUTE : non 45 degree angle metal2_label metal2_slot_OFFGRID OFFGRID : OFFGRID vertex on metal2_slot metal2_slot_angle ACUTE : non 45 degree angle metal2_slot metal2_blk_OFFGRID OFFGRID : OFFGRID vertex on metal2_blk metal2_blk_angle ACUTE : non 45 degree angle metal2_blk via2_OFFGRID OFFGRID : OFFGRID vertex on via2 via2_angle ACUTE : non 45 degree angle via2 metal3_OFFGRID OFFGRID : OFFGRID vertex on metal3 metal3_angle ACUTE : non 45 degree angle metal3 metal3_dummy_OFFGRID OFFGRID : OFFGRID vertex on metal3_dummy metal3_dummy_angle ACUTE : non 45 degree angle metal3_dummy metal3_label_OFFGRID OFFGRID : OFFGRID vertex on metal3_label metal3_label_angle ACUTE : non 45 degree angle metal3_label metal3_blk_OFFGRID OFFGRID : OFFGRID vertex on metal3_blk metal3_blk_angle ACUTE : non 45 degree angle metal3_blk via3_OFFGRID OFFGRID : OFFGRID vertex on via3 via3_angle ACUTE : non 45 degree angle via3 metal4_OFFGRID OFFGRID : OFFGRID vertex on metal4 metal4_angle ACUTE : non 45 degree angle metal4 metal4_dummy_OFFGRID OFFGRID : OFFGRID vertex on metal4_dummy metal4_dummy_angle ACUTE : non 45 degree angle metal4_dummy metal4_label_OFFGRID OFFGRID : OFFGRID vertex on metal4_label metal4_label_angle ACUTE : non 45 degree angle metal4_label metal4_blk_OFFGRID OFFGRID : OFFGRID vertex on metal4_blk metal4_blk_angle ACUTE : non 45 degree angle metal4_blk via4_OFFGRID OFFGRID : OFFGRID vertex on via4 via4_angle ACUTE : non 45 degree angle via4 metal5_OFFGRID OFFGRID : OFFGRID vertex on metal5 metal5_angle ACUTE : non 45 degree angle metal5 metal5_dummy_OFFGRID OFFGRID : OFFGRID vertex on metal5_dummy metal5_dummy_angle ACUTE : non 45 degree angle metal5_dummy metal5_label_OFFGRID OFFGRID : OFFGRID vertex on metal5_label metal5_label_angle ACUTE : non 45 degree angle metal5_label metal5_blk_OFFGRID OFFGRID : OFFGRID vertex on metal5_blk metal5_blk_angle ACUTE : non 45 degree angle metal5_blk pad_OFFGRID OFFGRID : OFFGRID vertex on pad pad_angle ACUTE : non 45 degree angle pad ubmpperi_OFFGRID OFFGRID : OFFGRID vertex on ubmpperi ubmpperi_angle ACUTE : non 45 degree angle ubmpperi ubmparray_OFFGRID OFFGRID : OFFGRID vertex on ubmparray ubmparray_angle ACUTE : non 45 degree angle ubmparray ubmeplate_OFFGRID OFFGRID : OFFGRID vertex on ubmeplate ubmeplate_angle ACUTE : non 45 degree angle ubmeplate metal1_res_OFFGRID OFFGRID : OFFGRID vertex on metal1_res metal1_res_angle ACUTE : non 45 degree angle metal1_res metal2_res_OFFGRID OFFGRID : OFFGRID vertex on metal2_res metal2_res_angle ACUTE : non 45 degree angle metal2_res metal3_res_OFFGRID OFFGRID : OFFGRID vertex on metal3_res metal3_res_angle ACUTE : non 45 degree angle metal3_res metal4_res_OFFGRID OFFGRID : OFFGRID vertex on metal4_res metal4_res_angle ACUTE : non 45 degree angle metal4_res metal5_res_OFFGRID OFFGRID : OFFGRID vertex on metal5_res metal5_res_angle ACUTE : non 45 degree angle metal5_res metal6_res_OFFGRID OFFGRID : OFFGRID vertex on metal6_res metal6_res_angle ACUTE : non 45 degree angle metal6_res pr_bndry_OFFGRID OFFGRID : OFFGRID vertex on pr_bndry pr_bndry_angle ACUTE : non 45 degree angle pr_bndry border_OFFGRID OFFGRID : OFFGRID vertex on border border_angle ACUTE : non 45 degree angle border HRES.1 HRES.1 : Minimum space: 0.4µm. Note: Merge if the spacing is less than 0.4 um. HRES.2 HRES.2 : Minimum width of Poly2 resistor: 1µm HRES.3 HRES.3 : Minimum space between Poly2 resistors: 0.4µm HRES.4 HRES.4 : Minimum RESISTOR overlap of Poly2 resistor: 0.4µm HRES.5 HRES.5 : Minimum RESISTOR space to unrelated Poly2: 0.3µm HRES.6 HRES.6 : Minimum RESISTOR space to COMP: 0.3um HRES.7 HRES.7 : Minimum Pplus overlap of contact on Poly2 resistor: 0.2µm HRES.8 HRES.8 : Minimum space from salicide block to contact on Poly2 resistor: 0.22.um HRES.9 HRES.9 : Minimum salicide block overlap of Poly2 resistor in width direction: 0.28.um HRES.10 HRES.10 : Minimum & maximum Pplus overlap of SAB: 0.1.um HRES.12a HRES.12a : P type Poly2 resistor (high sheet rho) shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by Pplus space) and width covering the width of Poly2. HRES.12b HRES.12b : If the size of single RES_MK mark layer is greater than 15000 um2 and both side (X and Y) are greater than 80 um. Then the minimum spacing to adjacent RES_MK layer: 20µm MDN.1 MDN.1 : Min MVSD width (for litho purpose). : 1µm MDN.2a MDN.2a : Min MVSD space [Same Potential]. : 1µm MDN.2b MDN.2b : Min MVSD space [Diff Potential]. : 2µm MDN.3a MDN.3a : Min transistor channel length. : 0.6µm MDN.3b MDN.3b : Max transistor channel length: 20um MDN.4a MDN.4a : Min transistor channel width. : 4µm MDN.4b MDN.4b : Max transistor channel width : 50 um MDN.5ai MDN.5ai : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap non-butted): 1um. PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. MDN.5aii MDN.5aii : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap butted): 0.92um. PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. : 0.92µm MDN.5b MDN.5b : Min PCOMP (Pplus AND COMP) space to LDNMOS Source (Nplus AND COMP): 0.4um. Use butted source and p-substrate tab otherwise and that is good for Latch-up immunity as well. MDN.5c MDN.5c : Maximum distance of the nearest edge of the substrate tab from NCOMP edge: 15µm MDN.6 MDN.6 : ALL LDNMOS shall be covered by Dualgate layer. MDN.6a MDN.6a : Min Dualgate enclose NCOMP. MDN.7 MDN.7 : Each LDNMOS shall be covered by LDMOS_XTOR (GDS#226) mark layer. MDN.7a MDN.7a : Min LDMOS_XTOR enclose Dualgate.: 0 um MDN.8a MDN.8a : Min LDNMOS drain MVSD space to any other equal potential Nwell space. MDN.8b MDN.8b : Min LDNMOS drain MVSD space to any other different potential Nwell space. MDN.9 MDN.9 : Min LDNMOS drain MVSD space to NCOMP (Nplus AND COMP) outside LDNMOS drain MVSD. : 4µm MDN.10a MDN.10a : Min LDNMOS POLY2 width. : 1.2µm MDN.10b MDN.10b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDNMOS drain direction). : 0.4µm MDN.10c MDN.10c : Min/Max POLY2 extension beyond COMP on the field towards LDNMOS drain COMP direction.: 0.2 um MDN.10d MDN.10d : Min/Max POLY2 on field space to LDNMOS drain COMP. MDN.10ei MDN.10ei : Min POLY2 space to Psub tap (source and body tap non-butted). MDN.10eii MDN.10eii : Min POLY2 space to Psub tap (source and body tap butted). : 0.32µm MDN.10f MDN.10f : Poly2 interconnect in HV region (LDMOS_XTOR marked region) not allowed. Also, any Poly2 interconnect with poly2 to substrate potential greater than 6V is not allowed. MDN.11 MDN.11 : Min/Max MVSD overlap channel COMP ((((LDMOS_XTOR AND MVSD) AND COMP) AND POLY2) AND NPlus). MDN.12 MDN.12 : Min MVSD enclose NCOMP in the LDNMOS drain and in the direction along the transistor width. MDN.13a MDN.13a : Max single finger width. : 50µm MDN.13b MDN.13b : Layout shall have alternative source & drain. MDN.13c MDN.13c : Both sides of the transistor shall be terminated by source. MDN.13d MDN.13d : Every two poly fingers shall be surrounded by a P-sub guard ring. (Exclude the case when each LDNMOS transistor have full width butting to well tap). MDN.14 MDN.14 : Min MVSD space to any DNWELL. MDN.15a MDN.15a : Min LDNMOS drain COMP width. : 0.22µm MDN.15b MDN.15b : Min LDNMOS drain COMP enclose contact. : 0µm MDN.17 MDN.17 : It is recommended to surround the LDNMOS transistor with non-broken Psub guard ring to improve the latch up immunity. Guideline to improve the latch up immunity. MDP.1 MDP.1 : Minimum transistor channel length. : 0.6µm MDP.1a MDP.1a : Max transistor channel length. MDP.2 MDP.2 : Minimum transistor channel width. : 4µm MDP.3 MDP.3 : Each LDPMOS shall be surrounded by non-broken Nplus guard ring inside DNWELL MDP.3ai MDP.3ai : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap non-butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed. MDP.3aii MDP.3aii : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed. MDP.3b MDP.3b : Min NCOMP (Nplus AND COMP) space to PCOMP in DNWELL (Pplus AND COMP AND DNWELL). Use butted source and DNWELL contacts otherwise and that is best for Latch-up immunity as well. : 0.4µm MDP.3c MDP.3c : Maximum distance of the nearest edge of the DNWELL tab (NCOMP inside DNWELL) from PCOMP edge (PCOMP inside DNWELL). : 15µm MDP.3d MDP.3d : The metal connection for the Nplus guard ring recommended to be continuous. The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability. : 10µm MDP.4 MDP.4 : DNWELL covering LDPMOS shall be surrounded by non broken Pplus guard. The metal connection for the Pplus guard ring recommended to be continuous, The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability. MDP.4a MDP.4a : Min PCOMP (Pplus AND COMP) space to DNWELL. : 2.5µm MDP.4b MDP.4b : Maximum distance of the nearest edge of the DNWELL from the PCOMP Guard ring outside DNWELL. : 15µm MDP.5 MDP.5 : Each LDPMOS shall be covered by Dualgate layer. MDP.5a MDP.5a : Minimum Dualgate enclose Plus guarding ring PCOMP (Pplus AND COMP). : 0.5µm MDP.6 MDP.6 : Each LDPMOS shall be covered by LDMOS_XTOR (GDS#226) layer. MDP.6a MDP.6a : Minimum LDMOS_XTOR enclose Dualgate. MDP.7 MDP.7 : Minimum LDMOS_XTOR layer space to Nwell outside LDMOS_XTOR. : 2µm MDP.8 MDP.8 : Minimum LDMOS_XTOR layer space to NCOMP outside LDMOS_XTOR. : 1.5µm MDP.9a MDP.9a : Min LDPMOS POLY2 width. : 1.2µm MDP.9b MDP.9b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDMOS drain direction). : 0.4µm MDP.9c MDP.9c : Min/Max POLY2 extension beyond COMP on the field towards LDPMOS drain (MVPSD AND COMP AND Pplus NOT POLY2) direction. MDP.9d MDP.9d : Min/Max POLY2 on field to LDPMOS drain COMP (MVPSD AND COMP AND Pplus NOT POLY2) space. MDP.9ei MDP.9ei : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap non-butted). MDP.9eii MDP.9eii : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap butted): 0.32um MDP.9f MDP.9f : Poly2 interconnect is not allowed in LDPMOS region (LDMOS_XTOR marked region). MDP.10 MDP.10 : Min/Max MVPSD overlap onto the channel (LDMOS_XTOR AND COMP AND POLY2 AND Pplus): 0.4 um MDP.10a MDP.10a : Min MVPSD space within LDMOS_XTOR marking [diff potential]. : 2µm MDP.10b MDP.10b : Min MVPSD space [same potential]. Merge if space less than 1um. : 1µm MDP.11 MDP.11 : Min MVPSD enclosing PCOMP in the drain (MVPSD AND COMP NOT POLY2) direction and in the direction along the transistor width. MDP.12 MDP.12 : Min DNWELL enclose Nplus guard ring (NCOMP). : 0.66µm MDP.13a MDP.13a : Max single finger width. : 50µm MDP.13b MDP.13b : Layout shall have alternative source & drain. MDP.13c MDP.13c : Both sides of the transistor shall be terminated by source. MDP.15 MDP.15 : Min DNWELL enclosing MVPSD to any DNWELL spacing. : 6µm MDP.16a MDP.16a : Min LDPMOS drain COMP width. : 0.22µm MDP.16b MDP.16b : Min LDPMOS drain COMP enclose contact. : 0µm MDP.17a MDP.17a : For better latch up immunity, it is necessary to put DNWELL guard ring between MVPSD Inside DNWELL covered by LDMOS_XTOR and NCOMP (outside DNWELL and outside Nwell) when spacing between them is less than 40um. MDP.17c MDP.17c : DNWELL guard ring shall have NCOMP tab to be connected to highest potential LRES.1 LRES.1 : Minimum width of Poly2 resistor: 0.8µm LRES.2 LRES.2 : Minimum space between Poly2 resistors: 0.4µm LRES.3 LRES.3 : Minimum space from Poly2 resistor to COMP: 0.6.um LRES.4 LRES.4 : Minimum space from Poly2 resistor to unrelated Poly2: 0.6µm LRES.5 LRES.5 : Minimum Nplus implant overlap of Poly2 resistor: 0.3µm LRES.6 LRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction: 0.28µm LRES.7 LRES.7 : Minimum space from salicide block to contact on Poly2 resistor: 0.22.um LRES.9a LRES.9a : Nplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. LRES.9b LRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer: 20µm LPW.1_LV LPW.1_LV : Min. LVPWELL Width. : 0.6µm LPW.1_MV LPW.1_MV : Min. LVPWELL Width. : 0.74µm LPW.2a_LV LPW.2a_LV : Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. : 1.4µm LPW.2a_MV LPW.2a_MV : Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. : 1.7µm LPW.2b_LV LPW.2b_LV : Min. LVPWELL to LVPWELL Space [Equi potential]. : 0.86µm LPW.2b_MV LPW.2b_MV : Min. LVPWELL to LVPWELL Space [Equi potential]. : 0.86µm LPW.3 LPW.3 : Min. DNWELL enclose LVPWELL. : 2.5µm LPW.5 LPW.5 : LVPWELL resistors must be enclosed by DNWELL. LPW.11 LPW.11 : Min. (LVPWELL outside DNWELL) space to DNWELL. : 1.5µm LPW.12 LPW.12 : LVPWELL cannot overlap with Nwell. LVS_BJT.1 LVS_BJT.1 : Minimum LVS_BJT enclosure of NPN or PNP Emitter COMP layers: 0um MC.1 MC.1 : min. mcell width : 0.4µm MC.2 MC.2 : min. mcell spacing : 0.4µm MC.3 MC.3 : Minimum Mcell area : 0.35µm² MC.4 MC.4 : Minimum area enclosed by Mcell : 0.35µm² M1.1 M1.1 : min. metal1 width : 0.23µm M1.2a M1.2a : min. metal1 spacing : 0.23µm M1.2b M1.2b : Space to wide Metal1 (length & width > 10um) : 0.3µm M1.3 M1.3 : Minimum Metal1 area : 0.1444µm² M2.1 M2.1 : min. metal2 width : 0.28µm M2.2a M2.2a : min. metal2 spacing : 0.28µm M2.2b M2.2b : Space to wide Metal2 (length & width > 10um) : 0.3µm M2.3 M2.3 : Minimum metal2 area : 0.1444µm² M3.1 M3.1 : min. metal3 width : 0.28µm M3.2a M3.2a : min. metal3 spacing : 0.28µm M3.2b M3.2b : Space to wide Metal3 (length & width > 10um) : 0.3µm M3.3 M3.3 : Minimum metal3 area : 0.1444µm² M4.1 M4.1 : min. metal4 width : 0.28µm M4.2a M4.2a : min. metal4 spacing : 0.28µm M4.2b M4.2b : Space to wide Metal4 (length & width > 10um) : 0.3µm M4.3 M4.3 : Minimum metal4 area : 0.1444µm² MT.1 MT.1 : min. metaltop width : 0.44µm MT.2a MT.2a : min. metaltop spacing : 0.46µm MT.2b MT.2b : Space to wide metaltop (length & width > 10um) : 0.6µm MT.4 MT.4 : Minimum MetalTop area : 0.5625µm² MIMTM.1 MIMTM.1 : Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). : 1.2µm MIMTM.2 MIMTM.2 : Minimum MiM bottom plate overlap of Vian-1 layer. [This is applicable for Vian-1 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. : 0.4µm MIMTM.3 MIMTM.3 : Minimum MiM bottom plate overlap of Top plate. MIMTM.4 MIMTM.4 : Minimum MiM top plate (FuseTop) overlap of Vian-1: 0.4µm MIMTM.5 MIMTM.5 : Minimum spacing between top plate and the Vian-1 connecting to the bottom plate. : 0.4µm MIMTM.6 MIMTM.6 : Minimum spacing between unrelated top plates: 0.6µm MIMTM.7 MIMTM.7 : Min FuseTop enclosure by CAP_MK: 0um. MIMTM.8a MIMTM.8a : Minimum MIM cap area (defined by FuseTop area): 25µm² MIMTM.8b MIMTM.8b : Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). : 10000µm MIMTM.9 MIMTM.9 : Min. Via (Vian-1) spacing for sea of Via on MIM top plate. : 0.5µm MIMTM.10 MIMTM.10 : (a) There cannot be any Vian-2 touching MIM bottom plate Metaln-1. (b) MIM bottom plate Metaln-1 can only be connected through the higher Via (Vian-1). MIMTM.11 MIMTM.11 : Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIMTM.8b rule. : -µm NAT.1 NAT.1 : Min. NAT Overlap of COMP of Native Vt NMOS. : 2µm NAT.2 NAT.2 : Space to unrelated COMP (outside NAT). : 0.3µm NAT.3 NAT.3 : Space to NWell edge. : 0.5µm NAT.4 NAT.4 : Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm NAT.5 NAT.5 : Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm NAT.6 NAT.6 : Two or more COMPs if connected to different potential are not allowed under same NAT layer. NAT.7 NAT.7 : Minimum NAT to NAT spacing. : 0.74µm NAT.8 NAT.8 : Min. Dualgate overlap of NAT (for 5V/6V) native VT NMOS only: 0um NAT.9 NAT.9 : Poly interconnect under NAT layer is not allowed, minimum spacing of un-related poly from the NAT layer: 0.3um NAT.10 NAT.10 : Nwell inside NAT layer are not allowed. NAT.11 NAT.11 : NCOMP not intersecting to Poly2, is not allowed inside NAT layer. NAT.12 NAT.12 : Poly2 not intersecting with COMP is not allowed inside NAT (Poly2 resistor is not allowed inside NAT). NP.1 NP.1 : min. nplus width : 0.4µm NP.2 NP.2 : min. nplus spacing : 0.4µm NP.3a NP.3a : Space to PCOMP for PCOMP: (1) Inside Nwell (2) Outside LVPWELL but inside DNWELL. : 0.16µm NP.3bi NP.3bi : Space to PCOMP: For Inside DNWELL, inside LVPWELL: (i) For PCOMP overlap by LVPWELL < 0.43um. : 0.16µm NP.3bii NP.3bii : Space to PCOMP: For Inside DNWELL, inside LVPWELL: (ii) For PCOMP overlap by LVPWELL >= 0.43um. : 0.08µm NP.3ci NP.3ci : Space to PCOMP: For Outside DNWELL: (i) For PCOMP space to Nwell < 0.43um. : 0.16µm NP.3cii NP.3cii : Space to PCOMP: For Outside DNWELL: (ii) For PCOMP space to Nwell >= 0.43um. : 0.08µm NP.3d NP.3d : Min/max space to a butted PCOMP: 0um NP.3e NP.3e : Space to related PCOMP edge adjacent to a butting edge: 0um NP.4a NP.4a : Space to related P-channel gate at a butting edge parallel to gate. : 0.32µm NP.4b NP.4b : Within 0.32um of channel, space to P-channel gate extension perpendicular to the direction of Poly2. NP.5a NP.5a : Overlap of N-channel gate. : 0.23µm NP.5b NP.5b : Extension beyond COMP for the COMP (1) inside LVPWELL (2) outside Nwell and DNWELL. : 0.16µm NP.5ci NP.5ci : Extension beyond COMP: For Inside DNWELL: (i)For Nplus < 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. : 0.16µm NP.5cii NP.5cii : Extension beyond COMP: For Inside DNWELL: (ii) For Nplus >= 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. : 0.02µm NP.5di NP.5di : Extension beyond COMP: For Outside DNWELL, inside Nwell: (i) For Nwell overlap of Nplus < 0.43um. : 0.16µm NP.5dii NP.5dii : Extension beyond COMP: For Outside DNWELL, inside Nwell: (ii) For Nwell overlap of Nplus >= 0.43um. : 0.02µm NP.6 NP.6 : Overlap with NCOMP butted to PCOMP. : 0.22µm NP.7 NP.7 : Space to unrelated unsalicided Poly2. : 0.18µm NP.8a NP.8a : Minimum Nplus area (um2). : 0.35µm² NP.8b NP.8b : Minimum area enclosed by Nplus (um2). : 0.35µm² NP.9 NP.9 : Overlap of unsalicided Poly2. : 0.18µm NP.10 NP.10 : Overlap of unsalicided COMP. : 0.18µm NP.11 NP.11 : Butting Nplus and PCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case). NP.12 NP.12 : Overlap with P-channel poly2 gate extension is forbidden within 0.32um of P-channel gate. NW.1a_LV NW.1a_LV : Min. Nwell Width (This is only for litho purpose on the generated area): 0.86µm NW.1a_MV NW.1a_MV : Min. Nwell Width (This is only for litho purpose on the generated area): 0.86µm NW.1b_LV NW.1b_LV : Min. Nwell Width as a resistor (Outside DNWELL only): 2µm NW.1b_MV NW.1b_MV : Min. Nwell Width as a resistor (Outside DNWELL only): 2µm NW.2a_LV NW.2a_LV : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.6µm NW.2a_MV NW.2a_MV : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.74µm NW.2b_LV NW.2b_LV : Min. Nwell Space (Outside DNWELL) [Different potential]: 1.4µm. NW.2b_MV NW.2b_MV : Min. Nwell Space (Outside DNWELL) [Different potential]: 1.7µm NW.3 NW.3 : Min. Nwell to DNWELL space: 3.1µm NW.4 NW.4 : Min. Nwell to LVPWELL space: 0um NW.5_LV NW.5_LV : Min. DNWELL enclose Nwell: 0.5µm NW.5_MV NW.5_MV : Min. DNWELL enclose Nwell: 0.5µm NW.6 NW.6 : Nwell resistors can only exist outside DNWELL. O.DF.3a O.DF.3a : Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. : 0.24µm O.DF.6 O.DF.6 : Min. COMP extend beyond poly2 (it also means source/drain overhang). : 0.22µm O.DF.9 O.DF.9 : Min. COMP area (um2). : 0.1444µm² O.PL.2 O.PL.2 : Min. poly2 width. : 0.22µm O.PL.3a O.PL.3a : Min. poly2 Space on COMP. : 0.18µm O.PL.4 O.PL.4 : Min. extension beyond COMP to form Poly2 end cap. : 0.14µm O.SB.2 O.SB.2 : Min. salicide Block Space. : 0.28µm O.SB.3 O.SB.3 : Min. space from salicide block to unrelated COMP. : 0.09µm O.SB.4 O.SB.4 : Min. space from salicide block to contact. O.SB.5b_LV O.SB.5b_LV : Min. space from salicide block to unrelated Poly2 on COMP. : 0.1µm O.SB.9 O.SB.9 : Min. salicide block extension beyond unsalicided Poly2. : 0.1µm O.SB.11 O.SB.11 : Min. salicide block overlap with COMP. : 0.04µm O.SB.13_LV O.SB.13_LV : Min. area of silicide block (um2). : 1.488µm² O.SB.13_MV O.SB.13_MV : Min. area of silicide block (um2). : 2µm² O.CO.7 O.CO.7 : Min. space from COMP contact to Poly2 on COMP. : 0.13µm O.PL.ORT O.PL.ORT : Orientation-restricted gates must have the gate width aligned along the X-axis (poly line running horizontally) in reference to wafer notch down. PL.1_LV PL.1_LV : Interconnect Width (outside PLFUSE). : 0.18µm PL.1_MV PL.1_MV : Interconnect Width (outside PLFUSE). : 0.2µm PL.1a_LV PL.1a_LV : Interconnect Width (inside PLFUSE). : 0.18µm PL.1a_MV PL.1a_MV : Interconnect Width (inside PLFUSE). : 0.18µm PL.2_LV PL.2_LV : Gate Width (Channel Length). : 0.28µm PL.2_MV PL.2_MV : Gate Width (Channel Length). PL.3a PL.3a : Space on COMP/Field: 0.24µm PL.4_LV PL.4_LV : Extension beyond COMP to form Poly2 end cap. : 0.22µm PL.4_MV PL.4_MV : Extension beyond COMP to form Poly2 end cap. : 0.22µm PL.5a_LV PL.5a_LV : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.1µm PL.5a_MV PL.5a_MV : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.3µm PL.5b_LV PL.5b_LV : Space from field Poly2 to related COMP. : 0.1µm PL.5b_MV PL.5b_MV : Space from field Poly2 to related COMP. : 0.3µm PL.6 PL.6 : 90 degree bends on the COMP are not allowed. PL.7_LV PL.7_LV : 45 degree bent gate width : 0.3µm PL.7_MV PL.7_MV : 45 degree bent gate width: 0.7µm PL.9 PL.9 : Poly2 inter connect connecting 3.3V and 5V areas (area inside and outside Dualgate) are not allowed. They shall be done though metal lines only. PL.11 PL.11 : V5_Xtor must enclose 5V device. PL.12 PL.12 : V5_Xtor enclose 5V Comp. PP.1 PP.1 : min. pplus width : 0.4µm PP.2 PP.2 : min. pplus spacing : 0.4µm PP.3a PP.3a : Space to NCOMP for NCOMP (1) inside LVPWELL (2) outside NWELL and DNWELL: 0.16µm PP.3bi PP.3bi : Space to NCOMP: For Inside DNWELL. (i) NCOMP space to LVPWELL >= 0.43um: 0.08µm PP.3bii PP.3bii : Space to NCOMP: For Inside DNWELL. (ii) NCOMP space to LVPWELL < 0.43um. : 0.16µm PP.3ci PP.3ci : Space to NCOMP: For Outside DNWELL, inside Nwell: (i) NWELL Overlap of NCOMP >= 0.43um: 0.08µm PP.3cii PP.3cii : Space to NCOMP: For Outside DNWELL, inside Nwell: (ii) NWELL Overlap of NCOMP 0.43um. : 0.16µm PP.3d PP.3d : Min/max space to a butted NCOMP: 0um PP.3e PP.3e : Space to NCOMP edge adjacent to a butting edge: 0um PP.4a PP.4a : Space related to N-channel gate at a butting edge parallel to gate. : 0.32µm PP.4b PP.4b : Within 0.32um of channel, space to N-channel gate extension perpendicular to the direction of Poly2. PP.5a PP.5a : Overlap of P-channel gate. : 0.23µm PP.5b PP.5b : Extension beyond COMP for COMP (1) Inside NWELL (2) outside LVPWELL but inside DNWELL. : 0.16µm PP.5ci PP.5ci : Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (i) For LVPWELL overlap of Pplus >= 0.43um for LVPWELL tap. : 0.02µm PP.5cii PP.5cii : Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (ii) For LVPWELL overlap of Pplus < 0.43um for the LVPWELL tap. : 0.16µm PP.5di PP.5di : Extension beyond COMP: For Outside DNWELL (i) For Pplus to NWELL space >= 0.43um for Pfield or LVPWELL tap. : 0.02µm PP.5dii PP.5dii : Extension beyond COMP: For Outside DNWELL (ii) For Pplus to NWELL space < 0.43um for Pfield or LVPWELL tap. : 0.16µm PP.6 PP.6 : Overlap with PCOMP butted to NCOMP. : 0.22µm PP.7 PP.7 : Space to unrelated unsalicided Poly2. : 0.18µm PP.8a PP.8a : Minimum Pplus area (um2). : 0.35µm² PP.8b PP.8b : Minimum area enclosed by Pplus (um2). : 0.35µm² PP.9 PP.9 : Overlap of unsalicided Poly2. : 0.18µm PP.10 PP.10 : Overlap of unsalicided COMP. : 0.18µm PP.11 PP.11 : Butting Pplus and NCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case). PP.12 PP.12 : Overlap with N-channel Poly2 gate extension is forbidden within 0.32um of N-channel gate. PRES.1 PRES.1 : Minimum width of Poly2 resistor: 0.8µm PRES.2 PRES.2 : Minimum space between Poly2 resistors: 0.4µm PRES.3 PRES.3 : Minimum space from Poly2 resistor to COMP: 0.6.um PRES.4 PRES.4 : Minimum space from Poly2 resistor to unrelated Poly2: 0.6µm PRES.5 PRES.5 : Minimum Plus implant overlap of Poly2 resistor: 0.3µm PRES.6 PRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction: 0.28µm PRES.7 PRES.7 : Minimum space from salicide block to contact on Poly2 resistor: 0.22.um PRES.9a PRES.9a : Pplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. PRES.9b PRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer: 20µm SB.1 SB.1 : min. sab width : 0.42µm SB.2 SB.2 : min. sab spacing : 0.42µm SB.3 SB.3 : Space from salicide block to unrelated COMP. : 0.22µm SB.4 SB.4 : Space from salicide block to contact: 0.15 um SB.5a SB.5a : Space from salicide block to unrelated Poly2 on field. : 0.3µm SB.5b SB.5b : Space from salicide block to unrelated Poly2 on COMP. : 0.28µm SB.6 SB.6 : Salicide block extension beyond related COMP. : 0.22µm SB.7 SB.7 : COMP extension beyond related salicide block. : 0.22µm SB.8 SB.8 : Non-salicided contacts are forbidden. SB.9 SB.9 : Salicide block extension beyond unsalicided Poly2. : 0.22µm SB.10 SB.10 : Poly2 extension beyond related salicide block. : 0.22µm SB.11 SB.11 : Overlap with COMP. : 0.22µm SB.12 SB.12 : Overlap with Poly2 outside ESD_MK : 0.22µm SB.13 SB.13 : Min. area (um2) : 2µm² SB.14a SB.14a : Space from unsalicided Nplus Poly2 to unsalicided Pplus Poly2. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at unsalicided Pplus Poly2 corners). : 0.56µm SB.14b SB.14b : Space from unsalicided Nplus Poly2 to P-channel gate. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at P-channel gate corners). : 0.56µm SB.15a SB.15a : Space from unsalicided Poly2 to unrelated Nplus/Pplus. : 0.18µm SB.15b SB.15b : Space from unsalicided Poly2 to unrelated Nplus/Pplus. : 0.32µm SB.16 SB.16 : SAB layer cannot exist on 3.3V and 5V/6V CMOS transistors' Poly and COMP area of the core circuit (Excluding the transistors used for ESD purpose). It can only exist on CMOS transistors marked by LVS_IO, OTP_MK, ESD_MK layers. S.DF.4c_LV S.DF.4c_LV : Min. (Nwell overlap of PCOMP) outside DNWELL: 0.4µm S.DF.16_LV S.DF.16_LV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL): 0.4µm S.CO.3_LV S.CO.3_LV : Poly2 overlap of contact: 0.04µm S.CO.4_LV S.CO.4_LV : COMP overlap of contact: 0.03µm S.CO.6_ii_LV S.CO.6_ii_LV : (ii) If Metal1 overlaps contact by < 0.04um on one side, adjacent metal1 edges overlap: 0.02.um S.M1.1_LV S.M1.1_LV : min. metal1 width : 0.22µm S.DF.4c_MV S.DF.4c_MV : Min. (Nwell overlap of PCOMP) outside DNWELL: 0.45µm S.DF.6_MV S.DF.6_MV : Min. COMP extend beyond gate (it also means source/drain overhang): 0.32µm S.DF.7_MV S.DF.7_MV : Min. (LVPWELL Spacer to PCOMP) inside DNWELL: 0.45µm S.DF.8_MV S.DF.8_MV : Min. (LVPWELL overlap of NCOMP) Inside DNWELL: 0.45µm S.DF.16_MV S.DF.16_MV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL): 0.45µm S.PL.5a_MV S.PL.5a_MV : Space from field Poly2 to unrelated COMP/Spacer from field Poly2 to Guard-ring: 0.12µm S.PL.5b_MV S.PL.5b_MV : Space from field Poly2 to related COMP: 0.12µm S.CO.4_MV S.CO.4_MV : COMP overlap of contact: 0.04µm V1.1 V1.1 : Min/max Via1 size . : 0.26µm V1.2a V1.2a : min. via1 spacing : 0.26µm V1.2b V1.2b : Via1 Space in 4x4 or larger via1 array : 0.36µm V1.3a V1.3a : metal1 overlap of via1 >= 0.0 V1.3c V1.3c : metal1 (< 0.34um) end-of-line overlap. (Applies to all < 0.34µm wide Metal lines, excluding Metal branches shorter than 0.28µm.) : 0.06µm V1.3d V1.3d : If metal1 overlap via1 by < 0.04um on one side, adjacent metal1 edges overlap. : 0.06µm V1.4a V1.4a : metal2 overlap of via1 >= 0.01 um V1.4b V1.4p : metal2 (< 0.34um) end-of-line overlap. (Applies to all < 0.34µm wide Metal lines, excluding Metal branches shorter than 0.28µm.) : 0.06µm V1.4c V1.4c : If metal2 overlap via1 by < 0.04um on one side, adjacent metal2 edges overlap. : 0.06µm V2.1 V2.1 : Min/max Via2 size . : 0.26µm V2.2a V2.2a : min. via2 spacing : 0.26µm V2.2b V2.2b : via2 Space in 4x4 or larger via2 array : 0.36µm V2.3b V2.3b : metal2 overlap of via2 >= 0.01 V2.3c V2.3c : metal2 (< 0.34um) end-of-line overlap.(Applies to all < 0.34µm wide Metal lines, excluding Metal branches shorter than 0.28µm.) : 0.06µm V2.3d V2.3d : If metal2 overlap via2 by < 0.04um on one side, adjacent metal2 edges overlap. : 0.06µm V2.4a V2.4a : metal3 overlap of via2 >= 0.01 um V2.4b V2.4p : metal3 (< 0.34um) end-of-line overlap. : 0.06µm V2.4c V2.4c : If metal3 overlap via2 by < 0.04um on one side, adjacent metal3 edges overlap. : 0.06µm V3.1 V3.1 : Min/max Via3 size . : 0.26µm V3.2a V3.2a : min. via3 spacing : 0.26µm V3.2b V3.2b : via3 Space in 4x4 or larger via3 array : 0.36µm V3.3b V3.3b : metal3 overlap of via3 >= 0.01 V3.3c V3.3c : metal3 (< 0.34um) end-of-line overlap. (Applies to all < 0.34µm wide Metal lines, excluding Metal branches shorter than 0.28µm.) : 0.06µm V3.3d V3.3d : If metal3 overlap via3 by < 0.04um on one side, adjacent metal3 edges overlap. : 0.06µm V3.4a V3.4a : metal4 overlap of via3 >= 0.01 um V3.4b V3.4p : metal4 (< 0.34um) end-of-line overlap. (Applies to all < 0.34µm wide Metal lines, excluding Metal branches shorter than 0.28µm.) : 0.06µm V3.4c V3.4c : If metal4 overlap via3 by < 0.04um on one side, adjacent metal4 edges overlap. : 0.06µm V4.1 V4.1 : Min/max Via4 size . : 0.26µm V4.2a V4.2a : min. via4 spacing : 0.26µm V4.2b V4.2b : via4 Space in 4x4 or larger via4 array : 0.36µm V4.3b V4.3b : metal4 overlap of via4 >= 0.01 V4.3c V4.3c : metal4 (< 0.34um) end-of-line overlap. (Applies to all < 0.34µm wide Metal lines, excluding Metal branches shorter than 0.28µm.) : 0.06µm V4.3d V4.3d : If metal4 overlap via4 by < 0.04um on one side, adjacent metal4 edges overlap. : 0.06µm V4.4a V4.4a : metal5 overlap of via4 >= 0.01 um V4.4b V4.4p : metal5 (< 0.34um) end-of-line overlap. (Applies to all < 0.34µm wide Metal lines, excluding Metal branches shorter than 0.28µm.) : 0.06µm V4.4c V4.4c : If metal5 overlap via4 by < 0.04um on one side, adjacent metal5 edges overlap. : 0.06µm Y.NW.2b_LV Y.NW.2b_LV : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm Y.NW.2b_MV Y.NW.2b_MV : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm Y.DF.6_MV Y.DF.6_MV : Min. COMP extend beyond gate (it also means source/drain overhang) inside YMTP_MK. : 0.15µm Y.DF.16_LV Y.DF.16_LV : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.27µm Y.DF.16_MV Y.DF.16_MV : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.23µm Y.PL.1_LV Y.PL.1_LV : Interconnect Width (inside YMTP_MK). : 0.13µm Y.PL.1_MV Y.PL.1_MV : Interconnect Width (inside YMTP_MK). This rule is currently not applicable for 5V. Y.PL.2_LV Y.PL.2_LV : Gate Width (Channel Length) (inside YMTP_MK): 0.13µm Y.PL.2_MV Y.PL.2_MV : Gate Width (Channel Length) (inside YMTP_MK): 0.47µm Y.PL.4_MV Y.PL.4_MV : Poly2 extension beyond COMP to form Poly2 end cap (inside YMTP_MK): 0.16µm Y.PL.5a_LV Y.PL.5a_LV : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.04µm Y.PL.5a_MV Y.PL.5a_MV : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.2µm Y.PL.5b_LV Y.PL.5b_LV : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.04µm Y.PL.5b_MV Y.PL.5b_MV : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.2µm DE.2 DE.2 : Minimum NDMY or PMNDMY size (x or y dimension in um) : 0.8µm DE.3 DE.3 : Maximum NDMY size (um2): 15000 um2. If size greater than 15000 um2 then two sides should not be greater than (80 um). DE.4 DE.4 : Minimum NDMY to NDMY space (Merge if space is less) : 20µm DCF.2b DCF.2b : Resulted minimum space between Dummy active in all directions: 1.9 DCF.4 DCF.4 : Space from dummy COMP to COMP (circuit COMP): 3.5 DCF.5 DCF.5 : Space from dummy COMP to poly2: 1.5 DCF.6a DCF.6a : Space from dummy COMP to Nwell boundary: 1.3 DCF.6b DCF.6b : Space from dummy COMP to DNWELL boundary: 4 DCF.6c DCF.6c : Space from dummy COMP to LVPWELL boundary: 1.3 DCF.6d DCF.6d : Space from dummy COMP to Dualgate boundary: 1.3 DCF.8a DCF.8a : Space from dummy COMP to Resistor marking layer (RES_MK): 3.5 DCF.11a DCF.11a : Space from dummy COMP to dummy COMP excluding layer (NDMY): 3.5 DCF.12 DCF.12 : Minimum dummy COMP space to IND_MK layer: 3 DPF.1 DPF.1 : Dummy Poly2 is generated on top of dummy COMP. DPF.2b DPF.2b : Resulted minimum space between Dummy poly in all directions: 1.1 DPF.4 DPF.4 : Space of dummy poly2 to COMP: 3.2 DPF.5 DPF.5 : Space of dummy poly2 to poly2: 5 DPF.6a DPF.6a : Space from dummy poly2 to Nwell boundary: 1 DPF.6b DPF.6b : Space from dummy poly2 to DNWELL boundary: 2 DPF.6c DPF.6c : Space from dummy poly2 to LVPWELL boundary: 1 DPF.6d DPF.6d : Space from dummy poly2 to Dualgate boundary: 1 DPF.8 DPF.8 : Space from dummy poly2 to Resistor marking layer (RES_MK): 19.7 DPF.9 DPF.9 : Space of dummy poly2 to Pad: 6.7 DPF.11 DPF.11 : Space to dummy COMP exclude layer (NDMY): 29.7 DPF.14 DPF.14 : Minimum dummy poly2 space to IND_MK layer: 3 DPF.16 DPF.16 : Minimum dummy poly2 space to MTPMARK layer: 3 DPF.19 DPF.19 : Space from dummy poly2 to dummy poly2 excluding layer (PMNDMY): 8 DM1.2b DM1.2b : Min Dummy metal line space (for DRC): 0.98 DM1.3 DM1.3 : Minimum space between dummy metal and circuit Metal line: 2 DM1.8 DM1.8 : Minimum space between dummy metal and FuseTop, POLYFUSE, FUSEWINDOW_D, PMNDMY, MTPMK, OTP_MK: 6 DM2.2b DM2.2b : Min Dummy metal line space (for DRC): 0.98 DM2.3 DM2.3 : Minimum space between dummy metal and circuit Metal line: 2 DM2.8 DM2.8 : Minimum space between dummy metal and FuseTop, POLYFUSE, FUSEWINDOW_D, PMNDMY, MTPMK, OTP_MK: 6 DM3.2b DM3.2b : Min Dummy metal line space (for DRC): 0.98 DM3.3 DM3.3 : Minimum space between dummy metal and circuit Metal line: 2 DM3.8 DM3.8 : Minimum space between dummy metal and FuseTop, POLYFUSE, FUSEWINDOW_D, PMNDMY, MTPMK, OTP_MK: 6 DM4.2b DM4.2b : Min Dummy metal line space (for DRC): 0.98 DM4.3 DM4.3 : Minimum space between dummy metal and circuit Metal line: 2 DM4.8 DM4.8 : Minimum space between dummy metal and FuseTop, POLYFUSE, FUSEWINDOW_D, PMNDMY, MTPMK, OTP_MK: 6 DM5.2b DM5.2b : Min Dummy metal line space (for DRC): 0.98 DM5.8 DM5.8 : Minimum space between dummy metal and FuseTop, POLYFUSE, FUSEWINDOW_D, PMNDMY, MTPMK, OTP_MK: 6 CUP.2 CUP.2 : Minimum width of the metal (#{metal_name}) line used for bond pads: 1 CUP.3 CUP.3 : Minimum space of the metal (#{metal_name}) line used for bond pads (slots): 1 chip_top chiptop_A_track chiptop_A_track chip_top r0 *1 501.89,1038.68 padring padring chip_top r0 *1 501.89,1038.68 gf180mcu_fd_io__bi_t$2 r90 gf180mcu_fd_io__bi_t$2$VAR3 chip_top r90 *1 3436.89,2818.68 gf180mcu_fd_io__bi_t$2 r180 gf180mcu_fd_io__bi_t$2$VAR1 chip_top r180 *1 2756.89,3973.68 gf180mcu_fd_io__bi_t$2 r0 gf180mcu_fd_io__bi_t$2$VAR2 chip_top r0 *1 981.89,1038.68 gf180mcu_fd_io__bi_t$2 r270 gf180mcu_fd_io__bi_t$2 chip_top r270 *1 501.89,1493.68 gf180mcu_fd_io__dvdd$2 r90 gf180mcu_fd_io__dvdd$2$VAR3 chip_top r90 *1 3436.89,2518.68 5LM_METAL_RAIL_PAD_60$2 r90 5LM_METAL_RAIL_PAD_60$2$VAR3 chip_top r90 *1 3436.89,2518.68 Bondpad_5LM$2 r90 Bondpad_5LM$2$VAR3 chip_top r90 *1 3436.89,2524.18 gf180mcu_fd_io__dvdd$2 r180 gf180mcu_fd_io__dvdd$2$VAR1 chip_top r180 *1 2056.89,3973.68 5LM_METAL_RAIL_PAD_60$2 r180 5LM_METAL_RAIL_PAD_60$2$VAR1 chip_top r180 *1 2056.89,3973.68 Bondpad_5LM$2 r180 Bondpad_5LM$2$VAR1 chip_top r180 *1 2051.39,3973.68 gf180mcu_fd_io__asig_5p0$2 r90 gf180mcu_fd_io__asig_5p0$2$VAR3 chip_top r90 *1 3436.89,3118.68 gf180mcu_fd_io__asig_5p0$2 r180 gf180mcu_fd_io__asig_5p0$2$VAR1 chip_top r180 *1 2356.89,3973.68 gf180mcu_fd_io__dvss$2 r90 gf180mcu_fd_io__dvss$2$VAR3 chip_top r90 *1 3436.89,2718.68 gf180mcu_fd_io__dvss$2 r180 gf180mcu_fd_io__dvss$2$VAR1 chip_top r180 *1 2956.89,3973.68 gf180mcu_fd_io__asig_5p0$2 r270 gf180mcu_fd_io__asig_5p0$2 chip_top r270 *1 501.89,2593.68 5LM_METAL_RAIL_PAD_60$2 r270 5LM_METAL_RAIL_PAD_60$2 chip_top r270 *1 501.89,2593.68 Bondpad_5LM$2 r270 Bondpad_5LM$2 chip_top r270 *1 501.89,2588.18 gf180mcu_fd_io__dvdd$2 r270 gf180mcu_fd_io__dvdd$2 chip_top r270 *1 501.89,3593.68 gf180mcu_fd_io__dvss$2 r270 gf180mcu_fd_io__dvss$2 chip_top r270 *1 501.89,3493.68 gf180mcu_fd_io__asig_5p0$2 r0 gf180mcu_fd_io__asig_5p0$2$VAR2 chip_top r0 *1 1881.89,1038.68 5LM_METAL_RAIL_PAD_60$2 r0 5LM_METAL_RAIL_PAD_60$2$VAR2 chip_top r0 *1 1881.89,1038.68 Bondpad_5LM$2 r0 Bondpad_5LM$2$VAR2 chip_top r0 *1 1887.39,1038.68 gf180mcu_fd_io__dvdd$2 r0 gf180mcu_fd_io__dvdd$2$VAR2 chip_top r0 *1 1181.89,1038.68 gf180mcu_fd_io__dvss$2 r0 gf180mcu_fd_io__dvss$2$VAR2 chip_top r0 *1 881.89,1038.68 'CUP.3' chiptop_A_track false 1 edge-pair: (2542.46,2873;2542.46,2933)|(2542.16,2933;2542.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2538.46,2873;2538.46,2933)|(2538.16,2933;2538.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2536.46,2873;2536.46,2933)|(2536.16,2933;2536.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2528.46,2873;2528.46,2933)|(2528.16,2933;2528.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2524.46,2873;2524.46,2933)|(2524.16,2933;2524.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2520.46,2873;2520.46,2933)|(2520.16,2933;2520.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2514.46,2873;2514.46,2933)|(2514.16,2933;2514.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2512.46,2873;2512.46,2933)|(2512.16,2933;2512.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2510.46,2873;2510.46,2933)|(2510.16,2933;2510.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2508.46,2873;2508.46,2933)|(2508.16,2933;2508.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2506.46,2873;2506.46,2933)|(2506.16,2933;2506.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2504.46,2873;2504.46,2933)|(2504.16,2933;2504.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2492.46,2873;2492.46,2933)|(2492.16,2933;2492.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2488.46,2873;2488.46,2933)|(2487.5,2933;2487.5,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2440.46,2873;2440.46,2933)|(2440.16,2933;2440.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2438.46,2873;2438.46,2933)|(2438.16,2933;2438.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2420.46,2873;2420.46,2933)|(2420.16,2933;2420.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2416.46,2873;2416.46,2933)|(2416.16,2933;2416.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2412.46,2873;2412.46,2933)|(2412.16,2933;2412.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2410.46,2873;2410.46,2933)|(2410.16,2933;2410.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2398.46,2873;2398.46,2933)|(2398.16,2933;2398.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2396.46,2873;2396.46,2933)|(2396.16,2933;2396.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2394.46,2873;2394.46,2933)|(2394.16,2933;2394.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2402.46,2873;2402.46,2933)|(2402.16,2933;2402.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2388.46,2873;2388.46,2933)|(2387.5,2933;2387.5,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2432.46,2873;2432.46,2933)|(2432.16,2933;2432.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2442.46,2873;2442.46,2933)|(2442.16,2933;2442.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2414.46,2873;2414.46,2933)|(2414.16,2933;2414.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2408.46,2873;2408.46,2933)|(2408.16,2933;2408.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2516.46,2873;2516.46,2933)|(2516.16,2933;2516.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2490.46,2873;2490.46,2933)|(2490.16,2933;2490.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2500.46,2873;2500.46,2933)|(2500.16,2933;2500.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2522.46,2873;2522.46,2933)|(2522.16,2933;2522.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2518.46,2873;2518.46,2933)|(2518.16,2933;2518.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2430.46,2873;2430.46,2933)|(2430.16,2933;2430.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2406.46,2873;2406.46,2933)|(2406.16,2933;2406.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2502.46,2873;2502.46,2933)|(2502.16,2933;2502.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2444.46,2873;2444.46,2933)|(2444.16,2933;2444.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2392.46,2873;2392.46,2933)|(2392.16,2933;2392.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2426.46,2873;2426.46,2933)|(2426.16,2933;2426.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2496.46,2873;2496.46,2933)|(2496.16,2933;2496.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2498.46,2873;2498.46,2933)|(2498.16,2933;2498.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2434.46,2873;2434.46,2933)|(2434.16,2933;2434.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2422.46,2873;2422.46,2933)|(2422.16,2933;2422.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2424.46,2873;2424.46,2933)|(2424.16,2933;2424.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2418.46,2873;2418.46,2933)|(2418.16,2933;2418.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2390.46,2873;2390.46,2933)|(2390.16,2933;2390.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2526.46,2873;2526.46,2933)|(2526.16,2933;2526.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2530.46,2873;2530.46,2933)|(2530.16,2933;2530.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2494.46,2873;2494.46,2933)|(2494.16,2933;2494.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2428.46,2873;2428.46,2933)|(2428.16,2933;2428.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2436.46,2873;2436.46,2933)|(2436.16,2933;2436.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2534.46,2873;2534.46,2933)|(2534.16,2933;2534.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2400.46,2873;2400.46,2933)|(2400.16,2933;2400.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2404.46,2873;2404.46,2933)|(2404.16,2933;2404.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2544.46,2873;2544.46,2933)|(2544.16,2933;2544.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2540.46,2873;2540.46,2933)|(2540.16,2933;2540.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2532.46,2873;2532.46,2933)|(2532.16,2933;2532.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2540.54;2933,2540.54)|(2933,2540.84;2873,2540.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2434.54;2933,2434.54)|(2933,2434.84;2873,2434.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2426.54;2933,2426.54)|(2933,2426.84;2873,2426.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2392.54;2933,2392.54)|(2933,2392.84;2873,2392.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2538.54;2933,2538.54)|(2933,2538.84;2873,2538.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2420.54;2933,2420.54)|(2933,2420.84;2873,2420.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2514.54;2933,2514.54)|(2933,2514.84;2873,2514.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2530.54;2933,2530.54)|(2933,2530.84;2873,2530.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2496.54;2933,2496.54)|(2933,2496.84;2873,2496.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2526.54;2933,2526.54)|(2933,2526.84;2873,2526.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2506.54;2933,2506.54)|(2933,2506.84;2873,2506.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2490.54;2933,2490.54)|(2933,2490.84;2873,2490.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2542.54;2933,2542.54)|(2933,2542.84;2873,2542.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2520.54;2933,2520.54)|(2933,2520.84;2873,2520.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2544.54;2933,2544.54)|(2933,2544.84;2873,2544.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2512.54;2933,2512.54)|(2933,2512.84;2873,2512.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2528.54;2933,2528.54)|(2933,2528.84;2873,2528.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2536.54;2933,2536.54)|(2933,2536.84;2873,2536.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2518.54;2933,2518.54)|(2933,2518.84;2873,2518.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2516.54;2933,2516.54)|(2933,2516.84;2873,2516.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2510.54;2933,2510.54)|(2933,2510.84;2873,2510.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2446.54;2933,2446.54)|(2933,2447.5;2873,2447.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2444.54;2933,2444.54)|(2933,2444.84;2873,2444.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2422.54;2933,2422.54)|(2933,2422.84;2873,2422.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2398.54;2933,2398.54)|(2933,2398.84;2873,2398.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2428.54;2933,2428.54)|(2933,2428.84;2873,2428.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2546.54;2933,2546.54)|(2933,2547.5;2873,2547.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2532.54;2933,2532.54)|(2933,2532.84;2873,2532.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2500.54;2933,2500.54)|(2933,2500.84;2873,2500.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2498.54;2933,2498.54)|(2933,2498.84;2873,2498.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2508.54;2933,2508.54)|(2933,2508.84;2873,2508.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2492.54;2933,2492.54)|(2933,2492.84;2873,2492.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2502.54;2933,2502.54)|(2933,2502.84;2873,2502.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2438.54;2933,2438.54)|(2933,2438.84;2873,2438.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2432.54;2933,2432.54)|(2933,2432.84;2873,2432.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2424.54;2933,2424.54)|(2933,2424.84;2873,2424.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2418.54;2933,2418.54)|(2933,2418.84;2873,2418.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2534.54;2933,2534.54)|(2933,2534.84;2873,2534.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2416.54;2933,2416.54)|(2933,2416.84;2873,2416.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2414.54;2933,2414.54)|(2933,2414.84;2873,2414.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2410.54;2933,2410.54)|(2933,2410.84;2873,2410.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2408.54;2933,2408.54)|(2933,2408.84;2873,2408.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2524.54;2933,2524.54)|(2933,2524.84;2873,2524.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2406.54;2933,2406.54)|(2933,2406.84;2873,2406.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2430.54;2933,2430.54)|(2933,2430.84;2873,2430.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2404.54;2933,2404.54)|(2933,2404.84;2873,2404.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2402.54;2933,2402.54)|(2933,2402.84;2873,2402.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2522.54;2933,2522.54)|(2933,2522.84;2873,2522.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2400.54;2933,2400.54)|(2933,2400.84;2873,2400.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2396.54;2933,2396.54)|(2933,2396.84;2873,2396.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2394.54;2933,2394.54)|(2933,2394.84;2873,2394.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2494.54;2933,2494.54)|(2933,2494.84;2873,2494.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2442.54;2933,2442.54)|(2933,2442.84;2873,2442.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2436.54;2933,2436.54)|(2933,2436.84;2873,2436.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2504.54;2933,2504.54)|(2933,2504.84;2873,2504.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2440.54;2933,2440.54)|(2933,2440.84;2873,2440.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2412.54;2933,2412.54)|(2933,2412.84;2873,2412.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2390.54;2933,2390.54)|(2933,2390.84;2873,2390.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2232.54;2933,2232.54)|(2933,2232.84;2873,2232.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2304.54;2933,2304.54)|(2933,2304.84;2873,2304.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2226.54;2933,2226.54)|(2933,2226.84;2873,2226.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2224.54;2933,2224.54)|(2933,2224.84;2873,2224.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2204.54;2933,2204.54)|(2933,2204.84;2873,2204.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2222.54;2933,2222.54)|(2933,2222.84;2873,2222.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2220.54;2933,2220.54)|(2933,2220.84;2873,2220.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2218.54;2933,2218.54)|(2933,2218.84;2873,2218.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2216.54;2933,2216.54)|(2933,2216.84;2873,2216.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2214.54;2933,2214.54)|(2933,2214.84;2873,2214.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2210.54;2933,2210.54)|(2933,2210.84;2873,2210.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2212.54;2933,2212.54)|(2933,2212.84;2873,2212.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2208.54;2933,2208.54)|(2933,2208.84;2873,2208.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2206.54;2933,2206.54)|(2933,2206.84;2873,2206.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2240.54;2933,2240.54)|(2933,2240.84;2873,2240.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2340.54;2933,2340.54)|(2933,2340.84;2873,2340.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2334.54;2933,2334.54)|(2933,2334.84;2873,2334.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2326.54;2933,2326.54)|(2933,2326.84;2873,2326.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2314.54;2933,2314.54)|(2933,2314.84;2873,2314.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2228.54;2933,2228.54)|(2933,2228.84;2873,2228.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2312.54;2933,2312.54)|(2933,2312.84;2873,2312.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2234.54;2933,2234.54)|(2933,2234.84;2873,2234.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2330.54;2933,2330.54)|(2933,2330.84;2873,2330.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2308.54;2933,2308.54)|(2933,2308.84;2873,2308.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2306.54;2933,2306.54)|(2933,2306.84;2873,2306.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2336.54;2933,2336.54)|(2933,2336.84;2873,2336.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2310.54;2933,2310.54)|(2933,2310.84;2873,2310.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2298.54;2933,2298.54)|(2933,2298.84;2873,2298.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2342.54;2933,2342.54)|(2933,2342.84;2873,2342.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2296.54;2933,2296.54)|(2933,2296.84;2873,2296.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2294.54;2933,2294.54)|(2933,2294.84;2873,2294.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2300.54;2933,2300.54)|(2933,2300.84;2873,2300.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2292.54;2933,2292.54)|(2933,2292.84;2873,2292.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2332.54;2933,2332.54)|(2933,2332.84;2873,2332.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2246.54;2933,2246.54)|(2933,2247.5;2873,2247.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2302.54;2933,2302.54)|(2933,2302.84;2873,2302.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2324.54;2933,2324.54)|(2933,2324.84;2873,2324.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2328.54;2933,2328.54)|(2933,2328.84;2873,2328.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2200.54;2933,2200.54)|(2933,2200.84;2873,2200.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2346.54;2933,2346.54)|(2933,2347.5;2873,2347.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2238.54;2933,2238.54)|(2933,2238.84;2873,2238.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2202.54;2933,2202.54)|(2933,2202.84;2873,2202.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2316.54;2933,2316.54)|(2933,2316.84;2873,2316.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2322.54;2933,2322.54)|(2933,2322.84;2873,2322.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2290.54;2933,2290.54)|(2933,2290.84;2873,2290.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2344.54;2933,2344.54)|(2933,2344.84;2873,2344.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2338.54;2933,2338.54)|(2933,2338.84;2873,2338.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2242.54;2933,2242.54)|(2933,2242.84;2873,2242.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2320.54;2933,2320.54)|(2933,2320.84;2873,2320.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2244.54;2933,2244.54)|(2933,2244.84;2873,2244.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2318.54;2933,2318.54)|(2933,2318.84;2873,2318.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2236.54;2933,2236.54)|(2933,2236.84;2873,2236.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2230.54;2933,2230.54)|(2933,2230.84;2873,2230.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2044.46,2873;2044.46,2933)|(2044.16,2933;2044.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1998.46,2873;1998.46,2933)|(1998.16,2933;1998.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2012.46,2873;2012.46,2933)|(2012.16,2933;2012.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2036.46,2873;2036.46,2933)|(2036.16,2933;2036.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2028.46,2873;2028.46,2933)|(2028.16,2933;2028.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2026.46,2873;2026.46,2933)|(2026.16,2933;2026.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1834.46,2873;1834.46,2933)|(1834.16,2933;1834.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1992.46,2873;1992.46,2933)|(1992.16,2933;1992.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2042.46,2873;2042.46,2933)|(2042.16,2933;2042.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2010.46,2873;2010.46,2933)|(2010.16,2933;2010.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1996.46,2873;1996.46,2933)|(1996.16,2933;1996.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1988.46,2873;1988.46,2933)|(1987.5,2933;1987.5,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2040.46,2873;2040.46,2933)|(2040.16,2933;2040.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2014.46,2873;2014.46,2933)|(2014.16,2933;2014.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2030.46,2873;2030.46,2933)|(2030.16,2933;2030.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2024.46,2873;2024.46,2933)|(2024.16,2933;2024.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2038.46,2873;2038.46,2933)|(2038.16,2933;2038.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2018.46,2873;2018.46,2933)|(2018.16,2933;2018.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1842.46,2873;1842.46,2933)|(1842.16,2933;1842.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2016.46,2873;2016.46,2933)|(2016.16,2933;2016.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2034.46,2873;2034.46,2933)|(2034.16,2933;2034.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2032.46,2873;2032.46,2933)|(2032.16,2933;2032.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1994.46,2873;1994.46,2933)|(1994.16,2933;1994.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2008.46,2873;2008.46,2933)|(2008.16,2933;2008.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2006.46,2873;2006.46,2933)|(2006.16,2933;2006.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2004.46,2873;2004.46,2933)|(2004.16,2933;2004.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2002.46,2873;2002.46,2933)|(2002.16,2933;2002.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2022.46,2873;2022.46,2933)|(2022.16,2933;2022.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2000.46,2873;2000.46,2933)|(2000.16,2933;2000.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1838.46,2873;1838.46,2933)|(1838.16,2933;1838.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1990.46,2873;1990.46,2933)|(1990.16,2933;1990.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1844.46,2873;1844.46,2933)|(1844.16,2933;1844.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1840.46,2873;1840.46,2933)|(1840.16,2933;1840.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2020.46,2873;2020.46,2933)|(2020.16,2933;2020.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1836.46,2873;1836.46,2933)|(1836.16,2933;1836.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1626.46,2873;1626.46,2933)|(1626.16,2933;1626.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1612.46,2873;1612.46,2933)|(1612.16,2933;1612.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1624.46,2873;1624.46,2933)|(1624.16,2933;1624.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1614.46,2873;1614.46,2933)|(1614.16,2933;1614.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1620.46,2873;1620.46,2933)|(1620.16,2933;1620.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1534.46,2873;1534.46,2933)|(1534.16,2933;1534.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1808.46,2873;1808.46,2933)|(1808.16,2933;1808.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1598.46,2873;1598.46,2933)|(1598.16,2933;1598.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1596.46,2873;1596.46,2933)|(1596.16,2933;1596.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1538.46,2873;1538.46,2933)|(1538.16,2933;1538.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1592.46,2873;1592.46,2933)|(1592.16,2933;1592.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1640.46,2873;1640.46,2933)|(1640.16,2933;1640.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1590.46,2873;1590.46,2933)|(1590.16,2933;1590.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1532.46,2873;1532.46,2933)|(1532.16,2933;1532.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1828.46,2873;1828.46,2933)|(1828.16,2933;1828.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1816.46,2873;1816.46,2933)|(1816.16,2933;1816.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1630.46,2873;1630.46,2933)|(1630.16,2933;1630.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1822.46,2873;1822.46,2933)|(1822.16,2933;1822.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1528.46,2873;1528.46,2933)|(1528.16,2933;1528.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1802.46,2873;1802.46,2933)|(1802.16,2933;1802.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1600.46,2873;1600.46,2933)|(1600.16,2933;1600.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1492.46,2873;1492.46,2933)|(1492.16,2933;1492.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1522.46,2873;1522.46,2933)|(1522.16,2933;1522.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1520.46,2873;1520.46,2933)|(1520.16,2933;1520.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1516.46,2873;1516.46,2933)|(1516.16,2933;1516.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1510.46,2873;1510.46,2933)|(1510.16,2933;1510.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1800.46,2873;1800.46,2933)|(1800.16,2933;1800.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1508.46,2873;1508.46,2933)|(1508.16,2933;1508.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1794.46,2873;1794.46,2933)|(1794.16,2933;1794.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1506.46,2873;1506.46,2933)|(1506.16,2933;1506.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1504.46,2873;1504.46,2933)|(1504.16,2933;1504.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1790.46,2873;1790.46,2933)|(1790.16,2933;1790.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1502.46,2873;1502.46,2933)|(1502.16,2933;1502.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1796.46,2873;1796.46,2933)|(1796.16,2933;1796.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1498.46,2873;1498.46,2933)|(1498.16,2933;1498.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1496.46,2873;1496.46,2933)|(1496.16,2933;1496.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1494.46,2873;1494.46,2933)|(1494.16,2933;1494.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1544.46,2873;1544.46,2933)|(1544.16,2933;1544.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1530.46,2873;1530.46,2933)|(1530.16,2933;1530.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1788.46,2873;1788.46,2933)|(1787.5,2933;1787.5,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1490.46,2873;1490.46,2933)|(1490.16,2933;1490.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1488.46,2873;1488.46,2933)|(1487.5,2933;1487.5,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1540.46,2873;1540.46,2933)|(1540.16,2933;1540.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1594.46,2873;1594.46,2933)|(1594.16,2933;1594.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1512.46,2873;1512.46,2933)|(1512.16,2933;1512.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1618.46,2873;1618.46,2933)|(1618.16,2933;1618.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1536.46,2873;1536.46,2933)|(1536.16,2933;1536.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1500.46,2873;1500.46,2933)|(1500.16,2933;1500.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1644.46,2873;1644.46,2933)|(1644.16,2933;1644.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1514.46,2873;1514.46,2933)|(1514.16,2933;1514.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1638.46,2873;1638.46,2933)|(1638.16,2933;1638.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1804.46,2873;1804.46,2933)|(1804.16,2933;1804.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1636.46,2873;1636.46,2933)|(1636.16,2933;1636.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1820.46,2873;1820.46,2933)|(1820.16,2933;1820.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1610.46,2873;1610.46,2933)|(1610.16,2933;1610.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1798.46,2873;1798.46,2933)|(1798.16,2933;1798.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1518.46,2873;1518.46,2933)|(1518.16,2933;1518.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1634.46,2873;1634.46,2933)|(1634.16,2933;1634.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1604.46,2873;1604.46,2933)|(1604.16,2933;1604.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1632.46,2873;1632.46,2933)|(1632.16,2933;1632.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1830.46,2873;1830.46,2933)|(1830.16,2933;1830.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1622.46,2873;1622.46,2933)|(1622.16,2933;1622.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1606.46,2873;1606.46,2933)|(1606.16,2933;1606.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1628.46,2873;1628.46,2933)|(1628.16,2933;1628.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1810.46,2873;1810.46,2933)|(1810.16,2933;1810.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1588.46,2873;1588.46,2933)|(1587.5,2933;1587.5,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1792.46,2873;1792.46,2933)|(1792.16,2933;1792.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1542.46,2873;1542.46,2933)|(1542.16,2933;1542.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1642.46,2873;1642.46,2933)|(1642.16,2933;1642.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1832.46,2873;1832.46,2933)|(1832.16,2933;1832.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1826.46,2873;1826.46,2933)|(1826.16,2933;1826.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1824.46,2873;1824.46,2933)|(1824.16,2933;1824.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1524.46,2873;1524.46,2933)|(1524.16,2933;1524.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1818.46,2873;1818.46,2933)|(1818.16,2933;1818.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1616.46,2873;1616.46,2933)|(1616.16,2933;1616.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1608.46,2873;1608.46,2933)|(1608.16,2933;1608.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1814.46,2873;1814.46,2933)|(1814.16,2933;1814.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1602.46,2873;1602.46,2933)|(1602.16,2933;1602.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1812.46,2873;1812.46,2933)|(1812.16,2933;1812.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1526.46,2873;1526.46,2933)|(1526.16,2933;1526.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1806.46,2873;1806.46,2933)|(1806.16,2933;1806.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2104.54;2933,2104.54)|(2933,2104.84;2873,2104.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2194.54;2933,2194.54)|(2933,2194.84;2873,2194.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2132.54;2933,2132.54)|(2933,2132.84;2873,2132.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2098.54;2933,2098.54)|(2933,2098.84;2873,2098.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1928.54;2933,1928.54)|(2933,1928.84;2873,1928.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2094.54;2933,2094.54)|(2933,2094.84;2873,2094.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2092.54;2933,2092.54)|(2933,2092.84;2873,2092.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2046.54;2933,2046.54)|(2933,2047.5;2873,2047.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2044.54;2933,2044.54)|(2933,2044.84;2873,2044.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2040.54;2933,2040.54)|(2933,2040.84;2873,2040.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2038.54;2933,2038.54)|(2933,2038.84;2873,2038.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2034.54;2933,2034.54)|(2933,2034.84;2873,2034.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2030.54;2933,2030.54)|(2933,2030.84;2873,2030.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2028.54;2933,2028.54)|(2933,2028.84;2873,2028.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2022.54;2933,2022.54)|(2933,2022.84;2873,2022.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2192.54;2933,2192.54)|(2933,2192.84;2873,2192.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2020.54;2933,2020.54)|(2933,2020.84;2873,2020.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2010.54;2933,2010.54)|(2933,2010.84;2873,2010.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2002.54;2933,2002.54)|(2933,2002.84;2873,2002.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2018.54;2933,2018.54)|(2933,2018.84;2873,2018.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1998.54;2933,1998.54)|(2933,1998.84;2873,1998.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1996.54;2933,1996.54)|(2933,1996.84;2873,1996.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2198.54;2933,2198.54)|(2933,2198.84;2873,2198.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2102.54;2933,2102.54)|(2933,2102.84;2873,2102.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1994.54;2933,1994.54)|(2933,1994.84;2873,1994.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2012.54;2933,2012.54)|(2933,2012.84;2873,2012.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2142.54;2933,2142.54)|(2933,2142.84;2873,2142.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1992.54;2933,1992.54)|(2933,1992.84;2873,1992.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2026.54;2933,2026.54)|(2933,2026.84;2873,2026.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2006.54;2933,2006.54)|(2933,2006.84;2873,2006.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1944.54;2933,1944.54)|(2933,1944.84;2873,1944.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1942.54;2933,1942.54)|(2933,1942.84;2873,1942.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1940.54;2933,1940.54)|(2933,1940.84;2873,1940.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2042.54;2933,2042.54)|(2933,2042.84;2873,2042.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1938.54;2933,1938.54)|(2933,1938.84;2873,1938.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1936.54;2933,1936.54)|(2933,1936.84;2873,1936.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1934.54;2933,1934.54)|(2933,1934.84;2873,1934.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2190.54;2933,2190.54)|(2933,2190.84;2873,2190.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1932.54;2933,1932.54)|(2933,1932.84;2873,1932.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1926.54;2933,1926.54)|(2933,1926.84;2873,1926.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2134.54;2933,2134.54)|(2933,2134.84;2873,2134.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1922.54;2933,1922.54)|(2933,1922.84;2873,1922.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1918.54;2933,1918.54)|(2933,1918.84;2873,1918.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1916.54;2933,1916.54)|(2933,1916.84;2873,1916.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2146.54;2933,2146.54)|(2933,2147.5;2873,2147.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1910.54;2933,1910.54)|(2933,1910.84;2873,1910.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1914.54;2933,1914.54)|(2933,1914.84;2873,1914.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1912.54;2933,1912.54)|(2933,1912.84;2873,1912.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1906.54;2933,1906.54)|(2933,1906.84;2873,1906.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1904.54;2933,1904.54)|(2933,1904.84;2873,1904.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2016.54;2933,2016.54)|(2933,2016.84;2873,2016.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1946.54;2933,1946.54)|(2933,1947.5;2873,1947.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2144.54;2933,2144.54)|(2933,2144.84;2873,2144.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2118.54;2933,2118.54)|(2933,2118.84;2873,2118.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1896.54;2933,1896.54)|(2933,1896.84;2873,1896.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2112.54;2933,2112.54)|(2933,2112.84;2873,2112.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1892.54;2933,1892.54)|(2933,1892.84;2873,1892.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1890.54;2933,1890.54)|(2933,1890.84;2873,1890.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2140.54;2933,2140.54)|(2933,2140.84;2873,2140.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2008.54;2933,2008.54)|(2933,2008.84;2873,2008.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2136.54;2933,2136.54)|(2933,2136.84;2873,2136.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2130.54;2933,2130.54)|(2933,2130.84;2873,2130.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2128.54;2933,2128.54)|(2933,2128.84;2873,2128.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2000.54;2933,2000.54)|(2933,2000.84;2873,2000.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1924.54;2933,1924.54)|(2933,1924.84;2873,1924.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2100.54;2933,2100.54)|(2933,2100.84;2873,2100.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1990.54;2933,1990.54)|(2933,1990.84;2873,1990.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1930.54;2933,1930.54)|(2933,1930.84;2873,1930.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2024.54;2933,2024.54)|(2933,2024.84;2873,2024.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2122.54;2933,2122.54)|(2933,2122.84;2873,2122.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2120.54;2933,2120.54)|(2933,2120.84;2873,2120.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2004.54;2933,2004.54)|(2933,2004.84;2873,2004.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1898.54;2933,1898.54)|(2933,1898.84;2873,1898.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2090.54;2933,2090.54)|(2933,2090.84;2873,2090.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1902.54;2933,1902.54)|(2933,1902.84;2873,1902.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1908.54;2933,1908.54)|(2933,1908.84;2873,1908.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2116.54;2933,2116.54)|(2933,2116.84;2873,2116.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2114.54;2933,2114.54)|(2933,2114.84;2873,2114.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2096.54;2933,2096.54)|(2933,2096.84;2873,2096.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2110.54;2933,2110.54)|(2933,2110.84;2873,2110.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1920.54;2933,1920.54)|(2933,1920.84;2873,1920.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2108.54;2933,2108.54)|(2933,2108.84;2873,2108.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2124.54;2933,2124.54)|(2933,2124.84;2873,2124.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2196.54;2933,2196.54)|(2933,2196.84;2873,2196.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2126.54;2933,2126.54)|(2933,2126.84;2873,2126.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2032.54;2933,2032.54)|(2933,2032.84;2873,2032.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1900.54;2933,1900.54)|(2933,1900.84;2873,1900.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2036.54;2933,2036.54)|(2933,2036.84;2873,2036.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2138.54;2933,2138.54)|(2933,2138.84;2873,2138.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1894.54;2933,1894.54)|(2933,1894.84;2873,1894.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2014.54;2933,2014.54)|(2933,2014.84;2873,2014.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,2106.54;2933,2106.54)|(2933,2106.84;2873,2106.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1714.54;2933,1714.54)|(2933,1714.84;2873,1714.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1534.54;2933,1534.54)|(2933,1534.84;2873,1534.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1710.54;2933,1710.54)|(2933,1710.84;2873,1710.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1708.54;2933,1708.54)|(2933,1708.84;2873,1708.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1510.54;2933,1510.54)|(2933,1510.84;2873,1510.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1616.54;2933,1616.54)|(2933,1616.84;2873,1616.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1612.54;2933,1612.54)|(2933,1612.84;2873,1612.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1706.54;2933,1706.54)|(2933,1706.84;2873,1706.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1746.54;2933,1746.54)|(2933,1747.5;2873,1747.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1702.54;2933,1702.54)|(2933,1702.84;2873,1702.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1700.54;2933,1700.54)|(2933,1700.84;2873,1700.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1632.54;2933,1632.54)|(2933,1632.84;2873,1632.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1698.54;2933,1698.54)|(2933,1698.84;2873,1698.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1696.54;2933,1696.54)|(2933,1696.84;2873,1696.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1542.54;2933,1542.54)|(2933,1542.84;2873,1542.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1638.54;2933,1638.54)|(2933,1638.84;2873,1638.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1642.54;2933,1642.54)|(2933,1642.84;2873,1642.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1636.54;2933,1636.54)|(2933,1636.84;2873,1636.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1592.54;2933,1592.54)|(2933,1592.84;2873,1592.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1634.54;2933,1634.54)|(2933,1634.84;2873,1634.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1626.54;2933,1626.54)|(2933,1626.84;2873,1626.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1744.54;2933,1744.54)|(2933,1744.84;2873,1744.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1624.54;2933,1624.54)|(2933,1624.84;2873,1624.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1704.54;2933,1704.54)|(2933,1704.84;2873,1704.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1622.54;2933,1622.54)|(2933,1622.84;2873,1622.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1492.54;2933,1492.54)|(2933,1492.84;2873,1492.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1620.54;2933,1620.54)|(2933,1620.84;2873,1620.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1610.54;2933,1610.54)|(2933,1610.84;2873,1610.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1742.54;2933,1742.54)|(2933,1742.84;2873,1742.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1532.54;2933,1532.54)|(2933,1532.84;2873,1532.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1608.54;2933,1608.54)|(2933,1608.84;2873,1608.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1604.54;2933,1604.54)|(2933,1604.84;2873,1604.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1602.54;2933,1602.54)|(2933,1602.84;2873,1602.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1740.54;2933,1740.54)|(2933,1740.84;2873,1740.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1630.54;2933,1630.54)|(2933,1630.84;2873,1630.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1600.54;2933,1600.54)|(2933,1600.84;2873,1600.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1598.54;2933,1598.54)|(2933,1598.84;2873,1598.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1720.54;2933,1720.54)|(2933,1720.84;2873,1720.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1494.54;2933,1494.54)|(2933,1494.84;2873,1494.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1544.54;2933,1544.54)|(2933,1544.84;2873,1544.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1596.54;2933,1596.54)|(2933,1596.84;2873,1596.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1738.54;2933,1738.54)|(2933,1738.84;2873,1738.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1736.54;2933,1736.54)|(2933,1736.84;2873,1736.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1646.54;2933,1646.54)|(2933,1647.5;2873,1647.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1536.54;2933,1536.54)|(2933,1536.84;2873,1536.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1606.54;2933,1606.54)|(2933,1606.84;2873,1606.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1590.54;2933,1590.54)|(2933,1590.84;2873,1590.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1540.54;2933,1540.54)|(2933,1540.84;2873,1540.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1734.54;2933,1734.54)|(2933,1734.84;2873,1734.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1490.54;2933,1490.54)|(2933,1490.84;2873,1490.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1732.54;2933,1732.54)|(2933,1732.84;2873,1732.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1640.54;2933,1640.54)|(2933,1640.84;2873,1640.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1618.54;2933,1618.54)|(2933,1618.84;2873,1618.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1538.54;2933,1538.54)|(2933,1538.84;2873,1538.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1730.54;2933,1730.54)|(2933,1730.84;2873,1730.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1530.54;2933,1530.54)|(2933,1530.84;2873,1530.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1528.54;2933,1528.54)|(2933,1528.84;2873,1528.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1526.54;2933,1526.54)|(2933,1526.84;2873,1526.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1728.54;2933,1728.54)|(2933,1728.84;2873,1728.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1724.54;2933,1724.54)|(2933,1724.84;2873,1724.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1524.54;2933,1524.54)|(2933,1524.84;2873,1524.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1522.54;2933,1522.54)|(2933,1522.84;2873,1522.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1520.54;2933,1520.54)|(2933,1520.84;2873,1520.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1644.54;2933,1644.54)|(2933,1644.84;2873,1644.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1692.54;2933,1692.54)|(2933,1692.84;2873,1692.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1594.54;2933,1594.54)|(2933,1594.84;2873,1594.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1518.54;2933,1518.54)|(2933,1518.84;2873,1518.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1722.54;2933,1722.54)|(2933,1722.84;2873,1722.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1690.54;2933,1690.54)|(2933,1690.84;2873,1690.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1628.54;2933,1628.54)|(2933,1628.84;2873,1628.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1516.54;2933,1516.54)|(2933,1516.84;2873,1516.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1718.54;2933,1718.54)|(2933,1718.84;2873,1718.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1726.54;2933,1726.54)|(2933,1726.84;2873,1726.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1716.54;2933,1716.54)|(2933,1716.84;2873,1716.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1512.54;2933,1512.54)|(2933,1512.84;2873,1512.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1508.54;2933,1508.54)|(2933,1508.84;2873,1508.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1506.54;2933,1506.54)|(2933,1506.84;2873,1506.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1504.54;2933,1504.54)|(2933,1504.84;2873,1504.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1502.54;2933,1502.54)|(2933,1502.84;2873,1502.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1500.54;2933,1500.54)|(2933,1500.84;2873,1500.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1712.54;2933,1712.54)|(2933,1712.84;2873,1712.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1546.54;2933,1546.54)|(2933,1547.5;2873,1547.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1498.54;2933,1498.54)|(2933,1498.84;2873,1498.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1614.54;2933,1614.54)|(2933,1614.84;2873,1614.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1514.54;2933,1514.54)|(2933,1514.84;2873,1514.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1496.54;2933,1496.54)|(2933,1496.84;2873,1496.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1694.54;2933,1694.54)|(2933,1694.84;2873,1694.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2200.16;62,2200.16)|(62,2200.46;2,2200.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (1434.46,2873;1434.46,2933)|(1434.16,2933;1434.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1426.46,2873;1426.46,2933)|(1426.16,2933;1426.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1424.46,2873;1424.46,2933)|(1424.16,2933;1424.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1418.46,2873;1418.46,2933)|(1418.16,2933;1418.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (922.46,2873;922.46,2933)|(922.16,2933;922.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1412.46,2873;1412.46,2933)|(1412.16,2933;1412.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1422.46,2873;1422.46,2933)|(1422.16,2933;1422.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1408.46,2873;1408.46,2933)|(1408.16,2933;1408.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (926.46,2873;926.46,2933)|(926.16,2933;926.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1428.46,2873;1428.46,2933)|(1428.16,2933;1428.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1108.46,2873;1108.46,2933)|(1108.16,2933;1108.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (920.46,2873;920.46,2933)|(920.16,2933;920.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1404.46,2873;1404.46,2933)|(1404.16,2933;1404.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1414.46,2873;1414.46,2933)|(1414.16,2933;1414.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1402.46,2873;1402.46,2933)|(1402.16,2933;1402.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1396.46,2873;1396.46,2933)|(1396.16,2933;1396.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1390.46,2873;1390.46,2933)|(1390.16,2933;1390.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1394.46,2873;1394.46,2933)|(1394.16,2933;1394.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1388.46,2873;1388.46,2933)|(1387.5,2933;1387.5,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (918.46,2873;918.46,2933)|(918.16,2933;918.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1442.46,2873;1442.46,2933)|(1442.16,2933;1442.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1144.46,2873;1144.46,2933)|(1144.16,2933;1144.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (896.46,2873;896.46,2933)|(896.16,2933;896.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1420.46,2873;1420.46,2933)|(1420.16,2933;1420.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1126.46,2873;1126.46,2933)|(1126.16,2933;1126.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1142.46,2873;1142.46,2933)|(1142.16,2933;1142.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (940.46,2873;940.46,2933)|(940.16,2933;940.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1140.46,2873;1140.46,2933)|(1140.16,2933;1140.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1136.46,2873;1136.46,2933)|(1136.16,2933;1136.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (924.46,2873;924.46,2933)|(924.16,2933;924.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1430.46,2873;1430.46,2933)|(1430.16,2933;1430.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1132.46,2873;1132.46,2933)|(1132.16,2933;1132.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1128.46,2873;1128.46,2933)|(1128.16,2933;1128.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1124.46,2873;1124.46,2933)|(1124.16,2933;1124.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1118.46,2873;1118.46,2933)|(1118.16,2933;1118.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1116.46,2873;1116.46,2933)|(1116.16,2933;1116.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1114.46,2873;1114.46,2933)|(1114.16,2933;1114.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1110.46,2873;1110.46,2933)|(1110.16,2933;1110.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1106.46,2873;1106.46,2933)|(1106.16,2933;1106.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1122.46,2873;1122.46,2933)|(1122.16,2933;1122.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1104.46,2873;1104.46,2933)|(1104.16,2933;1104.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (916.46,2873;916.46,2933)|(916.16,2933;916.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (944.46,2873;944.46,2933)|(944.16,2933;944.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1130.46,2873;1130.46,2933)|(1130.16,2933;1130.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1416.46,2873;1416.46,2933)|(1416.16,2933;1416.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1440.46,2873;1440.46,2933)|(1440.16,2933;1440.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1102.46,2873;1102.46,2933)|(1102.16,2933;1102.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1410.46,2873;1410.46,2933)|(1410.16,2933;1410.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (938.46,2873;938.46,2933)|(938.16,2933;938.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1100.46,2873;1100.46,2933)|(1100.16,2933;1100.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1098.46,2873;1098.46,2933)|(1098.16,2933;1098.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1094.46,2873;1094.46,2933)|(1094.16,2933;1094.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1138.46,2873;1138.46,2933)|(1138.16,2933;1138.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (906.46,2873;906.46,2933)|(906.16,2933;906.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1120.46,2873;1120.46,2933)|(1120.16,2933;1120.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (942.46,2873;942.46,2933)|(942.16,2933;942.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1092.46,2873;1092.46,2933)|(1092.16,2933;1092.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1090.46,2873;1090.46,2933)|(1090.16,2933;1090.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1088.46,2873;1088.46,2933)|(1087.5,2933;1087.5,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1096.46,2873;1096.46,2933)|(1096.16,2933;1096.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (936.46,2873;936.46,2933)|(936.16,2933;936.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1438.46,2873;1438.46,2933)|(1438.16,2933;1438.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1134.46,2873;1134.46,2933)|(1134.16,2933;1134.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (904.46,2873;904.46,2933)|(904.16,2933;904.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (930.46,2873;930.46,2933)|(930.16,2933;930.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (934.46,2873;934.46,2933)|(934.16,2933;934.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (932.46,2873;932.46,2933)|(932.16,2933;932.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1432.46,2873;1432.46,2933)|(1432.16,2933;1432.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1444.46,2873;1444.46,2933)|(1444.16,2933;1444.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (928.46,2873;928.46,2933)|(928.16,2933;928.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (912.46,2873;912.46,2933)|(912.16,2933;912.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (902.46,2873;902.46,2933)|(902.16,2933;902.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1436.46,2873;1436.46,2933)|(1436.16,2933;1436.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1392.46,2873;1392.46,2933)|(1392.16,2933;1392.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (900.46,2873;900.46,2933)|(900.16,2933;900.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (898.46,2873;898.46,2933)|(898.16,2933;898.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (894.46,2873;894.46,2933)|(894.16,2933;894.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (910.46,2873;910.46,2933)|(910.16,2933;910.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1406.46,2873;1406.46,2933)|(1406.16,2933;1406.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1112.46,2873;1112.46,2933)|(1112.16,2933;1112.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1400.46,2873;1400.46,2933)|(1400.16,2933;1400.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (892.46,2873;892.46,2933)|(892.16,2933;892.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (1398.46,2873;1398.46,2933)|(1398.16,2933;1398.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (890.46,2873;890.46,2933)|(890.16,2933;890.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (888.46,2873;888.46,2933)|(887.5,2933;887.5,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (908.46,2873;908.46,2933)|(908.16,2933;908.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (914.46,2873;914.46,2933)|(914.16,2933;914.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (390.46,2873;390.46,2933)|(390.16,2933;390.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (396.46,2873;396.46,2933)|(396.16,2933;396.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (438.46,2873;438.46,2933)|(438.16,2933;438.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (420.46,2873;420.46,2933)|(420.16,2933;420.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (434.46,2873;434.46,2933)|(434.16,2933;434.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (432.46,2873;432.46,2933)|(432.16,2933;432.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (428.46,2873;428.46,2933)|(428.16,2933;428.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (426.46,2873;426.46,2933)|(426.16,2933;426.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (416.46,2873;416.46,2933)|(416.16,2933;416.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (436.46,2873;436.46,2933)|(436.16,2933;436.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (424.46,2873;424.46,2933)|(424.16,2933;424.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (388.46,2873;388.46,2933)|(387.5,2933;387.5,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (394.46,2873;394.46,2933)|(394.16,2933;394.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (400.46,2873;400.46,2933)|(400.16,2933;400.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (392.46,2873;392.46,2933)|(392.16,2933;392.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (402.46,2873;402.46,2933)|(402.16,2933;402.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (418.46,2873;418.46,2933)|(418.16,2933;418.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (410.46,2873;410.46,2933)|(410.16,2933;410.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (408.46,2873;408.46,2933)|(408.16,2933;408.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (412.46,2873;412.46,2933)|(412.16,2933;412.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (440.46,2873;440.46,2933)|(440.16,2933;440.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (406.46,2873;406.46,2933)|(406.16,2933;406.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (414.46,2873;414.46,2933)|(414.16,2933;414.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (422.46,2873;422.46,2933)|(422.16,2933;422.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (430.46,2873;430.46,2933)|(430.16,2933;430.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (404.46,2873;404.46,2933)|(404.16,2933;404.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (398.46,2873;398.46,2933)|(398.16,2933;398.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (442.46,2873;442.46,2933)|(442.16,2933;442.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (444.46,2873;444.46,2933)|(444.16,2933;444.16,2873) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2532.16;62,2532.16)|(62,2532.46;2,2532.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2412.16;62,2412.16)|(62,2412.46;2,2412.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2414.16;62,2414.16)|(62,2414.46;2,2414.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2524.16;62,2524.16)|(62,2524.46;2,2524.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2434.16;62,2434.16)|(62,2434.46;2,2434.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2394.16;62,2394.16)|(62,2394.46;2,2394.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2530.16;62,2530.16)|(62,2530.46;2,2530.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2410.16;62,2410.16)|(62,2410.46;2,2410.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2432.16;62,2432.16)|(62,2432.46;2,2432.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2387.5;62,2387.5)|(62,2388.46;2,2388.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2430.16;62,2430.16)|(62,2430.46;2,2430.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2528.16;62,2528.16)|(62,2528.46;2,2528.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2406.16;62,2406.16)|(62,2406.46;2,2406.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2526.16;62,2526.16)|(62,2526.46;2,2526.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2404.16;62,2404.16)|(62,2404.46;2,2404.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2400.16;62,2400.16)|(62,2400.46;2,2400.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2408.16;62,2408.16)|(62,2408.46;2,2408.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2398.16;62,2398.16)|(62,2398.46;2,2398.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2538.16;62,2538.16)|(62,2538.46;2,2538.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2426.16;62,2426.16)|(62,2426.46;2,2426.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2520.16;62,2520.16)|(62,2520.46;2,2520.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2536.16;62,2536.16)|(62,2536.46;2,2536.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2492.16;62,2492.16)|(62,2492.46;2,2492.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2534.16;62,2534.16)|(62,2534.46;2,2534.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2508.16;62,2508.16)|(62,2508.46;2,2508.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2487.5;62,2487.5)|(62,2488.46;2,2488.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2392.16;62,2392.16)|(62,2392.46;2,2392.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2390.16;62,2390.16)|(62,2390.46;2,2390.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2516.16;62,2516.16)|(62,2516.46;2,2516.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2402.16;62,2402.16)|(62,2402.46;2,2402.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2518.16;62,2518.16)|(62,2518.46;2,2518.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2444.16;62,2444.16)|(62,2444.46;2,2444.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2498.16;62,2498.16)|(62,2498.46;2,2498.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2396.16;62,2396.16)|(62,2396.46;2,2396.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2514.16;62,2514.16)|(62,2514.46;2,2514.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2422.16;62,2422.16)|(62,2422.46;2,2422.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2416.16;62,2416.16)|(62,2416.46;2,2416.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2542.16;62,2542.16)|(62,2542.46;2,2542.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2512.16;62,2512.16)|(62,2512.46;2,2512.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2510.16;62,2510.16)|(62,2510.46;2,2510.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2440.16;62,2440.16)|(62,2440.46;2,2440.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2438.16;62,2438.16)|(62,2438.46;2,2438.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2500.16;62,2500.16)|(62,2500.46;2,2500.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2428.16;62,2428.16)|(62,2428.46;2,2428.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2506.16;62,2506.16)|(62,2506.46;2,2506.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2424.16;62,2424.16)|(62,2424.46;2,2424.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2502.16;62,2502.16)|(62,2502.46;2,2502.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2420.16;62,2420.16)|(62,2420.46;2,2420.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2418.16;62,2418.16)|(62,2418.46;2,2418.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2436.16;62,2436.16)|(62,2436.46;2,2436.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2522.16;62,2522.16)|(62,2522.46;2,2522.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2544.16;62,2544.16)|(62,2544.46;2,2544.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2504.16;62,2504.16)|(62,2504.46;2,2504.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2496.16;62,2496.16)|(62,2496.46;2,2496.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2540.16;62,2540.16)|(62,2540.46;2,2540.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2490.16;62,2490.16)|(62,2490.46;2,2490.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2494.16;62,2494.16)|(62,2494.46;2,2494.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2442.16;62,2442.16)|(62,2442.46;2,2442.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2228.16;62,2228.16)|(62,2228.46;2,2228.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2330.16;62,2330.16)|(62,2330.46;2,2330.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2324.16;62,2324.16)|(62,2324.46;2,2324.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2226.16;62,2226.16)|(62,2226.46;2,2226.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2222.16;62,2222.16)|(62,2222.46;2,2222.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2302.16;62,2302.16)|(62,2302.46;2,2302.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2287.5;62,2287.5)|(62,2288.46;2,2288.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2332.16;62,2332.16)|(62,2332.46;2,2332.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2342.16;62,2342.16)|(62,2342.46;2,2342.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2334.16;62,2334.16)|(62,2334.46;2,2334.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2220.16;62,2220.16)|(62,2220.46;2,2220.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2322.16;62,2322.16)|(62,2322.46;2,2322.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2206.16;62,2206.16)|(62,2206.46;2,2206.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2210.16;62,2210.16)|(62,2210.46;2,2210.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2242.16;62,2242.16)|(62,2242.46;2,2242.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2292.16;62,2292.16)|(62,2292.46;2,2292.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2318.16;62,2318.16)|(62,2318.46;2,2318.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2238.16;62,2238.16)|(62,2238.46;2,2238.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2320.16;62,2320.16)|(62,2320.46;2,2320.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2298.16;62,2298.16)|(62,2298.46;2,2298.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2316.16;62,2316.16)|(62,2316.46;2,2316.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2328.16;62,2328.16)|(62,2328.46;2,2328.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2232.16;62,2232.16)|(62,2232.46;2,2232.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2314.16;62,2314.16)|(62,2314.46;2,2314.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2234.16;62,2234.16)|(62,2234.46;2,2234.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2240.16;62,2240.16)|(62,2240.46;2,2240.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2310.16;62,2310.16)|(62,2310.46;2,2310.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2236.16;62,2236.16)|(62,2236.46;2,2236.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2326.16;62,2326.16)|(62,2326.46;2,2326.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2308.16;62,2308.16)|(62,2308.46;2,2308.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2294.16;62,2294.16)|(62,2294.46;2,2294.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2340.16;62,2340.16)|(62,2340.46;2,2340.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2312.16;62,2312.16)|(62,2312.46;2,2312.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2224.16;62,2224.16)|(62,2224.46;2,2224.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2216.16;62,2216.16)|(62,2216.46;2,2216.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2214.16;62,2214.16)|(62,2214.46;2,2214.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2218.16;62,2218.16)|(62,2218.46;2,2218.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2230.16;62,2230.16)|(62,2230.46;2,2230.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2338.16;62,2338.16)|(62,2338.46;2,2338.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2300.16;62,2300.16)|(62,2300.46;2,2300.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2306.16;62,2306.16)|(62,2306.46;2,2306.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2304.16;62,2304.16)|(62,2304.46;2,2304.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2208.16;62,2208.16)|(62,2208.46;2,2208.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2204.16;62,2204.16)|(62,2204.46;2,2204.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2344.16;62,2344.16)|(62,2344.46;2,2344.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2212.16;62,2212.16)|(62,2212.46;2,2212.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2202.16;62,2202.16)|(62,2202.46;2,2202.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2290.16;62,2290.16)|(62,2290.46;2,2290.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2244.16;62,2244.16)|(62,2244.46;2,2244.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2296.16;62,2296.16)|(62,2296.46;2,2296.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2336.16;62,2336.16)|(62,2336.46;2,2336.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2098.16;62,2098.16)|(62,2098.46;2,2098.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2134.16;62,2134.16)|(62,2134.46;2,2134.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2038.16;62,2038.16)|(62,2038.46;2,2038.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1994.16;62,1994.16)|(62,1994.46;2,1994.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1992.16;62,1992.16)|(62,1992.46;2,1992.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2128.16;62,2128.16)|(62,2128.46;2,2128.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2144.16;62,2144.16)|(62,2144.46;2,2144.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1944.16;62,1944.16)|(62,1944.46;2,1944.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2116.16;62,2116.16)|(62,2116.46;2,2116.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1940.16;62,1940.16)|(62,1940.46;2,1940.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2124.16;62,2124.16)|(62,2124.46;2,2124.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1904.16;62,1904.16)|(62,1904.46;2,1904.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1938.16;62,1938.16)|(62,1938.46;2,1938.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1834.16;62,1834.16)|(62,1834.46;2,1834.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1934.16;62,1934.16)|(62,1934.46;2,1934.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1932.16;62,1932.16)|(62,1932.46;2,1932.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2126.16;62,2126.16)|(62,2126.46;2,2126.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1842.16;62,1842.16)|(62,1842.46;2,1842.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2118.16;62,2118.16)|(62,2118.46;2,2118.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1930.16;62,1930.16)|(62,1930.46;2,1930.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2114.16;62,2114.16)|(62,2114.46;2,2114.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1924.16;62,1924.16)|(62,1924.46;2,1924.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1922.16;62,1922.16)|(62,1922.46;2,1922.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1920.16;62,1920.16)|(62,1920.46;2,1920.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1912.16;62,1912.16)|(62,1912.46;2,1912.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2112.16;62,2112.16)|(62,2112.46;2,2112.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2018.16;62,2018.16)|(62,2018.46;2,2018.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1910.16;62,1910.16)|(62,1910.46;2,1910.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1908.16;62,1908.16)|(62,1908.46;2,1908.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2132.16;62,2132.16)|(62,2132.46;2,2132.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2110.16;62,2110.16)|(62,2110.46;2,2110.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2032.16;62,2032.16)|(62,2032.46;2,2032.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1906.16;62,1906.16)|(62,1906.46;2,1906.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1900.16;62,1900.16)|(62,1900.46;2,1900.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2108.16;62,2108.16)|(62,2108.46;2,2108.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1902.16;62,1902.16)|(62,1902.46;2,1902.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2138.16;62,2138.16)|(62,2138.46;2,2138.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2106.16;62,2106.16)|(62,2106.46;2,2106.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1898.16;62,1898.16)|(62,1898.46;2,1898.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1896.16;62,1896.16)|(62,1896.46;2,1896.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2140.16;62,2140.16)|(62,2140.46;2,2140.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2104.16;62,2104.16)|(62,2104.46;2,2104.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2198.16;62,2198.16)|(62,2198.46;2,2198.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1892.16;62,1892.16)|(62,1892.46;2,1892.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1890.16;62,1890.16)|(62,1890.46;2,1890.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1887.5;62,1887.5)|(62,1888.46;2,1888.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1844.16;62,1844.16)|(62,1844.46;2,1844.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1840.16;62,1840.16)|(62,1840.46;2,1840.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2008.16;62,2008.16)|(62,2008.46;2,2008.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1838.16;62,1838.16)|(62,1838.46;2,1838.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1836.16;62,1836.16)|(62,1836.46;2,1836.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2102.16;62,2102.16)|(62,2102.46;2,2102.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1914.16;62,1914.16)|(62,1914.46;2,1914.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2120.16;62,2120.16)|(62,2120.46;2,2120.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2020.16;62,2020.16)|(62,2020.46;2,2020.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2094.16;62,2094.16)|(62,2094.46;2,2094.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2092.16;62,2092.16)|(62,2092.46;2,2092.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2090.16;62,2090.16)|(62,2090.46;2,2090.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2130.16;62,2130.16)|(62,2130.46;2,2130.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2087.5;62,2087.5)|(62,2088.46;2,2088.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2196.16;62,2196.16)|(62,2196.46;2,2196.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1918.16;62,1918.16)|(62,1918.46;2,1918.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2014.16;62,2014.16)|(62,2014.46;2,2014.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2044.16;62,2044.16)|(62,2044.46;2,2044.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2122.16;62,2122.16)|(62,2122.46;2,2122.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2006.16;62,2006.16)|(62,2006.46;2,2006.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2042.16;62,2042.16)|(62,2042.46;2,2042.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1990.16;62,1990.16)|(62,1990.46;2,1990.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2040.16;62,2040.16)|(62,2040.46;2,2040.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2136.16;62,2136.16)|(62,2136.46;2,2136.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1996.16;62,1996.16)|(62,1996.46;2,1996.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2036.16;62,2036.16)|(62,2036.46;2,2036.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2034.16;62,2034.16)|(62,2034.46;2,2034.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2028.16;62,2028.16)|(62,2028.46;2,2028.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2192.16;62,2192.16)|(62,2192.46;2,2192.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2187.5;62,2187.5)|(62,2188.46;2,2188.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2004.16;62,2004.16)|(62,2004.46;2,2004.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2190.16;62,2190.16)|(62,2190.46;2,2190.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1894.16;62,1894.16)|(62,1894.46;2,1894.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2030.16;62,2030.16)|(62,2030.46;2,2030.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2026.16;62,2026.16)|(62,2026.46;2,2026.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1926.16;62,1926.16)|(62,1926.46;2,1926.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2024.16;62,2024.16)|(62,2024.46;2,2024.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1928.16;62,1928.16)|(62,1928.46;2,1928.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2022.16;62,2022.16)|(62,2022.46;2,2022.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2016.16;62,2016.16)|(62,2016.46;2,2016.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2100.16;62,2100.16)|(62,2100.46;2,2100.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1916.16;62,1916.16)|(62,1916.46;2,1916.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2012.16;62,2012.16)|(62,2012.46;2,2012.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2010.16;62,2010.16)|(62,2010.46;2,2010.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2142.16;62,2142.16)|(62,2142.46;2,2142.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2194.16;62,2194.16)|(62,2194.46;2,2194.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1987.5;62,1987.5)|(62,1988.46;2,1988.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2096.16;62,2096.16)|(62,2096.46;2,2096.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1942.16;62,1942.16)|(62,1942.46;2,1942.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2000.16;62,2000.16)|(62,2000.46;2,2000.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,2002.16;62,2002.16)|(62,2002.46;2,2002.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1936.16;62,1936.16)|(62,1936.46;2,1936.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1998.16;62,1998.16)|(62,1998.46;2,1998.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1830.16;62,1830.16)|(62,1830.46;2,1830.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1828.16;62,1828.16)|(62,1828.46;2,1828.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1824.16;62,1824.16)|(62,1824.46;2,1824.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1818.16;62,1818.16)|(62,1818.46;2,1818.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1808.16;62,1808.16)|(62,1808.46;2,1808.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1806.16;62,1806.16)|(62,1806.46;2,1806.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1734.16;62,1734.16)|(62,1734.46;2,1734.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1698.16;62,1698.16)|(62,1698.46;2,1698.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1802.16;62,1802.16)|(62,1802.46;2,1802.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1796.16;62,1796.16)|(62,1796.46;2,1796.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1794.16;62,1794.16)|(62,1794.46;2,1794.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1790.16;62,1790.16)|(62,1790.46;2,1790.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1787.5;62,1787.5)|(62,1788.46;2,1788.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1744.16;62,1744.16)|(62,1744.46;2,1744.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1742.16;62,1742.16)|(62,1742.46;2,1742.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1812.16;62,1812.16)|(62,1812.46;2,1812.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1738.16;62,1738.16)|(62,1738.46;2,1738.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1736.16;62,1736.16)|(62,1736.46;2,1736.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1696.16;62,1696.16)|(62,1696.46;2,1696.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1822.16;62,1822.16)|(62,1822.46;2,1822.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1798.16;62,1798.16)|(62,1798.46;2,1798.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1730.16;62,1730.16)|(62,1730.46;2,1730.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1720.16;62,1720.16)|(62,1720.46;2,1720.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1804.16;62,1804.16)|(62,1804.46;2,1804.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1728.16;62,1728.16)|(62,1728.46;2,1728.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1726.16;62,1726.16)|(62,1726.46;2,1726.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1724.16;62,1724.16)|(62,1724.46;2,1724.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1816.16;62,1816.16)|(62,1816.46;2,1816.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1722.16;62,1722.16)|(62,1722.46;2,1722.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1732.16;62,1732.16)|(62,1732.46;2,1732.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1718.16;62,1718.16)|(62,1718.46;2,1718.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1712.16;62,1712.16)|(62,1712.46;2,1712.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1716.16;62,1716.16)|(62,1716.46;2,1716.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1690.16;62,1690.16)|(62,1690.46;2,1690.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1714.16;62,1714.16)|(62,1714.46;2,1714.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1826.16;62,1826.16)|(62,1826.46;2,1826.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1710.16;62,1710.16)|(62,1710.46;2,1710.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1820.16;62,1820.16)|(62,1820.46;2,1820.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1810.16;62,1810.16)|(62,1810.46;2,1810.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1832.16;62,1832.16)|(62,1832.46;2,1832.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1708.16;62,1708.16)|(62,1708.46;2,1708.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1700.16;62,1700.16)|(62,1700.46;2,1700.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1706.16;62,1706.16)|(62,1706.46;2,1706.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1704.16;62,1704.16)|(62,1704.46;2,1704.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1702.16;62,1702.16)|(62,1702.46;2,1702.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1740.16;62,1740.16)|(62,1740.46;2,1740.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1694.16;62,1694.16)|(62,1694.46;2,1694.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1792.16;62,1792.16)|(62,1792.46;2,1792.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1687.5;62,1687.5)|(62,1688.46;2,1688.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1814.16;62,1814.16)|(62,1814.46;2,1814.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1800.16;62,1800.16)|(62,1800.46;2,1800.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1692.16;62,1692.16)|(62,1692.46;2,1692.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1500.16;62,1500.16)|(62,1500.46;2,1500.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1594.16;62,1594.16)|(62,1594.46;2,1594.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1636.16;62,1636.16)|(62,1636.46;2,1636.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1536.16;62,1536.16)|(62,1536.46;2,1536.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1542.16;62,1542.16)|(62,1542.46;2,1542.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1614.16;62,1614.16)|(62,1614.46;2,1614.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1530.16;62,1530.16)|(62,1530.46;2,1530.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1528.16;62,1528.16)|(62,1528.46;2,1528.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1526.16;62,1526.16)|(62,1526.46;2,1526.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1628.16;62,1628.16)|(62,1628.46;2,1628.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1624.16;62,1624.16)|(62,1624.46;2,1624.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1504.16;62,1504.16)|(62,1504.46;2,1504.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1498.16;62,1498.16)|(62,1498.46;2,1498.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1644.16;62,1644.16)|(62,1644.46;2,1644.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1534.16;62,1534.16)|(62,1534.46;2,1534.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1640.16;62,1640.16)|(62,1640.46;2,1640.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1496.16;62,1496.16)|(62,1496.46;2,1496.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1490.16;62,1490.16)|(62,1490.46;2,1490.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1604.16;62,1604.16)|(62,1604.46;2,1604.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1592.16;62,1592.16)|(62,1592.46;2,1592.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1590.16;62,1590.16)|(62,1590.46;2,1590.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1524.16;62,1524.16)|(62,1524.46;2,1524.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1512.16;62,1512.16)|(62,1512.46;2,1512.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1587.5;62,1587.5)|(62,1588.46;2,1588.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1634.16;62,1634.16)|(62,1634.46;2,1634.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1608.16;62,1608.16)|(62,1608.46;2,1608.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1518.16;62,1518.16)|(62,1518.46;2,1518.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1622.16;62,1622.16)|(62,1622.46;2,1622.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1502.16;62,1502.16)|(62,1502.46;2,1502.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1632.16;62,1632.16)|(62,1632.46;2,1632.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1510.16;62,1510.16)|(62,1510.46;2,1510.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1602.16;62,1602.16)|(62,1602.46;2,1602.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1600.16;62,1600.16)|(62,1600.46;2,1600.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1532.16;62,1532.16)|(62,1532.46;2,1532.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1538.16;62,1538.16)|(62,1538.46;2,1538.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1516.16;62,1516.16)|(62,1516.46;2,1516.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1544.16;62,1544.16)|(62,1544.46;2,1544.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1606.16;62,1606.16)|(62,1606.46;2,1606.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1540.16;62,1540.16)|(62,1540.46;2,1540.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1616.16;62,1616.16)|(62,1616.46;2,1616.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1596.16;62,1596.16)|(62,1596.46;2,1596.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1612.16;62,1612.16)|(62,1612.46;2,1612.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1610.16;62,1610.16)|(62,1610.46;2,1610.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1494.16;62,1494.16)|(62,1494.46;2,1494.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1618.16;62,1618.16)|(62,1618.46;2,1618.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1508.16;62,1508.16)|(62,1508.46;2,1508.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1626.16;62,1626.16)|(62,1626.46;2,1626.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1506.16;62,1506.16)|(62,1506.46;2,1506.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1514.16;62,1514.16)|(62,1514.46;2,1514.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1620.16;62,1620.16)|(62,1620.46;2,1620.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1520.16;62,1520.16)|(62,1520.46;2,1520.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1630.16;62,1630.16)|(62,1630.46;2,1630.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1642.16;62,1642.16)|(62,1642.46;2,1642.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1638.16;62,1638.16)|(62,1638.46;2,1638.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1487.5;62,1487.5)|(62,1488.46;2,1488.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1598.16;62,1598.16)|(62,1598.46;2,1598.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1522.16;62,1522.16)|(62,1522.46;2,1522.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1492.16;62,1492.16)|(62,1492.46;2,1492.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (734.84,2;734.84,62)|(734.54,62;734.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1442.16;62,1442.16)|(62,1442.46;2,1442.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1292.16;62,1292.16)|(62,1292.46;2,1292.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1426.16;62,1426.16)|(62,1426.46;2,1426.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1312.16;62,1312.16)|(62,1312.46;2,1312.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1328.16;62,1328.16)|(62,1328.46;2,1328.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1400.16;62,1400.16)|(62,1400.46;2,1400.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1436.16;62,1436.16)|(62,1436.46;2,1436.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1408.16;62,1408.16)|(62,1408.46;2,1408.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1338.16;62,1338.16)|(62,1338.46;2,1338.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1340.16;62,1340.16)|(62,1340.46;2,1340.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1336.16;62,1336.16)|(62,1336.46;2,1336.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1394.16;62,1394.16)|(62,1394.46;2,1394.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1440.16;62,1440.16)|(62,1440.46;2,1440.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1332.16;62,1332.16)|(62,1332.46;2,1332.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1314.16;62,1314.16)|(62,1314.46;2,1314.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1318.16;62,1318.16)|(62,1318.46;2,1318.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1320.16;62,1320.16)|(62,1320.46;2,1320.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1310.16;62,1310.16)|(62,1310.46;2,1310.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1330.16;62,1330.16)|(62,1330.46;2,1330.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1322.16;62,1322.16)|(62,1322.46;2,1322.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1342.16;62,1342.16)|(62,1342.46;2,1342.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1414.16;62,1414.16)|(62,1414.46;2,1414.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1412.16;62,1412.16)|(62,1412.46;2,1412.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1410.16;62,1410.16)|(62,1410.46;2,1410.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1416.16;62,1416.16)|(62,1416.46;2,1416.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1406.16;62,1406.16)|(62,1406.46;2,1406.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1428.16;62,1428.16)|(62,1428.46;2,1428.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1444.16;62,1444.16)|(62,1444.46;2,1444.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1438.16;62,1438.16)|(62,1438.46;2,1438.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1434.16;62,1434.16)|(62,1434.46;2,1434.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1430.16;62,1430.16)|(62,1430.46;2,1430.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1424.16;62,1424.16)|(62,1424.46;2,1424.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1422.16;62,1422.16)|(62,1422.46;2,1422.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1418.16;62,1418.16)|(62,1418.46;2,1418.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1390.16;62,1390.16)|(62,1390.46;2,1390.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1387.5;62,1387.5)|(62,1388.46;2,1388.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1404.16;62,1404.16)|(62,1404.46;2,1404.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1306.16;62,1306.16)|(62,1306.46;2,1306.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1396.16;62,1396.16)|(62,1396.46;2,1396.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1316.16;62,1316.16)|(62,1316.46;2,1316.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1344.16;62,1344.16)|(62,1344.46;2,1344.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1287.5;62,1287.5)|(62,1288.46;2,1288.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1398.16;62,1398.16)|(62,1398.46;2,1398.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1290.16;62,1290.16)|(62,1290.46;2,1290.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1294.16;62,1294.16)|(62,1294.46;2,1294.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1296.16;62,1296.16)|(62,1296.46;2,1296.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1302.16;62,1302.16)|(62,1302.46;2,1302.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1308.16;62,1308.16)|(62,1308.46;2,1308.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1304.16;62,1304.16)|(62,1304.46;2,1304.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1300.16;62,1300.16)|(62,1300.46;2,1300.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1298.16;62,1298.16)|(62,1298.46;2,1298.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1324.16;62,1324.16)|(62,1324.46;2,1324.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1420.16;62,1420.16)|(62,1420.46;2,1420.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1432.16;62,1432.16)|(62,1432.46;2,1432.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1334.16;62,1334.16)|(62,1334.46;2,1334.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1402.16;62,1402.16)|(62,1402.46;2,1402.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1326.16;62,1326.16)|(62,1326.46;2,1326.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1392.16;62,1392.16)|(62,1392.46;2,1392.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1210.16;62,1210.16)|(62,1210.46;2,1210.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1110.16;62,1110.16)|(62,1110.46;2,1110.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1116.16;62,1116.16)|(62,1116.46;2,1116.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1118.16;62,1118.16)|(62,1118.46;2,1118.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1120.16;62,1120.16)|(62,1120.46;2,1120.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1128.16;62,1128.16)|(62,1128.46;2,1128.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1122.16;62,1122.16)|(62,1122.46;2,1122.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1108.16;62,1108.16)|(62,1108.46;2,1108.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1130.16;62,1130.16)|(62,1130.46;2,1130.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1132.16;62,1132.16)|(62,1132.46;2,1132.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1140.16;62,1140.16)|(62,1140.46;2,1140.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1192.16;62,1192.16)|(62,1192.46;2,1192.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1190.16;62,1190.16)|(62,1190.46;2,1190.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1187.5;62,1187.5)|(62,1188.46;2,1188.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1234.16;62,1234.16)|(62,1234.46;2,1234.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1104.16;62,1104.16)|(62,1104.46;2,1104.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1106.16;62,1106.16)|(62,1106.46;2,1106.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1238.16;62,1238.16)|(62,1238.46;2,1238.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1136.16;62,1136.16)|(62,1136.46;2,1136.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1196.16;62,1196.16)|(62,1196.46;2,1196.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1134.16;62,1134.16)|(62,1134.46;2,1134.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1208.16;62,1208.16)|(62,1208.46;2,1208.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1144.16;62,1144.16)|(62,1144.46;2,1144.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1198.16;62,1198.16)|(62,1198.46;2,1198.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1218.16;62,1218.16)|(62,1218.46;2,1218.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1204.16;62,1204.16)|(62,1204.46;2,1204.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1194.16;62,1194.16)|(62,1194.46;2,1194.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1244.16;62,1244.16)|(62,1244.46;2,1244.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1224.16;62,1224.16)|(62,1224.46;2,1224.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1228.16;62,1228.16)|(62,1228.46;2,1228.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1226.16;62,1226.16)|(62,1226.46;2,1226.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1220.16;62,1220.16)|(62,1220.46;2,1220.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1200.16;62,1200.16)|(62,1200.46;2,1200.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1242.16;62,1242.16)|(62,1242.46;2,1242.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1240.16;62,1240.16)|(62,1240.46;2,1240.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1236.16;62,1236.16)|(62,1236.46;2,1236.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1124.16;62,1124.16)|(62,1124.46;2,1124.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1230.16;62,1230.16)|(62,1230.46;2,1230.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1142.16;62,1142.16)|(62,1142.46;2,1142.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1212.16;62,1212.16)|(62,1212.46;2,1212.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1232.16;62,1232.16)|(62,1232.46;2,1232.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1138.16;62,1138.16)|(62,1138.46;2,1138.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1206.16;62,1206.16)|(62,1206.46;2,1206.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1216.16;62,1216.16)|(62,1216.46;2,1216.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1112.16;62,1112.16)|(62,1112.46;2,1112.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1202.16;62,1202.16)|(62,1202.46;2,1202.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1214.16;62,1214.16)|(62,1214.46;2,1214.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1102.16;62,1102.16)|(62,1102.46;2,1102.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1126.16;62,1126.16)|(62,1126.46;2,1126.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1222.16;62,1222.16)|(62,1222.46;2,1222.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1114.16;62,1114.16)|(62,1114.46;2,1114.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1010.16;62,1010.16)|(62,1010.46;2,1010.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,800.16;62,800.16)|(62,800.46;2,800.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1012.16;62,1012.16)|(62,1012.46;2,1012.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,914.16;62,914.16)|(62,914.46;2,914.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,938.16;62,938.16)|(62,938.46;2,938.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,926.16;62,926.16)|(62,926.46;2,926.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,894.16;62,894.16)|(62,894.46;2,894.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1000.16;62,1000.16)|(62,1000.46;2,1000.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,810.16;62,810.16)|(62,810.46;2,810.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,802.16;62,802.16)|(62,802.46;2,802.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,822.16;62,822.16)|(62,822.46;2,822.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,740.16;62,740.16)|(62,740.46;2,740.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,890.16;62,890.16)|(62,890.46;2,890.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1022.16;62,1022.16)|(62,1022.46;2,1022.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1090.16;62,1090.16)|(62,1090.46;2,1090.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,832.16;62,832.16)|(62,832.46;2,832.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1038.16;62,1038.16)|(62,1038.46;2,1038.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,787.5;62,787.5)|(62,788.46;2,788.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1044.16;62,1044.16)|(62,1044.46;2,1044.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,834.16;62,834.16)|(62,834.46;2,834.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,820.16;62,820.16)|(62,820.46;2,820.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1087.5;62,1087.5)|(62,1088.46;2,1088.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1042.16;62,1042.16)|(62,1042.46;2,1042.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1092.16;62,1092.16)|(62,1092.46;2,1092.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1094.16;62,1094.16)|(62,1094.46;2,1094.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1098.16;62,1098.16)|(62,1098.46;2,1098.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1100.16;62,1100.16)|(62,1100.46;2,1100.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,906.16;62,906.16)|(62,906.46;2,906.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,902.16;62,902.16)|(62,902.46;2,902.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,816.16;62,816.16)|(62,816.46;2,816.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1006.16;62,1006.16)|(62,1006.46;2,1006.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,836.16;62,836.16)|(62,836.46;2,836.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1020.16;62,1020.16)|(62,1020.46;2,1020.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,840.16;62,840.16)|(62,840.46;2,840.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,842.16;62,842.16)|(62,842.46;2,842.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,844.16;62,844.16)|(62,844.46;2,844.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,808.16;62,808.16)|(62,808.46;2,808.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,892.16;62,892.16)|(62,892.46;2,892.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,896.16;62,896.16)|(62,896.46;2,896.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,790.16;62,790.16)|(62,790.46;2,790.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,898.16;62,898.16)|(62,898.46;2,898.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,934.16;62,934.16)|(62,934.46;2,934.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,794.16;62,794.16)|(62,794.46;2,794.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,812.16;62,812.16)|(62,812.46;2,812.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,942.16;62,942.16)|(62,942.46;2,942.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,814.16;62,814.16)|(62,814.46;2,814.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,792.16;62,792.16)|(62,792.46;2,792.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,887.5;62,887.5)|(62,888.46;2,888.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,824.16;62,824.16)|(62,824.46;2,824.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,798.16;62,798.16)|(62,798.46;2,798.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,804.16;62,804.16)|(62,804.46;2,804.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,826.16;62,826.16)|(62,826.46;2,826.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,828.16;62,828.16)|(62,828.46;2,828.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,992.16;62,992.16)|(62,992.46;2,992.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1040.16;62,1040.16)|(62,1040.46;2,1040.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1014.16;62,1014.16)|(62,1014.46;2,1014.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,924.16;62,924.16)|(62,924.46;2,924.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1016.16;62,1016.16)|(62,1016.46;2,1016.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,928.16;62,928.16)|(62,928.46;2,928.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,930.16;62,930.16)|(62,930.46;2,930.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1018.16;62,1018.16)|(62,1018.46;2,1018.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,932.16;62,932.16)|(62,932.46;2,932.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,900.16;62,900.16)|(62,900.46;2,900.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,940.16;62,940.16)|(62,940.46;2,940.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,918.16;62,918.16)|(62,918.46;2,918.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1028.16;62,1028.16)|(62,1028.46;2,1028.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,922.16;62,922.16)|(62,922.46;2,922.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1030.16;62,1030.16)|(62,1030.46;2,1030.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,987.5;62,987.5)|(62,988.46;2,988.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,910.16;62,910.16)|(62,910.46;2,910.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1032.16;62,1032.16)|(62,1032.46;2,1032.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,806.16;62,806.16)|(62,806.46;2,806.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,912.16;62,912.16)|(62,912.46;2,912.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,916.16;62,916.16)|(62,916.46;2,916.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,920.16;62,920.16)|(62,920.46;2,920.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1034.16;62,1034.16)|(62,1034.46;2,1034.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1036.16;62,1036.16)|(62,1036.46;2,1036.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,736.16;62,736.16)|(62,736.46;2,736.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,738.16;62,738.16)|(62,738.46;2,738.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,994.16;62,994.16)|(62,994.46;2,994.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,990.16;62,990.16)|(62,990.46;2,990.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,936.16;62,936.16)|(62,936.46;2,936.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1026.16;62,1026.16)|(62,1026.46;2,1026.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,818.16;62,818.16)|(62,818.46;2,818.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,742.16;62,742.16)|(62,742.46;2,742.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,996.16;62,996.16)|(62,996.46;2,996.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,796.16;62,796.16)|(62,796.46;2,796.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,830.16;62,830.16)|(62,830.46;2,830.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,998.16;62,998.16)|(62,998.46;2,998.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,904.16;62,904.16)|(62,904.46;2,904.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1002.16;62,1002.16)|(62,1002.46;2,1002.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1004.16;62,1004.16)|(62,1004.46;2,1004.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1024.16;62,1024.16)|(62,1024.46;2,1024.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,908.16;62,908.16)|(62,908.46;2,908.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1008.16;62,1008.16)|(62,1008.46;2,1008.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,944.16;62,944.16)|(62,944.46;2,944.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,838.16;62,838.16)|(62,838.46;2,838.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,744.16;62,744.16)|(62,744.46;2,744.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,1096.16;62,1096.16)|(62,1096.46;2,1096.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,722.16;62,722.16)|(62,722.46;2,722.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,508.16;62,508.16)|(62,508.46;2,508.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,638.16;62,638.16)|(62,638.46;2,638.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,518.16;62,518.16)|(62,518.46;2,518.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,620.16;62,620.16)|(62,620.46;2,620.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,724.16;62,724.16)|(62,724.46;2,724.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,616.16;62,616.16)|(62,616.46;2,616.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,732.16;62,732.16)|(62,732.46;2,732.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,714.16;62,714.16)|(62,714.46;2,714.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,636.16;62,636.16)|(62,636.46;2,636.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,506.16;62,506.16)|(62,506.46;2,506.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,514.16;62,514.16)|(62,514.46;2,514.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,494.16;62,494.16)|(62,494.46;2,494.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,728.16;62,728.16)|(62,728.46;2,728.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,696.16;62,696.16)|(62,696.46;2,696.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,502.16;62,502.16)|(62,502.46;2,502.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,644.16;62,644.16)|(62,644.46;2,644.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,510.16;62,510.16)|(62,510.46;2,510.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,602.16;62,602.16)|(62,602.46;2,602.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,504.16;62,504.16)|(62,504.46;2,504.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,710.16;62,710.16)|(62,710.46;2,710.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,720.16;62,720.16)|(62,720.46;2,720.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,698.16;62,698.16)|(62,698.46;2,698.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,700.16;62,700.16)|(62,700.46;2,700.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,702.16;62,702.16)|(62,702.46;2,702.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,704.16;62,704.16)|(62,704.46;2,704.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,694.16;62,694.16)|(62,694.46;2,694.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,487.5;62,487.5)|(62,488.46;2,488.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,490.16;62,490.16)|(62,490.46;2,490.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,492.16;62,492.16)|(62,492.46;2,492.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,520.16;62,520.16)|(62,520.46;2,520.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,708.16;62,708.16)|(62,708.46;2,708.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,544.16;62,544.16)|(62,544.46;2,544.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,590.16;62,590.16)|(62,590.46;2,590.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,594.16;62,594.16)|(62,594.46;2,594.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,596.16;62,596.16)|(62,596.46;2,596.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,542.16;62,542.16)|(62,542.46;2,542.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,606.16;62,606.16)|(62,606.46;2,606.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,608.16;62,608.16)|(62,608.46;2,608.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,610.16;62,610.16)|(62,610.46;2,610.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,706.16;62,706.16)|(62,706.46;2,706.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,692.16;62,692.16)|(62,692.46;2,692.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,612.16;62,612.16)|(62,612.46;2,612.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,614.16;62,614.16)|(62,614.46;2,614.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,522.16;62,522.16)|(62,522.46;2,522.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,526.16;62,526.16)|(62,526.46;2,526.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,734.16;62,734.16)|(62,734.46;2,734.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,528.16;62,528.16)|(62,528.46;2,528.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,598.16;62,598.16)|(62,598.46;2,598.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,500.16;62,500.16)|(62,500.46;2,500.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,718.16;62,718.16)|(62,718.46;2,718.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,634.16;62,634.16)|(62,634.46;2,634.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,534.16;62,534.16)|(62,534.46;2,534.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,538.16;62,538.16)|(62,538.46;2,538.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,618.16;62,618.16)|(62,618.46;2,618.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,622.16;62,622.16)|(62,622.46;2,622.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,540.16;62,540.16)|(62,540.46;2,540.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,624.16;62,624.16)|(62,624.46;2,624.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,626.16;62,626.16)|(62,626.46;2,626.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,530.16;62,530.16)|(62,530.46;2,530.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,512.16;62,512.16)|(62,512.46;2,512.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,628.16;62,628.16)|(62,628.46;2,628.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,524.16;62,524.16)|(62,524.46;2,524.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,642.16;62,642.16)|(62,642.46;2,642.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,600.16;62,600.16)|(62,600.46;2,600.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,516.16;62,516.16)|(62,516.46;2,516.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,630.16;62,630.16)|(62,630.46;2,630.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,632.16;62,632.16)|(62,632.46;2,632.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,496.16;62,496.16)|(62,496.46;2,496.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,640.16;62,640.16)|(62,640.46;2,640.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,687.5;62,687.5)|(62,688.46;2,688.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,592.16;62,592.16)|(62,592.46;2,592.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,712.16;62,712.16)|(62,712.46;2,712.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,690.16;62,690.16)|(62,690.46;2,690.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,730.16;62,730.16)|(62,730.46;2,730.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,498.16;62,498.16)|(62,498.46;2,498.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,604.16;62,604.16)|(62,604.46;2,604.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,532.16;62,532.16)|(62,532.46;2,532.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,536.16;62,536.16)|(62,536.46;2,536.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,587.5;62,587.5)|(62,588.46;2,588.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,726.16;62,726.16)|(62,726.46;2,726.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (2,716.16;62,716.16)|(62,716.46;2,716.46) 'CUP.3' chiptop_A_track false 1 edge-pair: (424.84,2;424.84,62)|(424.54,62;424.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (406.84,2;406.84,62)|(406.54,62;406.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (442.84,2;442.84,62)|(442.54,62;442.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (444.84,2;444.84,62)|(444.54,62;444.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (700.84,2;700.84,62)|(700.54,62;700.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (418.84,2;418.84,62)|(418.54,62;418.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (694.84,2;694.84,62)|(694.54,62;694.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (392.84,2;392.84,62)|(392.54,62;392.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (447.5,2;447.5,62)|(446.54,62;446.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (428.84,2;428.84,62)|(428.54,62;428.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (426.84,2;426.84,62)|(426.54,62;426.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (398.84,2;398.84,62)|(398.54,62;398.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (400.84,2;400.84,62)|(400.54,62;400.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (708.84,2;708.84,62)|(708.54,62;708.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (402.84,2;402.84,62)|(402.54,62;402.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (436.84,2;436.84,62)|(436.54,62;436.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (724.84,2;724.84,62)|(724.54,62;724.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (410.84,2;410.84,62)|(410.54,62;410.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (416.84,2;416.84,62)|(416.54,62;416.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (706.84,2;706.84,62)|(706.54,62;706.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (696.84,2;696.84,62)|(696.54,62;696.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (438.84,2;438.84,62)|(438.54,62;438.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (404.84,2;404.84,62)|(404.54,62;404.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (420.84,2;420.84,62)|(420.54,62;420.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (698.84,2;698.84,62)|(698.54,62;698.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (710.84,2;710.84,62)|(710.54,62;710.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (414.84,2;414.84,62)|(414.54,62;414.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (702.84,2;702.84,62)|(702.54,62;702.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (732.84,2;732.84,62)|(732.54,62;732.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (720.84,2;720.84,62)|(720.54,62;720.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (412.84,2;412.84,62)|(412.54,62;412.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (692.84,2;692.84,62)|(692.54,62;692.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (390.84,2;390.84,62)|(390.54,62;390.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (704.84,2;704.84,62)|(704.54,62;704.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (716.84,2;716.84,62)|(716.54,62;716.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (434.84,2;434.84,62)|(434.54,62;434.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (714.84,2;714.84,62)|(714.54,62;714.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (730.84,2;730.84,62)|(730.54,62;730.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (432.84,2;432.84,62)|(432.54,62;432.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (394.84,2;394.84,62)|(394.54,62;394.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (690.84,2;690.84,62)|(690.54,62;690.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (722.84,2;722.84,62)|(722.54,62;722.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (718.84,2;718.84,62)|(718.54,62;718.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (422.84,2;422.84,62)|(422.54,62;422.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (440.84,2;440.84,62)|(440.54,62;440.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (728.84,2;728.84,62)|(728.54,62;728.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (712.84,2;712.84,62)|(712.54,62;712.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (430.84,2;430.84,62)|(430.54,62;430.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (408.84,2;408.84,62)|(408.54,62;408.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (396.84,2;396.84,62)|(396.54,62;396.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (726.84,2;726.84,62)|(726.54,62;726.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (916.84,2;916.84,62)|(916.54,62;916.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (838.84,2;838.84,62)|(838.54,62;838.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (736.84,2;736.84,62)|(736.54,62;736.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (998.84,2;998.84,62)|(998.54,62;998.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (938.84,2;938.84,62)|(938.54,62;938.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (906.84,2;906.84,62)|(906.54,62;906.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1028.84,2;1028.84,62)|(1028.54,62;1028.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1034.84,2;1034.84,62)|(1034.54,62;1034.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1012.84,2;1012.84,62)|(1012.54,62;1012.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1030.84,2;1030.84,62)|(1030.54,62;1030.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (942.84,2;942.84,62)|(942.54,62;942.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (900.84,2;900.84,62)|(900.54,62;900.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (847.5,2;847.5,62)|(846.54,62;846.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (932.84,2;932.84,62)|(932.54,62;932.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (820.84,2;820.84,62)|(820.54,62;820.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (930.84,2;930.84,62)|(930.54,62;930.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (790.84,2;790.84,62)|(790.54,62;790.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (992.84,2;992.84,62)|(992.54,62;992.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (928.84,2;928.84,62)|(928.54,62;928.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1098.84,2;1098.84,62)|(1098.54,62;1098.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (996.84,2;996.84,62)|(996.54,62;996.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1026.84,2;1026.84,62)|(1026.54,62;1026.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1010.84,2;1010.84,62)|(1010.54,62;1010.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1006.84,2;1006.84,62)|(1006.54,62;1006.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1014.84,2;1014.84,62)|(1014.54,62;1014.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (804.84,2;804.84,62)|(804.54,62;804.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1036.84,2;1036.84,62)|(1036.54,62;1036.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (944.84,2;944.84,62)|(944.54,62;944.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (818.84,2;818.84,62)|(818.54,62;818.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (918.84,2;918.84,62)|(918.54,62;918.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (744.84,2;744.84,62)|(744.54,62;744.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1096.84,2;1096.84,62)|(1096.54,62;1096.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (934.84,2;934.84,62)|(934.54,62;934.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (940.84,2;940.84,62)|(940.54,62;940.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (826.84,2;826.84,62)|(826.54,62;826.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1092.84,2;1092.84,62)|(1092.54,62;1092.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (990.84,2;990.84,62)|(990.54,62;990.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (828.84,2;828.84,62)|(828.54,62;828.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (814.84,2;814.84,62)|(814.54,62;814.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (794.84,2;794.84,62)|(794.54,62;794.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (892.84,2;892.84,62)|(892.54,62;892.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1004.84,2;1004.84,62)|(1004.54,62;1004.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (844.84,2;844.84,62)|(844.54,62;844.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (908.84,2;908.84,62)|(908.54,62;908.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1040.84,2;1040.84,62)|(1040.54,62;1040.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (926.84,2;926.84,62)|(926.54,62;926.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1032.84,2;1032.84,62)|(1032.54,62;1032.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1020.84,2;1020.84,62)|(1020.54,62;1020.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (808.84,2;808.84,62)|(808.54,62;808.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (898.84,2;898.84,62)|(898.54,62;898.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (904.84,2;904.84,62)|(904.54,62;904.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (902.84,2;902.84,62)|(902.54,62;902.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1022.84,2;1022.84,62)|(1022.54,62;1022.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (936.84,2;936.84,62)|(936.54,62;936.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (816.84,2;816.84,62)|(816.54,62;816.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1042.84,2;1042.84,62)|(1042.54,62;1042.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (924.84,2;924.84,62)|(924.54,62;924.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (802.84,2;802.84,62)|(802.54,62;802.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (836.84,2;836.84,62)|(836.54,62;836.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (742.84,2;742.84,62)|(742.54,62;742.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (800.84,2;800.84,62)|(800.54,62;800.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (947.5,2;947.5,62)|(946.54,62;946.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (842.84,2;842.84,62)|(842.54,62;842.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (810.84,2;810.84,62)|(810.54,62;810.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (894.84,2;894.84,62)|(894.54,62;894.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (822.84,2;822.84,62)|(822.54,62;822.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1024.84,2;1024.84,62)|(1024.54,62;1024.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1047.5,2;1047.5,62)|(1046.54,62;1046.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1002.84,2;1002.84,62)|(1002.54,62;1002.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1038.84,2;1038.84,62)|(1038.54,62;1038.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (910.84,2;910.84,62)|(910.54,62;910.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (994.84,2;994.84,62)|(994.54,62;994.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (812.84,2;812.84,62)|(812.54,62;812.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (920.84,2;920.84,62)|(920.54,62;920.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1100.84,2;1100.84,62)|(1100.54,62;1100.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (792.84,2;792.84,62)|(792.54,62;792.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (824.84,2;824.84,62)|(824.54,62;824.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1018.84,2;1018.84,62)|(1018.54,62;1018.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (896.84,2;896.84,62)|(896.54,62;896.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (830.84,2;830.84,62)|(830.54,62;830.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1044.84,2;1044.84,62)|(1044.54,62;1044.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (890.84,2;890.84,62)|(890.54,62;890.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (832.84,2;832.84,62)|(832.54,62;832.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (834.84,2;834.84,62)|(834.54,62;834.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1008.84,2;1008.84,62)|(1008.54,62;1008.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (914.84,2;914.84,62)|(914.54,62;914.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (740.84,2;740.84,62)|(740.54,62;740.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (796.84,2;796.84,62)|(796.54,62;796.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (922.84,2;922.84,62)|(922.54,62;922.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (912.84,2;912.84,62)|(912.54,62;912.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (840.84,2;840.84,62)|(840.54,62;840.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1016.84,2;1016.84,62)|(1016.54,62;1016.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (798.84,2;798.84,62)|(798.54,62;798.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1094.84,2;1094.84,62)|(1094.54,62;1094.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (747.5,2;747.5,62)|(746.54,62;746.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (806.84,2;806.84,62)|(806.54,62;806.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1000.84,2;1000.84,62)|(1000.54,62;1000.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1090.84,2;1090.84,62)|(1090.54,62;1090.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (738.84,2;738.84,62)|(738.54,62;738.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1190.84,2;1190.84,62)|(1190.54,62;1190.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1104.84,2;1104.84,62)|(1104.54,62;1104.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1230.84,2;1230.84,62)|(1230.54,62;1230.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1224.84,2;1224.84,62)|(1224.54,62;1224.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1238.84,2;1238.84,62)|(1238.54,62;1238.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1138.84,2;1138.84,62)|(1138.54,62;1138.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1144.84,2;1144.84,62)|(1144.54,62;1144.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1106.84,2;1106.84,62)|(1106.54,62;1106.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1116.84,2;1116.84,62)|(1116.54,62;1116.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1102.84,2;1102.84,62)|(1102.54,62;1102.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1234.84,2;1234.84,62)|(1234.54,62;1234.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1194.84,2;1194.84,62)|(1194.54,62;1194.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1222.84,2;1222.84,62)|(1222.54,62;1222.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1240.84,2;1240.84,62)|(1240.54,62;1240.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1124.84,2;1124.84,62)|(1124.54,62;1124.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1142.84,2;1142.84,62)|(1142.54,62;1142.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1192.84,2;1192.84,62)|(1192.54,62;1192.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1147.5,2;1147.5,62)|(1146.54,62;1146.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1214.84,2;1214.84,62)|(1214.54,62;1214.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1226.84,2;1226.84,62)|(1226.54,62;1226.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1198.84,2;1198.84,62)|(1198.54,62;1198.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1134.84,2;1134.84,62)|(1134.54,62;1134.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1204.84,2;1204.84,62)|(1204.54,62;1204.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1236.84,2;1236.84,62)|(1236.54,62;1236.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1118.84,2;1118.84,62)|(1118.54,62;1118.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1132.84,2;1132.84,62)|(1132.54,62;1132.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1206.84,2;1206.84,62)|(1206.54,62;1206.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1242.84,2;1242.84,62)|(1242.54,62;1242.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1126.84,2;1126.84,62)|(1126.54,62;1126.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1208.84,2;1208.84,62)|(1208.54,62;1208.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1212.84,2;1212.84,62)|(1212.54,62;1212.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1128.84,2;1128.84,62)|(1128.54,62;1128.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1244.84,2;1244.84,62)|(1244.54,62;1244.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1202.84,2;1202.84,62)|(1202.54,62;1202.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1218.84,2;1218.84,62)|(1218.54,62;1218.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1130.84,2;1130.84,62)|(1130.54,62;1130.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1196.84,2;1196.84,62)|(1196.54,62;1196.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1136.84,2;1136.84,62)|(1136.54,62;1136.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1232.84,2;1232.84,62)|(1232.54,62;1232.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1200.84,2;1200.84,62)|(1200.54,62;1200.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1120.84,2;1120.84,62)|(1120.54,62;1120.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1140.84,2;1140.84,62)|(1140.54,62;1140.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1210.84,2;1210.84,62)|(1210.54,62;1210.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1216.84,2;1216.84,62)|(1216.54,62;1216.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1228.84,2;1228.84,62)|(1228.54,62;1228.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1122.84,2;1122.84,62)|(1122.54,62;1122.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1108.84,2;1108.84,62)|(1108.54,62;1108.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1114.84,2;1114.84,62)|(1114.54,62;1114.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1110.84,2;1110.84,62)|(1110.54,62;1110.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1220.84,2;1220.84,62)|(1220.54,62;1220.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1112.84,2;1112.84,62)|(1112.54,62;1112.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1247.5,2;1247.5,62)|(1246.54,62;1246.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1318.84,2;1318.84,62)|(1318.54,62;1318.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1442.84,2;1442.84,62)|(1442.54,62;1442.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1306.84,2;1306.84,62)|(1306.54,62;1306.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1330.84,2;1330.84,62)|(1330.54,62;1330.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1294.84,2;1294.84,62)|(1294.54,62;1294.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1322.84,2;1322.84,62)|(1322.54,62;1322.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1292.84,2;1292.84,62)|(1292.54,62;1292.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1347.5,2;1347.5,62)|(1346.54,62;1346.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1334.84,2;1334.84,62)|(1334.54,62;1334.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1410.84,2;1410.84,62)|(1410.54,62;1410.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1414.84,2;1414.84,62)|(1414.54,62;1414.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1392.84,2;1392.84,62)|(1392.54,62;1392.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1310.84,2;1310.84,62)|(1310.54,62;1310.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1398.84,2;1398.84,62)|(1398.54,62;1398.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1336.84,2;1336.84,62)|(1336.54,62;1336.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1302.84,2;1302.84,62)|(1302.54,62;1302.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1394.84,2;1394.84,62)|(1394.54,62;1394.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1408.84,2;1408.84,62)|(1408.54,62;1408.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1314.84,2;1314.84,62)|(1314.54,62;1314.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1328.84,2;1328.84,62)|(1328.54,62;1328.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1298.84,2;1298.84,62)|(1298.54,62;1298.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1308.84,2;1308.84,62)|(1308.54,62;1308.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1332.84,2;1332.84,62)|(1332.54,62;1332.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1390.84,2;1390.84,62)|(1390.54,62;1390.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1320.84,2;1320.84,62)|(1320.54,62;1320.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1422.84,2;1422.84,62)|(1422.54,62;1422.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1420.84,2;1420.84,62)|(1420.54,62;1420.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1402.84,2;1402.84,62)|(1402.54,62;1402.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1434.84,2;1434.84,62)|(1434.54,62;1434.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1340.84,2;1340.84,62)|(1340.54,62;1340.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1290.84,2;1290.84,62)|(1290.54,62;1290.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1426.84,2;1426.84,62)|(1426.54,62;1426.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1406.84,2;1406.84,62)|(1406.54,62;1406.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1396.84,2;1396.84,62)|(1396.54,62;1396.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1428.84,2;1428.84,62)|(1428.54,62;1428.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1344.84,2;1344.84,62)|(1344.54,62;1344.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1432.84,2;1432.84,62)|(1432.54,62;1432.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1312.84,2;1312.84,62)|(1312.54,62;1312.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1338.84,2;1338.84,62)|(1338.54,62;1338.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1447.5,2;1447.5,62)|(1446.54,62;1446.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1400.84,2;1400.84,62)|(1400.54,62;1400.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1438.84,2;1438.84,62)|(1438.54,62;1438.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1326.84,2;1326.84,62)|(1326.54,62;1326.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1412.84,2;1412.84,62)|(1412.54,62;1412.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1404.84,2;1404.84,62)|(1404.54,62;1404.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1424.84,2;1424.84,62)|(1424.54,62;1424.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1444.84,2;1444.84,62)|(1444.54,62;1444.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1342.84,2;1342.84,62)|(1342.54,62;1342.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1436.84,2;1436.84,62)|(1436.54,62;1436.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1416.84,2;1416.84,62)|(1416.54,62;1416.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1296.84,2;1296.84,62)|(1296.54,62;1296.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1304.84,2;1304.84,62)|(1304.54,62;1304.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1324.84,2;1324.84,62)|(1324.54,62;1324.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1440.84,2;1440.84,62)|(1440.54,62;1440.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1316.84,2;1316.84,62)|(1316.54,62;1316.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1430.84,2;1430.84,62)|(1430.54,62;1430.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1300.84,2;1300.84,62)|(1300.54,62;1300.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1418.84,2;1418.84,62)|(1418.54,62;1418.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,734.54;2933,734.54)|(2933,734.84;2873,734.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1416.54;2933,1416.54)|(2933,1416.84;2873,1416.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1420.54;2933,1420.54)|(2933,1420.84;2873,1420.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1246.54;2933,1246.54)|(2933,1247.5;2873,1247.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1190.54;2933,1190.54)|(2933,1190.84;2873,1190.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1320.54;2933,1320.54)|(2933,1320.84;2873,1320.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1214.54;2933,1214.54)|(2933,1214.84;2873,1214.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1312.54;2933,1312.54)|(2933,1312.84;2873,1312.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1306.54;2933,1306.54)|(2933,1306.84;2873,1306.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1436.54;2933,1436.54)|(2933,1436.84;2873,1436.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1446.54;2933,1446.54)|(2933,1447.5;2873,1447.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1408.54;2933,1408.54)|(2933,1408.84;2873,1408.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1208.54;2933,1208.54)|(2933,1208.84;2873,1208.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1236.54;2933,1236.54)|(2933,1236.84;2873,1236.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1344.54;2933,1344.54)|(2933,1344.84;2873,1344.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1202.54;2933,1202.54)|(2933,1202.84;2873,1202.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1422.54;2933,1422.54)|(2933,1422.84;2873,1422.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1304.54;2933,1304.54)|(2933,1304.84;2873,1304.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1204.54;2933,1204.54)|(2933,1204.84;2873,1204.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1432.54;2933,1432.54)|(2933,1432.84;2873,1432.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1216.54;2933,1216.54)|(2933,1216.84;2873,1216.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1342.54;2933,1342.54)|(2933,1342.84;2873,1342.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1318.54;2933,1318.54)|(2933,1318.84;2873,1318.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1322.54;2933,1322.54)|(2933,1322.84;2873,1322.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1326.54;2933,1326.54)|(2933,1326.84;2873,1326.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1220.54;2933,1220.54)|(2933,1220.84;2873,1220.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1316.54;2933,1316.54)|(2933,1316.84;2873,1316.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1302.54;2933,1302.54)|(2933,1302.84;2873,1302.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1244.54;2933,1244.54)|(2933,1244.84;2873,1244.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1308.54;2933,1308.54)|(2933,1308.84;2873,1308.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1430.54;2933,1430.54)|(2933,1430.84;2873,1430.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1200.54;2933,1200.54)|(2933,1200.84;2873,1200.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1192.54;2933,1192.54)|(2933,1192.84;2873,1192.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1434.54;2933,1434.54)|(2933,1434.84;2873,1434.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1242.54;2933,1242.54)|(2933,1242.84;2873,1242.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1346.54;2933,1346.54)|(2933,1347.5;2873,1347.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1338.54;2933,1338.54)|(2933,1338.84;2873,1338.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1414.54;2933,1414.54)|(2933,1414.84;2873,1414.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1240.54;2933,1240.54)|(2933,1240.84;2873,1240.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1442.54;2933,1442.54)|(2933,1442.84;2873,1442.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1324.54;2933,1324.54)|(2933,1324.84;2873,1324.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1428.54;2933,1428.54)|(2933,1428.84;2873,1428.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1404.54;2933,1404.54)|(2933,1404.84;2873,1404.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1206.54;2933,1206.54)|(2933,1206.84;2873,1206.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1406.54;2933,1406.54)|(2933,1406.84;2873,1406.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1210.54;2933,1210.54)|(2933,1210.84;2873,1210.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1212.54;2933,1212.54)|(2933,1212.84;2873,1212.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1198.54;2933,1198.54)|(2933,1198.84;2873,1198.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1196.54;2933,1196.54)|(2933,1196.84;2873,1196.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1194.54;2933,1194.54)|(2933,1194.84;2873,1194.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1402.54;2933,1402.54)|(2933,1402.84;2873,1402.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1400.54;2933,1400.54)|(2933,1400.84;2873,1400.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1398.54;2933,1398.54)|(2933,1398.84;2873,1398.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1300.54;2933,1300.54)|(2933,1300.84;2873,1300.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1396.54;2933,1396.54)|(2933,1396.84;2873,1396.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1394.54;2933,1394.54)|(2933,1394.84;2873,1394.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1392.54;2933,1392.54)|(2933,1392.84;2873,1392.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1340.54;2933,1340.54)|(2933,1340.84;2873,1340.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1336.54;2933,1336.54)|(2933,1336.84;2873,1336.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1330.54;2933,1330.54)|(2933,1330.84;2873,1330.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1426.54;2933,1426.54)|(2933,1426.84;2873,1426.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1444.54;2933,1444.54)|(2933,1444.84;2873,1444.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1440.54;2933,1440.54)|(2933,1440.84;2873,1440.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1438.54;2933,1438.54)|(2933,1438.84;2873,1438.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1328.54;2933,1328.54)|(2933,1328.84;2873,1328.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1424.54;2933,1424.54)|(2933,1424.84;2873,1424.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1418.54;2933,1418.54)|(2933,1418.84;2873,1418.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1412.54;2933,1412.54)|(2933,1412.84;2873,1412.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1410.54;2933,1410.54)|(2933,1410.84;2873,1410.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1230.54;2933,1230.54)|(2933,1230.84;2873,1230.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1238.54;2933,1238.54)|(2933,1238.84;2873,1238.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1234.54;2933,1234.54)|(2933,1234.84;2873,1234.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1232.54;2933,1232.54)|(2933,1232.84;2873,1232.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1292.54;2933,1292.54)|(2933,1292.84;2873,1292.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1228.54;2933,1228.54)|(2933,1228.84;2873,1228.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1226.54;2933,1226.54)|(2933,1226.84;2873,1226.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1224.54;2933,1224.54)|(2933,1224.84;2873,1224.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1222.54;2933,1222.54)|(2933,1222.84;2873,1222.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1218.54;2933,1218.54)|(2933,1218.84;2873,1218.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1310.54;2933,1310.54)|(2933,1310.84;2873,1310.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1298.54;2933,1298.54)|(2933,1298.84;2873,1298.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1296.54;2933,1296.54)|(2933,1296.84;2873,1296.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1390.54;2933,1390.54)|(2933,1390.84;2873,1390.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1290.54;2933,1290.54)|(2933,1290.84;2873,1290.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1332.54;2933,1332.54)|(2933,1332.84;2873,1332.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1294.54;2933,1294.54)|(2933,1294.84;2873,1294.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1314.54;2933,1314.54)|(2933,1314.84;2873,1314.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1334.54;2933,1334.54)|(2933,1334.84;2873,1334.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,840.54;2933,840.54)|(2933,840.84;2873,840.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1012.54;2933,1012.54)|(2933,1012.84;2873,1012.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,836.54;2933,836.54)|(2933,836.84;2873,836.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,796.54;2933,796.54)|(2933,796.84;2873,796.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,906.54;2933,906.54)|(2933,906.84;2873,906.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,908.54;2933,908.54)|(2933,908.84;2873,908.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1040.54;2933,1040.54)|(2933,1040.84;2873,1040.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,844.54;2933,844.54)|(2933,844.84;2873,844.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,918.54;2933,918.54)|(2933,918.84;2873,918.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,924.54;2933,924.54)|(2933,924.84;2873,924.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1030.54;2933,1030.54)|(2933,1030.84;2873,1030.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,792.54;2933,792.54)|(2933,792.84;2873,792.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1010.54;2933,1010.54)|(2933,1010.84;2873,1010.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,910.54;2933,910.54)|(2933,910.84;2873,910.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,806.54;2933,806.54)|(2933,806.84;2873,806.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,800.54;2933,800.54)|(2933,800.84;2873,800.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,930.54;2933,930.54)|(2933,930.84;2873,930.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,798.54;2933,798.54)|(2933,798.84;2873,798.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,936.54;2933,936.54)|(2933,936.84;2873,936.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1046.54;2933,1046.54)|(2933,1047.5;2873,1047.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1020.54;2933,1020.54)|(2933,1020.84;2873,1020.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,738.54;2933,738.54)|(2933,738.84;2873,738.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,740.54;2933,740.54)|(2933,740.84;2873,740.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,998.54;2933,998.54)|(2933,998.84;2873,998.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1006.54;2933,1006.54)|(2933,1006.84;2873,1006.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1042.54;2933,1042.54)|(2933,1042.84;2873,1042.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,896.54;2933,896.54)|(2933,896.84;2873,896.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,990.54;2933,990.54)|(2933,990.84;2873,990.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,898.54;2933,898.54)|(2933,898.84;2873,898.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,742.54;2933,742.54)|(2933,742.84;2873,742.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,894.54;2933,894.54)|(2933,894.84;2873,894.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,808.54;2933,808.54)|(2933,808.84;2873,808.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,946.54;2933,946.54)|(2933,947.5;2873,947.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,828.54;2933,828.54)|(2933,828.84;2873,828.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,996.54;2933,996.54)|(2933,996.84;2873,996.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,902.54;2933,902.54)|(2933,902.84;2873,902.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,744.54;2933,744.54)|(2933,744.84;2873,744.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,814.54;2933,814.54)|(2933,814.84;2873,814.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1028.54;2933,1028.54)|(2933,1028.84;2873,1028.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,818.54;2933,818.54)|(2933,818.84;2873,818.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1032.54;2933,1032.54)|(2933,1032.84;2873,1032.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,816.54;2933,816.54)|(2933,816.84;2873,816.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,820.54;2933,820.54)|(2933,820.84;2873,820.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,994.54;2933,994.54)|(2933,994.84;2873,994.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,826.54;2933,826.54)|(2933,826.84;2873,826.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,746.54;2933,746.54)|(2933,747.5;2873,747.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1026.54;2933,1026.54)|(2933,1026.84;2873,1026.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,938.54;2933,938.54)|(2933,938.84;2873,938.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1000.54;2933,1000.54)|(2933,1000.84;2873,1000.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,992.54;2933,992.54)|(2933,992.84;2873,992.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,944.54;2933,944.54)|(2933,944.84;2873,944.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,934.54;2933,934.54)|(2933,934.84;2873,934.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,932.54;2933,932.54)|(2933,932.84;2873,932.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,846.54;2933,846.54)|(2933,847.5;2873,847.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,928.54;2933,928.54)|(2933,928.84;2873,928.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,926.54;2933,926.54)|(2933,926.84;2873,926.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,922.54;2933,922.54)|(2933,922.84;2873,922.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,920.54;2933,920.54)|(2933,920.84;2873,920.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1024.54;2933,1024.54)|(2933,1024.84;2873,1024.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1044.54;2933,1044.54)|(2933,1044.84;2873,1044.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1038.54;2933,1038.54)|(2933,1038.84;2873,1038.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1034.54;2933,1034.54)|(2933,1034.84;2873,1034.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,916.54;2933,916.54)|(2933,916.84;2873,916.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1022.54;2933,1022.54)|(2933,1022.84;2873,1022.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1018.54;2933,1018.54)|(2933,1018.84;2873,1018.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1016.54;2933,1016.54)|(2933,1016.84;2873,1016.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1014.54;2933,1014.54)|(2933,1014.84;2873,1014.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1008.54;2933,1008.54)|(2933,1008.84;2873,1008.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,790.54;2933,790.54)|(2933,790.84;2873,790.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1004.54;2933,1004.54)|(2933,1004.84;2873,1004.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,810.54;2933,810.54)|(2933,810.84;2873,810.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1036.54;2933,1036.54)|(2933,1036.84;2873,1036.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,830.54;2933,830.54)|(2933,830.84;2873,830.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,824.54;2933,824.54)|(2933,824.84;2873,824.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,822.54;2933,822.54)|(2933,822.84;2873,822.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,812.54;2933,812.54)|(2933,812.84;2873,812.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,832.54;2933,832.54)|(2933,832.84;2873,832.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,804.54;2933,804.54)|(2933,804.84;2873,804.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,802.54;2933,802.54)|(2933,802.84;2873,802.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,794.54;2933,794.54)|(2933,794.84;2873,794.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,914.54;2933,914.54)|(2933,914.84;2873,914.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,912.54;2933,912.54)|(2933,912.84;2873,912.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,904.54;2933,904.54)|(2933,904.84;2873,904.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,900.54;2933,900.54)|(2933,900.84;2873,900.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,940.54;2933,940.54)|(2933,940.84;2873,940.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,736.54;2933,736.54)|(2933,736.84;2873,736.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,892.54;2933,892.54)|(2933,892.84;2873,892.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,890.54;2933,890.54)|(2933,890.84;2873,890.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,842.54;2933,842.54)|(2933,842.84;2873,842.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,1002.54;2933,1002.54)|(2933,1002.84;2873,1002.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,838.54;2933,838.54)|(2933,838.84;2873,838.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,834.54;2933,834.54)|(2933,834.84;2873,834.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,942.54;2933,942.54)|(2933,942.84;2873,942.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (1642.84,2;1642.84,62)|(1642.54,62;1642.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1644.84,2;1644.84,62)|(1644.54,62;1644.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1606.84,2;1606.84,62)|(1606.54,62;1606.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1604.84,2;1604.84,62)|(1604.54,62;1604.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1526.84,2;1526.84,62)|(1526.54,62;1526.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1594.84,2;1594.84,62)|(1594.54,62;1594.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1544.84,2;1544.84,62)|(1544.54,62;1544.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1600.84,2;1600.84,62)|(1600.54,62;1600.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1534.84,2;1534.84,62)|(1534.54,62;1534.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1492.84,2;1492.84,62)|(1492.54,62;1492.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1532.84,2;1532.84,62)|(1532.54,62;1532.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1630.84,2;1630.84,62)|(1630.54,62;1630.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1494.84,2;1494.84,62)|(1494.54,62;1494.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1490.84,2;1490.84,62)|(1490.54,62;1490.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1616.84,2;1616.84,62)|(1616.54,62;1616.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1504.84,2;1504.84,62)|(1504.54,62;1504.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1620.84,2;1620.84,62)|(1620.54,62;1620.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1538.84,2;1538.84,62)|(1538.54,62;1538.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1602.84,2;1602.84,62)|(1602.54,62;1602.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1540.84,2;1540.84,62)|(1540.54,62;1540.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1520.84,2;1520.84,62)|(1520.54,62;1520.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1518.84,2;1518.84,62)|(1518.54,62;1518.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1542.84,2;1542.84,62)|(1542.54,62;1542.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1634.84,2;1634.84,62)|(1634.54,62;1634.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1590.84,2;1590.84,62)|(1590.54,62;1590.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1512.84,2;1512.84,62)|(1512.54,62;1512.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1516.84,2;1516.84,62)|(1516.54,62;1516.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1536.84,2;1536.84,62)|(1536.54,62;1536.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1530.84,2;1530.84,62)|(1530.54,62;1530.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1514.84,2;1514.84,62)|(1514.54,62;1514.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1596.84,2;1596.84,62)|(1596.54,62;1596.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1502.84,2;1502.84,62)|(1502.54,62;1502.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1510.84,2;1510.84,62)|(1510.54,62;1510.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1626.84,2;1626.84,62)|(1626.54,62;1626.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1632.84,2;1632.84,62)|(1632.54,62;1632.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1508.84,2;1508.84,62)|(1508.54,62;1508.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1500.84,2;1500.84,62)|(1500.54,62;1500.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1624.84,2;1624.84,62)|(1624.54,62;1624.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1628.84,2;1628.84,62)|(1628.54,62;1628.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1592.84,2;1592.84,62)|(1592.54,62;1592.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1524.84,2;1524.84,62)|(1524.54,62;1524.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1598.84,2;1598.84,62)|(1598.54,62;1598.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1608.84,2;1608.84,62)|(1608.54,62;1608.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1647.5,2;1647.5,62)|(1646.54,62;1646.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1618.84,2;1618.84,62)|(1618.54,62;1618.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1638.84,2;1638.84,62)|(1638.54,62;1638.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1528.84,2;1528.84,62)|(1528.54,62;1528.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1610.84,2;1610.84,62)|(1610.54,62;1610.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1640.84,2;1640.84,62)|(1640.54,62;1640.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1622.84,2;1622.84,62)|(1622.54,62;1622.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1614.84,2;1614.84,62)|(1614.54,62;1614.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1498.84,2;1498.84,62)|(1498.54,62;1498.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1547.5,2;1547.5,62)|(1546.54,62;1546.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1506.84,2;1506.84,62)|(1506.54,62;1506.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1636.84,2;1636.84,62)|(1636.54,62;1636.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1612.84,2;1612.84,62)|(1612.54,62;1612.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1496.84,2;1496.84,62)|(1496.54,62;1496.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1522.84,2;1522.84,62)|(1522.54,62;1522.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1724.84,2;1724.84,62)|(1724.54,62;1724.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1742.84,2;1742.84,62)|(1742.54,62;1742.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1802.84,2;1802.84,62)|(1802.54,62;1802.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1814.84,2;1814.84,62)|(1814.54,62;1814.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1738.84,2;1738.84,62)|(1738.54,62;1738.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1818.84,2;1818.84,62)|(1818.54,62;1818.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1718.84,2;1718.84,62)|(1718.54,62;1718.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1804.84,2;1804.84,62)|(1804.54,62;1804.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1828.84,2;1828.84,62)|(1828.54,62;1828.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1800.84,2;1800.84,62)|(1800.54,62;1800.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1820.84,2;1820.84,62)|(1820.54,62;1820.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1702.84,2;1702.84,62)|(1702.54,62;1702.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1728.84,2;1728.84,62)|(1728.54,62;1728.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1794.84,2;1794.84,62)|(1794.54,62;1794.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1716.84,2;1716.84,62)|(1716.54,62;1716.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1698.84,2;1698.84,62)|(1698.54,62;1698.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1826.84,2;1826.84,62)|(1826.54,62;1826.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1747.5,2;1747.5,62)|(1746.54,62;1746.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1708.84,2;1708.84,62)|(1708.54,62;1708.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1712.84,2;1712.84,62)|(1712.54,62;1712.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1806.84,2;1806.84,62)|(1806.54,62;1806.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1694.84,2;1694.84,62)|(1694.54,62;1694.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1726.84,2;1726.84,62)|(1726.54,62;1726.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1790.84,2;1790.84,62)|(1790.54,62;1790.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1706.84,2;1706.84,62)|(1706.54,62;1706.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1808.84,2;1808.84,62)|(1808.54,62;1808.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1730.84,2;1730.84,62)|(1730.54,62;1730.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1810.84,2;1810.84,62)|(1810.54,62;1810.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1822.84,2;1822.84,62)|(1822.54,62;1822.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1740.84,2;1740.84,62)|(1740.54,62;1740.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1812.84,2;1812.84,62)|(1812.54,62;1812.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1744.84,2;1744.84,62)|(1744.54,62;1744.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1722.84,2;1722.84,62)|(1722.54,62;1722.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1732.84,2;1732.84,62)|(1732.54,62;1732.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1796.84,2;1796.84,62)|(1796.54,62;1796.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1704.84,2;1704.84,62)|(1704.54,62;1704.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1832.84,2;1832.84,62)|(1832.54,62;1832.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1692.84,2;1692.84,62)|(1692.54,62;1692.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1824.84,2;1824.84,62)|(1824.54,62;1824.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1690.84,2;1690.84,62)|(1690.54,62;1690.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1830.84,2;1830.84,62)|(1830.54,62;1830.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1736.84,2;1736.84,62)|(1736.54,62;1736.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1714.84,2;1714.84,62)|(1714.54,62;1714.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1710.84,2;1710.84,62)|(1710.54,62;1710.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1792.84,2;1792.84,62)|(1792.54,62;1792.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1816.84,2;1816.84,62)|(1816.54,62;1816.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1798.84,2;1798.84,62)|(1798.54,62;1798.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1720.84,2;1720.84,62)|(1720.54,62;1720.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1700.84,2;1700.84,62)|(1700.54,62;1700.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1696.84,2;1696.84,62)|(1696.54,62;1696.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1734.84,2;1734.84,62)|(1734.54,62;1734.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2116.84,2;2116.84,62)|(2116.54,62;2116.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1842.84,2;1842.84,62)|(1842.54,62;1842.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2047.5,2;2047.5,62)|(2046.54,62;2046.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2030.84,2;2030.84,62)|(2030.54,62;2030.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2126.84,2;2126.84,62)|(2126.54,62;2126.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2128.84,2;2128.84,62)|(2128.54,62;2128.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1994.84,2;1994.84,62)|(1994.54,62;1994.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2038.84,2;2038.84,62)|(2038.54,62;2038.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2016.84,2;2016.84,62)|(2016.54,62;2016.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2098.84,2;2098.84,62)|(2098.54,62;2098.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2106.84,2;2106.84,62)|(2106.54,62;2106.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2122.84,2;2122.84,62)|(2122.54,62;2122.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2102.84,2;2102.84,62)|(2102.54,62;2102.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2124.84,2;2124.84,62)|(2124.54,62;2124.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2198.84,2;2198.84,62)|(2198.54,62;2198.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2024.84,2;2024.84,62)|(2024.54,62;2024.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2120.84,2;2120.84,62)|(2120.54,62;2120.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2028.84,2;2028.84,62)|(2028.54,62;2028.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1838.84,2;1838.84,62)|(1838.54,62;1838.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2006.84,2;2006.84,62)|(2006.54,62;2006.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2138.84,2;2138.84,62)|(2138.54,62;2138.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2092.84,2;2092.84,62)|(2092.54,62;2092.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2100.84,2;2100.84,62)|(2100.54,62;2100.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2022.84,2;2022.84,62)|(2022.54,62;2022.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2008.84,2;2008.84,62)|(2008.54,62;2008.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2134.84,2;2134.84,62)|(2134.54,62;2134.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2014.84,2;2014.84,62)|(2014.54,62;2014.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2144.84,2;2144.84,62)|(2144.54,62;2144.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1844.84,2;1844.84,62)|(1844.54,62;1844.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2032.84,2;2032.84,62)|(2032.54,62;2032.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2136.84,2;2136.84,62)|(2136.54,62;2136.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2142.84,2;2142.84,62)|(2142.54,62;2142.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2004.84,2;2004.84,62)|(2004.54,62;2004.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1998.84,2;1998.84,62)|(1998.54,62;1998.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2196.84,2;2196.84,62)|(2196.54,62;2196.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2010.84,2;2010.84,62)|(2010.54,62;2010.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2112.84,2;2112.84,62)|(2112.54,62;2112.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2132.84,2;2132.84,62)|(2132.54,62;2132.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2094.84,2;2094.84,62)|(2094.54,62;2094.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2140.84,2;2140.84,62)|(2140.54,62;2140.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1836.84,2;1836.84,62)|(1836.54,62;1836.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2020.84,2;2020.84,62)|(2020.54,62;2020.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1847.5,2;1847.5,62)|(1846.54,62;1846.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2042.84,2;2042.84,62)|(2042.54,62;2042.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1834.84,2;1834.84,62)|(1834.54,62;1834.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1840.84,2;1840.84,62)|(1840.54,62;1840.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2002.84,2;2002.84,62)|(2002.54,62;2002.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1992.84,2;1992.84,62)|(1992.54,62;1992.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2026.84,2;2026.84,62)|(2026.54,62;2026.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2108.84,2;2108.84,62)|(2108.54,62;2108.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2044.84,2;2044.84,62)|(2044.54,62;2044.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2130.84,2;2130.84,62)|(2130.54,62;2130.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2096.84,2;2096.84,62)|(2096.54,62;2096.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2040.84,2;2040.84,62)|(2040.54,62;2040.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1990.84,2;1990.84,62)|(1990.54,62;1990.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2190.84,2;2190.84,62)|(2190.54,62;2190.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2110.84,2;2110.84,62)|(2110.54,62;2110.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2012.84,2;2012.84,62)|(2012.54,62;2012.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2192.84,2;2192.84,62)|(2192.54,62;2192.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2114.84,2;2114.84,62)|(2114.54,62;2114.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2194.84,2;2194.84,62)|(2194.54,62;2194.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2147.5,2;2147.5,62)|(2146.54,62;2146.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2104.84,2;2104.84,62)|(2104.54,62;2104.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2090.84,2;2090.84,62)|(2090.54,62;2090.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2036.84,2;2036.84,62)|(2036.54,62;2036.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2118.84,2;2118.84,62)|(2118.54,62;2118.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2034.84,2;2034.84,62)|(2034.54,62;2034.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2000.84,2;2000.84,62)|(2000.54,62;2000.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2018.84,2;2018.84,62)|(2018.54,62;2018.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (1996.84,2;1996.84,62)|(1996.54,62;1996.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,530.54;2933,530.54)|(2933,530.84;2873,530.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,540.54;2933,540.54)|(2933,540.84;2873,540.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,722.54;2933,722.54)|(2933,722.84;2873,722.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,414.54;2933,414.54)|(2933,414.84;2873,414.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,404.54;2933,404.54)|(2933,404.84;2873,404.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,412.54;2933,412.54)|(2933,412.84;2873,412.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,402.54;2933,402.54)|(2933,402.84;2873,402.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,432.54;2933,432.54)|(2933,432.84;2873,432.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,532.54;2933,532.54)|(2933,532.84;2873,532.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,728.54;2933,728.54)|(2933,728.84;2873,728.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,528.54;2933,528.54)|(2933,528.84;2873,528.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,498.54;2933,498.54)|(2933,498.84;2873,498.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,442.54;2933,442.54)|(2933,442.84;2873,442.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,698.54;2933,698.54)|(2933,698.84;2873,698.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,696.54;2933,696.54)|(2933,696.84;2873,696.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,694.54;2933,694.54)|(2933,694.84;2873,694.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,692.54;2933,692.54)|(2933,692.84;2873,692.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,546.54;2933,546.54)|(2933,547.5;2873,547.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,544.54;2933,544.54)|(2933,544.84;2873,544.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,536.54;2933,536.54)|(2933,536.84;2873,536.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,500.54;2933,500.54)|(2933,500.84;2873,500.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,534.54;2933,534.54)|(2933,534.84;2873,534.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,522.54;2933,522.54)|(2933,522.84;2873,522.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,520.54;2933,520.54)|(2933,520.84;2873,520.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,700.54;2933,700.54)|(2933,700.84;2873,700.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,418.54;2933,418.54)|(2933,418.84;2873,418.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,726.54;2933,726.54)|(2933,726.84;2873,726.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,720.54;2933,720.54)|(2933,720.84;2873,720.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,716.54;2933,716.54)|(2933,716.84;2873,716.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,712.54;2933,712.54)|(2933,712.84;2873,712.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,708.54;2933,708.54)|(2933,708.84;2873,708.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,706.54;2933,706.54)|(2933,706.84;2873,706.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,410.54;2933,410.54)|(2933,410.84;2873,410.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,430.54;2933,430.54)|(2933,430.84;2873,430.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,422.54;2933,422.54)|(2933,422.84;2873,422.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,420.54;2933,420.54)|(2933,420.84;2873,420.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,416.54;2933,416.54)|(2933,416.84;2873,416.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,408.54;2933,408.54)|(2933,408.84;2873,408.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,406.54;2933,406.54)|(2933,406.84;2873,406.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,400.54;2933,400.54)|(2933,400.84;2873,400.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,428.54;2933,428.54)|(2933,428.84;2873,428.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,398.54;2933,398.54)|(2933,398.84;2873,398.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,394.54;2933,394.54)|(2933,394.84;2873,394.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,392.54;2933,392.54)|(2933,392.84;2873,392.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,390.54;2933,390.54)|(2933,390.84;2873,390.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,516.54;2933,516.54)|(2933,516.84;2873,516.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,512.54;2933,512.54)|(2933,512.84;2873,512.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,508.54;2933,508.54)|(2933,508.84;2873,508.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,506.54;2933,506.54)|(2933,506.84;2873,506.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,524.54;2933,524.54)|(2933,524.84;2873,524.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,426.54;2933,426.54)|(2933,426.84;2873,426.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,504.54;2933,504.54)|(2933,504.84;2873,504.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,496.54;2933,496.54)|(2933,496.84;2873,496.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,490.54;2933,490.54)|(2933,490.84;2873,490.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,444.54;2933,444.54)|(2933,444.84;2873,444.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,440.54;2933,440.54)|(2933,440.84;2873,440.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,690.54;2933,690.54)|(2933,690.84;2873,690.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,436.54;2933,436.54)|(2933,436.84;2873,436.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,702.54;2933,702.54)|(2933,702.84;2873,702.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,434.54;2933,434.54)|(2933,434.84;2873,434.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,446.54;2933,446.54)|(2933,447.5;2873,447.5) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,494.54;2933,494.54)|(2933,494.84;2873,494.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,424.54;2933,424.54)|(2933,424.84;2873,424.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,538.54;2933,538.54)|(2933,538.84;2873,538.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,714.54;2933,714.54)|(2933,714.84;2873,714.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,518.54;2933,518.54)|(2933,518.84;2873,518.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,718.54;2933,718.54)|(2933,718.84;2873,718.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,710.54;2933,710.54)|(2933,710.84;2873,710.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,510.54;2933,510.54)|(2933,510.84;2873,510.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,724.54;2933,724.54)|(2933,724.84;2873,724.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,732.54;2933,732.54)|(2933,732.84;2873,732.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,502.54;2933,502.54)|(2933,502.84;2873,502.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,514.54;2933,514.54)|(2933,514.84;2873,514.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,704.54;2933,704.54)|(2933,704.84;2873,704.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,492.54;2933,492.54)|(2933,492.84;2873,492.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,438.54;2933,438.54)|(2933,438.84;2873,438.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,396.54;2933,396.54)|(2933,396.84;2873,396.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,730.54;2933,730.54)|(2933,730.84;2873,730.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,526.54;2933,526.54)|(2933,526.84;2873,526.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2873,542.54;2933,542.54)|(2933,542.84;2873,542.84) 'CUP.3' chiptop_A_track false 1 edge-pair: (2326.84,2;2326.84,62)|(2326.54,62;2326.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2236.84,2;2236.84,62)|(2236.54,62;2236.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2334.84,2;2334.84,62)|(2334.54,62;2334.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2244.84,2;2244.84,62)|(2244.54,62;2244.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2342.84,2;2342.84,62)|(2342.54,62;2342.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2336.84,2;2336.84,62)|(2336.54,62;2336.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2218.84,2;2218.84,62)|(2218.54,62;2218.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2238.84,2;2238.84,62)|(2238.54,62;2238.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2302.84,2;2302.84,62)|(2302.54,62;2302.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2292.84,2;2292.84,62)|(2292.54,62;2292.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2226.84,2;2226.84,62)|(2226.54,62;2226.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2296.84,2;2296.84,62)|(2296.54,62;2296.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2306.84,2;2306.84,62)|(2306.54,62;2306.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2312.84,2;2312.84,62)|(2312.54,62;2312.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2338.84,2;2338.84,62)|(2338.54,62;2338.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2318.84,2;2318.84,62)|(2318.54,62;2318.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2242.84,2;2242.84,62)|(2242.54,62;2242.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2294.84,2;2294.84,62)|(2294.54,62;2294.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2222.84,2;2222.84,62)|(2222.54,62;2222.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2324.84,2;2324.84,62)|(2324.54,62;2324.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2200.84,2;2200.84,62)|(2200.54,62;2200.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2308.84,2;2308.84,62)|(2308.54,62;2308.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2320.84,2;2320.84,62)|(2320.54,62;2320.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2234.84,2;2234.84,62)|(2234.54,62;2234.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2290.84,2;2290.84,62)|(2290.54,62;2290.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2300.84,2;2300.84,62)|(2300.54,62;2300.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2347.5,2;2347.5,62)|(2346.54,62;2346.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2332.84,2;2332.84,62)|(2332.54,62;2332.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2228.84,2;2228.84,62)|(2228.54,62;2228.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2230.84,2;2230.84,62)|(2230.54,62;2230.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2304.84,2;2304.84,62)|(2304.54,62;2304.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2340.84,2;2340.84,62)|(2340.54,62;2340.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2206.84,2;2206.84,62)|(2206.54,62;2206.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2240.84,2;2240.84,62)|(2240.54,62;2240.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2328.84,2;2328.84,62)|(2328.54,62;2328.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2247.5,2;2247.5,62)|(2246.54,62;2246.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2212.84,2;2212.84,62)|(2212.54,62;2212.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2202.84,2;2202.84,62)|(2202.54,62;2202.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2298.84,2;2298.84,62)|(2298.54,62;2298.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2220.84,2;2220.84,62)|(2220.54,62;2220.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2216.84,2;2216.84,62)|(2216.54,62;2216.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2314.84,2;2314.84,62)|(2314.54,62;2314.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2310.84,2;2310.84,62)|(2310.54,62;2310.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2224.84,2;2224.84,62)|(2224.54,62;2224.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2330.84,2;2330.84,62)|(2330.54,62;2330.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2232.84,2;2232.84,62)|(2232.54,62;2232.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2316.84,2;2316.84,62)|(2316.54,62;2316.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2208.84,2;2208.84,62)|(2208.54,62;2208.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2322.84,2;2322.84,62)|(2322.54,62;2322.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2344.84,2;2344.84,62)|(2344.54,62;2344.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2214.84,2;2214.84,62)|(2214.54,62;2214.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2204.84,2;2204.84,62)|(2204.54,62;2204.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2210.84,2;2210.84,62)|(2210.54,62;2210.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2532.84,2;2532.84,62)|(2532.54,62;2532.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2522.84,2;2522.84,62)|(2522.54,62;2522.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2444.84,2;2444.84,62)|(2444.54,62;2444.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2508.84,2;2508.84,62)|(2508.54,62;2508.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2547.5,2;2547.5,62)|(2546.54,62;2546.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2396.84,2;2396.84,62)|(2396.54,62;2396.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2518.84,2;2518.84,62)|(2518.54,62;2518.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2402.84,2;2402.84,62)|(2402.54,62;2402.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2516.84,2;2516.84,62)|(2516.54,62;2516.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2510.84,2;2510.84,62)|(2510.54,62;2510.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2536.84,2;2536.84,62)|(2536.54,62;2536.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2442.84,2;2442.84,62)|(2442.54,62;2442.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2494.84,2;2494.84,62)|(2494.54,62;2494.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2420.84,2;2420.84,62)|(2420.54,62;2420.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2390.84,2;2390.84,62)|(2390.54,62;2390.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2394.84,2;2394.84,62)|(2394.54,62;2394.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2392.84,2;2392.84,62)|(2392.54,62;2392.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2447.5,2;2447.5,62)|(2446.54,62;2446.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2408.84,2;2408.84,62)|(2408.54,62;2408.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2542.84,2;2542.84,62)|(2542.54,62;2542.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2436.84,2;2436.84,62)|(2436.54,62;2436.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2428.84,2;2428.84,62)|(2428.54,62;2428.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2418.84,2;2418.84,62)|(2418.54,62;2418.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2406.84,2;2406.84,62)|(2406.54,62;2406.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2538.84,2;2538.84,62)|(2538.54,62;2538.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2526.84,2;2526.84,62)|(2526.54,62;2526.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2530.84,2;2530.84,62)|(2530.54,62;2530.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2438.84,2;2438.84,62)|(2438.54,62;2438.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2520.84,2;2520.84,62)|(2520.54,62;2520.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2422.84,2;2422.84,62)|(2422.54,62;2422.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2506.84,2;2506.84,62)|(2506.54,62;2506.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2514.84,2;2514.84,62)|(2514.54,62;2514.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2414.84,2;2414.84,62)|(2414.54,62;2414.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2430.84,2;2430.84,62)|(2430.54,62;2430.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2512.84,2;2512.84,62)|(2512.54,62;2512.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2412.84,2;2412.84,62)|(2412.54,62;2412.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2398.84,2;2398.84,62)|(2398.54,62;2398.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2496.84,2;2496.84,62)|(2496.54,62;2496.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2540.84,2;2540.84,62)|(2540.54,62;2540.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2434.84,2;2434.84,62)|(2434.54,62;2434.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2424.84,2;2424.84,62)|(2424.54,62;2424.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2416.84,2;2416.84,62)|(2416.54,62;2416.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2404.84,2;2404.84,62)|(2404.54,62;2404.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2500.84,2;2500.84,62)|(2500.54,62;2500.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2492.84,2;2492.84,62)|(2492.54,62;2492.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2504.84,2;2504.84,62)|(2504.54,62;2504.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2440.84,2;2440.84,62)|(2440.54,62;2440.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2544.84,2;2544.84,62)|(2544.54,62;2544.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2400.84,2;2400.84,62)|(2400.54,62;2400.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2432.84,2;2432.84,62)|(2432.54,62;2432.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2426.84,2;2426.84,62)|(2426.54,62;2426.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2498.84,2;2498.84,62)|(2498.54,62;2498.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2534.84,2;2534.84,62)|(2534.54,62;2534.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2410.84,2;2410.84,62)|(2410.54,62;2410.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2528.84,2;2528.84,62)|(2528.54,62;2528.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2524.84,2;2524.84,62)|(2524.54,62;2524.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2502.84,2;2502.84,62)|(2502.54,62;2502.54,2) 'CUP.3' chiptop_A_track false 1 edge-pair: (2490.84,2;2490.84,62)|(2490.54,62;2490.54,2) 'CUP.3' padring false 1 edge-pair: (1947.5,2;1947.5,62)|(1946.54,62;1946.54,2) 'CUP.3' padring false 1 edge-pair: (1944.84,2;1944.84,62)|(1944.54,62;1944.54,2) 'CUP.3' padring false 1 edge-pair: (1940.84,2;1940.84,62)|(1940.54,62;1940.54,2) 'CUP.3' padring false 1 edge-pair: (1938.84,2;1938.84,62)|(1938.54,62;1938.54,2) 'CUP.3' padring false 1 edge-pair: (1934.84,2;1934.84,62)|(1934.54,62;1934.54,2) 'CUP.3' padring false 1 edge-pair: (1930.84,2;1930.84,62)|(1930.54,62;1930.54,2) 'CUP.3' padring false 1 edge-pair: (1922.84,2;1922.84,62)|(1922.54,62;1922.54,2) 'CUP.3' padring false 1 edge-pair: (1920.84,2;1920.84,62)|(1920.54,62;1920.54,2) 'CUP.3' padring false 1 edge-pair: (1918.84,2;1918.84,62)|(1918.54,62;1918.54,2) 'CUP.3' padring false 1 edge-pair: (1916.84,2;1916.84,62)|(1916.54,62;1916.54,2) 'CUP.3' padring false 1 edge-pair: (1936.84,2;1936.84,62)|(1936.54,62;1936.54,2) 'CUP.3' padring false 1 edge-pair: (1914.84,2;1914.84,62)|(1914.54,62;1914.54,2) 'CUP.3' padring false 1 edge-pair: (1908.84,2;1908.84,62)|(1908.54,62;1908.54,2) 'CUP.3' padring false 1 edge-pair: (1906.84,2;1906.84,62)|(1906.54,62;1906.54,2) 'CUP.3' padring false 1 edge-pair: (1902.84,2;1902.84,62)|(1902.54,62;1902.54,2) 'CUP.3' padring false 1 edge-pair: (1900.84,2;1900.84,62)|(1900.54,62;1900.54,2) 'CUP.3' padring false 1 edge-pair: (1898.84,2;1898.84,62)|(1898.54,62;1898.54,2) 'CUP.3' padring false 1 edge-pair: (1892.84,2;1892.84,62)|(1892.54,62;1892.54,2) 'CUP.3' padring false 1 edge-pair: (647.5,2;647.5,62)|(646.54,62;646.54,2) 'CUP.3' padring false 1 edge-pair: (644.84,2;644.84,62)|(644.54,62;644.54,2) 'CUP.3' padring false 1 edge-pair: (2873,638.54;2933,638.54)|(2933,638.84;2873,638.84) 'CUP.3' padring false 1 edge-pair: (2873,594.54;2933,594.54)|(2933,594.84;2873,594.84) 'CUP.3' padring false 1 edge-pair: (2873,642.54;2933,642.54)|(2933,642.84;2873,642.84) 'CUP.3' padring false 1 edge-pair: (2873,630.54;2933,630.54)|(2933,630.84;2873,630.84) 'CUP.3' padring false 1 edge-pair: (612.84,2;612.84,62)|(612.54,62;612.54,2) 'CUP.3' padring false 1 edge-pair: (614.84,2;614.84,62)|(614.54,62;614.54,2) 'CUP.3' padring false 1 edge-pair: (2873,618.54;2933,618.54)|(2933,618.84;2873,618.84) 'CUP.3' padring false 1 edge-pair: (2873,628.54;2933,628.54)|(2933,628.84;2873,628.84) 'CUP.3' padring false 1 edge-pair: (2873,590.54;2933,590.54)|(2933,590.84;2873,590.84) 'CUP.3' padring false 1 edge-pair: (1904.84,2;1904.84,62)|(1904.54,62;1904.54,2) 'CUP.3' padring false 1 edge-pair: (2873,622.54;2933,622.54)|(2933,622.84;2873,622.84) 'CUP.3' padring false 1 edge-pair: (2873,606.54;2933,606.54)|(2933,606.84;2873,606.84) 'CUP.3' padring false 1 edge-pair: (2873,602.54;2933,602.54)|(2933,602.84;2873,602.84) 'CUP.3' padring false 1 edge-pair: (2873,598.54;2933,598.54)|(2933,598.84;2873,598.84) 'CUP.3' padring false 1 edge-pair: (2873,632.54;2933,632.54)|(2933,632.84;2873,632.84) 'CUP.3' padring false 1 edge-pair: (1910.84,2;1910.84,62)|(1910.54,62;1910.54,2) 'CUP.3' padring false 1 edge-pair: (2873,616.54;2933,616.54)|(2933,616.84;2873,616.84) 'CUP.3' padring false 1 edge-pair: (2873,596.54;2933,596.54)|(2933,596.84;2873,596.84) 'CUP.3' padring false 1 edge-pair: (620.84,2;620.84,62)|(620.54,62;620.54,2) 'CUP.3' padring false 1 edge-pair: (2873,636.54;2933,636.54)|(2933,636.84;2873,636.84) 'CUP.3' padring false 1 edge-pair: (634.84,2;634.84,62)|(634.54,62;634.54,2) 'CUP.3' padring false 1 edge-pair: (1928.84,2;1928.84,62)|(1928.54,62;1928.54,2) 'CUP.3' padring false 1 edge-pair: (1924.84,2;1924.84,62)|(1924.54,62;1924.54,2) 'CUP.3' padring false 1 edge-pair: (2873,610.54;2933,610.54)|(2933,610.84;2873,610.84) 'CUP.3' padring false 1 edge-pair: (2873,646.54;2933,646.54)|(2933,647.5;2873,647.5) 'CUP.3' padring false 1 edge-pair: (2873,626.54;2933,626.54)|(2933,626.84;2873,626.84) 'CUP.3' padring false 1 edge-pair: (2873,592.54;2933,592.54)|(2933,592.84;2873,592.84) 'CUP.3' padring false 1 edge-pair: (600.84,2;600.84,62)|(600.54,62;600.54,2) 'CUP.3' padring false 1 edge-pair: (2873,634.54;2933,634.54)|(2933,634.84;2873,634.84) 'CUP.3' padring false 1 edge-pair: (630.84,2;630.84,62)|(630.54,62;630.54,2) 'CUP.3' padring false 1 edge-pair: (608.84,2;608.84,62)|(608.54,62;608.54,2) 'CUP.3' padring false 1 edge-pair: (606.84,2;606.84,62)|(606.54,62;606.54,2) 'CUP.3' padring false 1 edge-pair: (2873,608.54;2933,608.54)|(2933,608.84;2873,608.84) 'CUP.3' padring false 1 edge-pair: (2873,640.54;2933,640.54)|(2933,640.84;2873,640.84) 'CUP.3' padring false 1 edge-pair: (2873,600.54;2933,600.54)|(2933,600.84;2873,600.84) 'CUP.3' padring false 1 edge-pair: (2873,644.54;2933,644.54)|(2933,644.84;2873,644.84) 'CUP.3' padring false 1 edge-pair: (622.84,2;622.84,62)|(622.54,62;622.54,2) 'CUP.3' padring false 1 edge-pair: (1942.84,2;1942.84,62)|(1942.54,62;1942.54,2) 'CUP.3' padring false 1 edge-pair: (642.84,2;642.84,62)|(642.54,62;642.54,2) 'CUP.3' padring false 1 edge-pair: (2873,612.54;2933,612.54)|(2933,612.84;2873,612.84) 'CUP.3' padring false 1 edge-pair: (638.84,2;638.84,62)|(638.54,62;638.54,2) 'CUP.3' padring false 1 edge-pair: (636.84,2;636.84,62)|(636.54,62;636.54,2) 'CUP.3' padring false 1 edge-pair: (1912.84,2;1912.84,62)|(1912.54,62;1912.54,2) 'CUP.3' padring false 1 edge-pair: (618.84,2;618.84,62)|(618.54,62;618.54,2) 'CUP.3' padring false 1 edge-pair: (1894.84,2;1894.84,62)|(1894.54,62;1894.54,2) 'CUP.3' padring false 1 edge-pair: (632.84,2;632.84,62)|(632.54,62;632.54,2) 'CUP.3' padring false 1 edge-pair: (1932.84,2;1932.84,62)|(1932.54,62;1932.54,2) 'CUP.3' padring false 1 edge-pair: (628.84,2;628.84,62)|(628.54,62;628.54,2) 'CUP.3' padring false 1 edge-pair: (626.84,2;626.84,62)|(626.54,62;626.54,2) 'CUP.3' padring false 1 edge-pair: (2873,604.54;2933,604.54)|(2933,604.84;2873,604.84) 'CUP.3' padring false 1 edge-pair: (624.84,2;624.84,62)|(624.54,62;624.54,2) 'CUP.3' padring false 1 edge-pair: (596.84,2;596.84,62)|(596.54,62;596.54,2) 'CUP.3' padring false 1 edge-pair: (1896.84,2;1896.84,62)|(1896.54,62;1896.54,2) 'CUP.3' padring false 1 edge-pair: (2873,624.54;2933,624.54)|(2933,624.84;2873,624.84) 'CUP.3' padring false 1 edge-pair: (2873,620.54;2933,620.54)|(2933,620.84;2873,620.84) 'CUP.3' padring false 1 edge-pair: (616.84,2;616.84,62)|(616.54,62;616.54,2) 'CUP.3' padring false 1 edge-pair: (590.84,2;590.84,62)|(590.54,62;590.54,2) 'CUP.3' padring false 1 edge-pair: (598.84,2;598.84,62)|(598.54,62;598.54,2) 'CUP.3' padring false 1 edge-pair: (2873,614.54;2933,614.54)|(2933,614.84;2873,614.84) 'CUP.3' padring false 1 edge-pair: (592.84,2;592.84,62)|(592.54,62;592.54,2) 'CUP.3' padring false 1 edge-pair: (602.84,2;602.84,62)|(602.54,62;602.54,2) 'CUP.3' padring false 1 edge-pair: (604.84,2;604.84,62)|(604.54,62;604.54,2) 'CUP.3' padring false 1 edge-pair: (610.84,2;610.84,62)|(610.54,62;610.54,2) 'CUP.3' padring false 1 edge-pair: (1926.84,2;1926.84,62)|(1926.54,62;1926.54,2) 'CUP.3' padring false 1 edge-pair: (594.84,2;594.84,62)|(594.54,62;594.54,2) 'CUP.3' padring false 1 edge-pair: (640.84,2;640.84,62)|(640.54,62;640.54,2) 'CUP.3' padring false 1 edge-pair: (1890.84,2;1890.84,62)|(1890.54,62;1890.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (32.84,2;32.84,62)|(32.54,62;32.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (26.84,2;26.84,62)|(26.54,62;26.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (24.84,2;24.84,62)|(24.54,62;24.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (22.84,2;22.84,62)|(22.54,62;22.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (20.84,2;20.84,62)|(20.54,62;20.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (18.84,2;18.84,62)|(18.54,62;18.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (14.84,2;14.84,62)|(14.54,62;14.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (12.84,2;12.84,62)|(12.54,62;12.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (10.84,2;10.84,62)|(10.54,62;10.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (36.84,2;36.84,62)|(36.54,62;36.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (38.84,2;38.84,62)|(38.54,62;38.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (40.84,2;40.84,62)|(40.54,62;40.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (16.84,2;16.84,62)|(16.54,62;16.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (67.5,2;67.5,62)|(66.54,62;66.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (28.84,2;28.84,62)|(28.54,62;28.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (54.84,2;54.84,62)|(54.54,62;54.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (34.84,2;34.84,62)|(34.54,62;34.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (64.84,2;64.84,62)|(64.54,62;64.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (60.84,2;60.84,62)|(60.54,62;60.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (58.84,2;58.84,62)|(58.54,62;58.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (48.84,2;48.84,62)|(48.54,62;48.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (30.84,2;30.84,62)|(30.54,62;30.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (56.84,2;56.84,62)|(56.54,62;56.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (52.84,2;52.84,62)|(52.54,62;52.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (50.84,2;50.84,62)|(50.54,62;50.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (46.84,2;46.84,62)|(46.54,62;46.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (44.84,2;44.84,62)|(44.54,62;44.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (62.84,2;62.84,62)|(62.54,62;62.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r90 false 1 edge-pair: (42.84,2;42.84,62)|(42.54,62;42.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (32.84,2;32.84,62)|(32.54,62;32.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (26.84,2;26.84,62)|(26.54,62;26.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (24.84,2;24.84,62)|(24.54,62;24.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (22.84,2;22.84,62)|(22.54,62;22.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (20.84,2;20.84,62)|(20.54,62;20.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (18.84,2;18.84,62)|(18.54,62;18.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (14.84,2;14.84,62)|(14.54,62;14.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (12.84,2;12.84,62)|(12.54,62;12.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (10.84,2;10.84,62)|(10.54,62;10.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (36.84,2;36.84,62)|(36.54,62;36.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (38.84,2;38.84,62)|(38.54,62;38.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (40.84,2;40.84,62)|(40.54,62;40.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (16.84,2;16.84,62)|(16.54,62;16.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (67.5,2;67.5,62)|(66.54,62;66.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (28.84,2;28.84,62)|(28.54,62;28.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (54.84,2;54.84,62)|(54.54,62;54.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (34.84,2;34.84,62)|(34.54,62;34.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (64.84,2;64.84,62)|(64.54,62;64.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (60.84,2;60.84,62)|(60.54,62;60.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (58.84,2;58.84,62)|(58.54,62;58.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (48.84,2;48.84,62)|(48.54,62;48.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (30.84,2;30.84,62)|(30.54,62;30.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (56.84,2;56.84,62)|(56.54,62;56.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (52.84,2;52.84,62)|(52.54,62;52.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (50.84,2;50.84,62)|(50.54,62;50.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (46.84,2;46.84,62)|(46.54,62;46.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (44.84,2;44.84,62)|(44.54,62;44.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (62.84,2;62.84,62)|(62.54,62;62.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r180 false 1 edge-pair: (42.84,2;42.84,62)|(42.54,62;42.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (32.84,2;32.84,62)|(32.54,62;32.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (26.84,2;26.84,62)|(26.54,62;26.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (24.84,2;24.84,62)|(24.54,62;24.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (22.84,2;22.84,62)|(22.54,62;22.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (20.84,2;20.84,62)|(20.54,62;20.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (18.84,2;18.84,62)|(18.54,62;18.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (14.84,2;14.84,62)|(14.54,62;14.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (12.84,2;12.84,62)|(12.54,62;12.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (10.84,2;10.84,62)|(10.54,62;10.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (36.84,2;36.84,62)|(36.54,62;36.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (38.84,2;38.84,62)|(38.54,62;38.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (40.84,2;40.84,62)|(40.54,62;40.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (16.84,2;16.84,62)|(16.54,62;16.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (67.5,2;67.5,62)|(66.54,62;66.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (28.84,2;28.84,62)|(28.54,62;28.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (54.84,2;54.84,62)|(54.54,62;54.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (34.84,2;34.84,62)|(34.54,62;34.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (64.84,2;64.84,62)|(64.54,62;64.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (60.84,2;60.84,62)|(60.54,62;60.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (58.84,2;58.84,62)|(58.54,62;58.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (48.84,2;48.84,62)|(48.54,62;48.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (30.84,2;30.84,62)|(30.54,62;30.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (56.84,2;56.84,62)|(56.54,62;56.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (52.84,2;52.84,62)|(52.54,62;52.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (50.84,2;50.84,62)|(50.54,62;50.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (46.84,2;46.84,62)|(46.54,62;46.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (44.84,2;44.84,62)|(44.54,62;44.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (62.84,2;62.84,62)|(62.54,62;62.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r0 false 1 edge-pair: (42.84,2;42.84,62)|(42.54,62;42.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (32.84,2;32.84,62)|(32.54,62;32.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (26.84,2;26.84,62)|(26.54,62;26.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (24.84,2;24.84,62)|(24.54,62;24.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (22.84,2;22.84,62)|(22.54,62;22.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (20.84,2;20.84,62)|(20.54,62;20.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (18.84,2;18.84,62)|(18.54,62;18.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (14.84,2;14.84,62)|(14.54,62;14.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (12.84,2;12.84,62)|(12.54,62;12.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (10.84,2;10.84,62)|(10.54,62;10.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (36.84,2;36.84,62)|(36.54,62;36.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (38.84,2;38.84,62)|(38.54,62;38.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (40.84,2;40.84,62)|(40.54,62;40.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (16.84,2;16.84,62)|(16.54,62;16.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (67.5,2;67.5,62)|(66.54,62;66.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (28.84,2;28.84,62)|(28.54,62;28.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (54.84,2;54.84,62)|(54.54,62;54.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (34.84,2;34.84,62)|(34.54,62;34.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (64.84,2;64.84,62)|(64.54,62;64.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (60.84,2;60.84,62)|(60.54,62;60.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (58.84,2;58.84,62)|(58.54,62;58.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (48.84,2;48.84,62)|(48.54,62;48.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (30.84,2;30.84,62)|(30.54,62;30.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (56.84,2;56.84,62)|(56.54,62;56.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (52.84,2;52.84,62)|(52.54,62;52.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (50.84,2;50.84,62)|(50.54,62;50.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (46.84,2;46.84,62)|(46.54,62;46.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (44.84,2;44.84,62)|(44.54,62;44.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (62.84,2;62.84,62)|(62.54,62;62.54,2) 'CUP.3' gf180mcu_fd_io__bi_t$2:r270 false 1 edge-pair: (42.84,2;42.84,62)|(42.54,62;42.54,2) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (29.34,2.29;29.34,61.6)|(29.04,61.6;29.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (27.34,2.29;27.34,61.6)|(27.04,61.6;27.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (25.34,2.29;25.34,61.6)|(25.04,61.6;25.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (23.34,2.29;23.34,61.6)|(23.04,61.6;23.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (19.34,2.29;19.34,61.6)|(19.04,61.6;19.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (17.34,2.29;17.34,61.6)|(17.04,61.6;17.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (21.34,2.29;21.34,61.6)|(21.04,61.6;21.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (11.34,2.29;11.34,61.6)|(11.04,61.6;11.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (15.34,2.29;15.34,61.6)|(15.04,61.6;15.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (7.34,2.29;7.34,61.6)|(7.04,61.6;7.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (5.34,2.29;5.34,61.6)|(5.04,61.6;5.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (13.34,2.29;13.34,61.6)|(13.04,61.6;13.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (33.34,2.29;33.34,61.6)|(33.04,61.6;33.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (59.34,2.29;59.34,61.6)|(59.04,61.6;59.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (57.34,2.29;57.34,61.6)|(57.04,61.6;57.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (9.34,2.29;9.34,61.6)|(9.04,61.6;9.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (55.34,2.29;55.34,61.6)|(55.04,61.6;55.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (53.34,2.29;53.34,61.6)|(53.04,61.6;53.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (62,2.29;62,61.6)|(61.04,61.6;61.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (37.34,2.29;37.34,61.6)|(37.04,61.6;37.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (51.34,2.29;51.34,61.6)|(51.04,61.6;51.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (45.34,2.29;45.34,61.6)|(45.04,61.6;45.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (49.34,2.29;49.34,61.6)|(49.04,61.6;49.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (31.34,2.29;31.34,61.6)|(31.04,61.6;31.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (35.34,2.29;35.34,61.6)|(35.04,61.6;35.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (47.34,2.29;47.34,61.6)|(47.04,61.6;47.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (43.34,2.29;43.34,61.6)|(43.04,61.6;43.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (39.34,2.29;39.34,61.6)|(39.04,61.6;39.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (41.34,2.29;41.34,61.6)|(41.04,61.6;41.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (29.34,2.29;29.34,61.6)|(29.04,61.6;29.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (27.34,2.29;27.34,61.6)|(27.04,61.6;27.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (25.34,2.29;25.34,61.6)|(25.04,61.6;25.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (23.34,2.29;23.34,61.6)|(23.04,61.6;23.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (19.34,2.29;19.34,61.6)|(19.04,61.6;19.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (17.34,2.29;17.34,61.6)|(17.04,61.6;17.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (21.34,2.29;21.34,61.6)|(21.04,61.6;21.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (11.34,2.29;11.34,61.6)|(11.04,61.6;11.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (15.34,2.29;15.34,61.6)|(15.04,61.6;15.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (7.34,2.29;7.34,61.6)|(7.04,61.6;7.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (5.34,2.29;5.34,61.6)|(5.04,61.6;5.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (13.34,2.29;13.34,61.6)|(13.04,61.6;13.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (33.34,2.29;33.34,61.6)|(33.04,61.6;33.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (59.34,2.29;59.34,61.6)|(59.04,61.6;59.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (57.34,2.29;57.34,61.6)|(57.04,61.6;57.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (9.34,2.29;9.34,61.6)|(9.04,61.6;9.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (55.34,2.29;55.34,61.6)|(55.04,61.6;55.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (53.34,2.29;53.34,61.6)|(53.04,61.6;53.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (62,2.29;62,61.6)|(61.04,61.6;61.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (37.34,2.29;37.34,61.6)|(37.04,61.6;37.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (51.34,2.29;51.34,61.6)|(51.04,61.6;51.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (45.34,2.29;45.34,61.6)|(45.04,61.6;45.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (49.34,2.29;49.34,61.6)|(49.04,61.6;49.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (31.34,2.29;31.34,61.6)|(31.04,61.6;31.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (35.34,2.29;35.34,61.6)|(35.04,61.6;35.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (47.34,2.29;47.34,61.6)|(47.04,61.6;47.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (43.34,2.29;43.34,61.6)|(43.04,61.6;43.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (39.34,2.29;39.34,61.6)|(39.04,61.6;39.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (41.34,2.29;41.34,61.6)|(41.04,61.6;41.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (29.34,2.29;29.34,61.6)|(29.04,61.6;29.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (27.34,2.29;27.34,61.6)|(27.04,61.6;27.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (25.34,2.29;25.34,61.6)|(25.04,61.6;25.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (23.34,2.29;23.34,61.6)|(23.04,61.6;23.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (19.34,2.29;19.34,61.6)|(19.04,61.6;19.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (17.34,2.29;17.34,61.6)|(17.04,61.6;17.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (21.34,2.29;21.34,61.6)|(21.04,61.6;21.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (11.34,2.29;11.34,61.6)|(11.04,61.6;11.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (15.34,2.29;15.34,61.6)|(15.04,61.6;15.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (7.34,2.29;7.34,61.6)|(7.04,61.6;7.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (5.34,2.29;5.34,61.6)|(5.04,61.6;5.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (13.34,2.29;13.34,61.6)|(13.04,61.6;13.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (33.34,2.29;33.34,61.6)|(33.04,61.6;33.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (59.34,2.29;59.34,61.6)|(59.04,61.6;59.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (57.34,2.29;57.34,61.6)|(57.04,61.6;57.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (9.34,2.29;9.34,61.6)|(9.04,61.6;9.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (55.34,2.29;55.34,61.6)|(55.04,61.6;55.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (53.34,2.29;53.34,61.6)|(53.04,61.6;53.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (62,2.29;62,61.6)|(61.04,61.6;61.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (37.34,2.29;37.34,61.6)|(37.04,61.6;37.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (51.34,2.29;51.34,61.6)|(51.04,61.6;51.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (45.34,2.29;45.34,61.6)|(45.04,61.6;45.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (49.34,2.29;49.34,61.6)|(49.04,61.6;49.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (31.34,2.29;31.34,61.6)|(31.04,61.6;31.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (35.34,2.29;35.34,61.6)|(35.04,61.6;35.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (47.34,2.29;47.34,61.6)|(47.04,61.6;47.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (43.34,2.29;43.34,61.6)|(43.04,61.6;43.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (39.34,2.29;39.34,61.6)|(39.04,61.6;39.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (41.34,2.29;41.34,61.6)|(41.04,61.6;41.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (29.34,2.29;29.34,61.6)|(29.04,61.6;29.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (27.34,2.29;27.34,61.6)|(27.04,61.6;27.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (25.34,2.29;25.34,61.6)|(25.04,61.6;25.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (23.34,2.29;23.34,61.6)|(23.04,61.6;23.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (19.34,2.29;19.34,61.6)|(19.04,61.6;19.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (17.34,2.29;17.34,61.6)|(17.04,61.6;17.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (21.34,2.29;21.34,61.6)|(21.04,61.6;21.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (11.34,2.29;11.34,61.6)|(11.04,61.6;11.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (15.34,2.29;15.34,61.6)|(15.04,61.6;15.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (7.34,2.29;7.34,61.6)|(7.04,61.6;7.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (5.34,2.29;5.34,61.6)|(5.04,61.6;5.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (13.34,2.29;13.34,61.6)|(13.04,61.6;13.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (33.34,2.29;33.34,61.6)|(33.04,61.6;33.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (59.34,2.29;59.34,61.6)|(59.04,61.6;59.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (57.34,2.29;57.34,61.6)|(57.04,61.6;57.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (9.34,2.29;9.34,61.6)|(9.04,61.6;9.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (55.34,2.29;55.34,61.6)|(55.04,61.6;55.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (53.34,2.29;53.34,61.6)|(53.04,61.6;53.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (62,2.29;62,61.6)|(61.04,61.6;61.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (37.34,2.29;37.34,61.6)|(37.04,61.6;37.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (51.34,2.29;51.34,61.6)|(51.04,61.6;51.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (45.34,2.29;45.34,61.6)|(45.04,61.6;45.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (49.34,2.29;49.34,61.6)|(49.04,61.6;49.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (31.34,2.29;31.34,61.6)|(31.04,61.6;31.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (35.34,2.29;35.34,61.6)|(35.04,61.6;35.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (47.34,2.29;47.34,61.6)|(47.04,61.6;47.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (43.34,2.29;43.34,61.6)|(43.04,61.6;43.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (39.34,2.29;39.34,61.6)|(39.04,61.6;39.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (41.34,2.29;41.34,61.6)|(41.04,61.6;41.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (29.34,2.29;29.34,61.6)|(29.04,61.6;29.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (27.34,2.29;27.34,61.6)|(27.04,61.6;27.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (25.34,2.29;25.34,61.6)|(25.04,61.6;25.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (23.34,2.29;23.34,61.6)|(23.04,61.6;23.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (19.34,2.29;19.34,61.6)|(19.04,61.6;19.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (17.34,2.29;17.34,61.6)|(17.04,61.6;17.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (21.34,2.29;21.34,61.6)|(21.04,61.6;21.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (11.34,2.29;11.34,61.6)|(11.04,61.6;11.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (15.34,2.29;15.34,61.6)|(15.04,61.6;15.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (7.34,2.29;7.34,61.6)|(7.04,61.6;7.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (5.34,2.29;5.34,61.6)|(5.04,61.6;5.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (13.34,2.29;13.34,61.6)|(13.04,61.6;13.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (33.34,2.29;33.34,61.6)|(33.04,61.6;33.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (59.34,2.29;59.34,61.6)|(59.04,61.6;59.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (57.34,2.29;57.34,61.6)|(57.04,61.6;57.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (9.34,2.29;9.34,61.6)|(9.04,61.6;9.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (55.34,2.29;55.34,61.6)|(55.04,61.6;55.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (53.34,2.29;53.34,61.6)|(53.04,61.6;53.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (62,2.29;62,61.6)|(61.04,61.6;61.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (37.34,2.29;37.34,61.6)|(37.04,61.6;37.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (51.34,2.29;51.34,61.6)|(51.04,61.6;51.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (45.34,2.29;45.34,61.6)|(45.04,61.6;45.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (49.34,2.29;49.34,61.6)|(49.04,61.6;49.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (31.34,2.29;31.34,61.6)|(31.04,61.6;31.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (35.34,2.29;35.34,61.6)|(35.04,61.6;35.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (47.34,2.29;47.34,61.6)|(47.04,61.6;47.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (43.34,2.29;43.34,61.6)|(43.04,61.6;43.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (39.34,2.29;39.34,61.6)|(39.04,61.6;39.04,2.29) 'CUP.3' Bondpad_5LM$2:r90 false 1 edge-pair: (41.34,2.29;41.34,61.6)|(41.04,61.6;41.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (29.34,2.29;29.34,61.6)|(29.04,61.6;29.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (27.34,2.29;27.34,61.6)|(27.04,61.6;27.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (25.34,2.29;25.34,61.6)|(25.04,61.6;25.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (23.34,2.29;23.34,61.6)|(23.04,61.6;23.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (19.34,2.29;19.34,61.6)|(19.04,61.6;19.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (17.34,2.29;17.34,61.6)|(17.04,61.6;17.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (21.34,2.29;21.34,61.6)|(21.04,61.6;21.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (11.34,2.29;11.34,61.6)|(11.04,61.6;11.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (15.34,2.29;15.34,61.6)|(15.04,61.6;15.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (7.34,2.29;7.34,61.6)|(7.04,61.6;7.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (5.34,2.29;5.34,61.6)|(5.04,61.6;5.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (13.34,2.29;13.34,61.6)|(13.04,61.6;13.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (33.34,2.29;33.34,61.6)|(33.04,61.6;33.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (59.34,2.29;59.34,61.6)|(59.04,61.6;59.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (57.34,2.29;57.34,61.6)|(57.04,61.6;57.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (9.34,2.29;9.34,61.6)|(9.04,61.6;9.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (55.34,2.29;55.34,61.6)|(55.04,61.6;55.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (53.34,2.29;53.34,61.6)|(53.04,61.6;53.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (62,2.29;62,61.6)|(61.04,61.6;61.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (37.34,2.29;37.34,61.6)|(37.04,61.6;37.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (51.34,2.29;51.34,61.6)|(51.04,61.6;51.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (45.34,2.29;45.34,61.6)|(45.04,61.6;45.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (49.34,2.29;49.34,61.6)|(49.04,61.6;49.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (31.34,2.29;31.34,61.6)|(31.04,61.6;31.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (35.34,2.29;35.34,61.6)|(35.04,61.6;35.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (47.34,2.29;47.34,61.6)|(47.04,61.6;47.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (43.34,2.29;43.34,61.6)|(43.04,61.6;43.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (39.34,2.29;39.34,61.6)|(39.04,61.6;39.04,2.29) 'CUP.3' Bondpad_5LM$2:r180 false 1 edge-pair: (41.34,2.29;41.34,61.6)|(41.04,61.6;41.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (29.34,2.29;29.34,61.6)|(29.04,61.6;29.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (27.34,2.29;27.34,61.6)|(27.04,61.6;27.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (25.34,2.29;25.34,61.6)|(25.04,61.6;25.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (23.34,2.29;23.34,61.6)|(23.04,61.6;23.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (19.34,2.29;19.34,61.6)|(19.04,61.6;19.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (17.34,2.29;17.34,61.6)|(17.04,61.6;17.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (21.34,2.29;21.34,61.6)|(21.04,61.6;21.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (11.34,2.29;11.34,61.6)|(11.04,61.6;11.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (15.34,2.29;15.34,61.6)|(15.04,61.6;15.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (7.34,2.29;7.34,61.6)|(7.04,61.6;7.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (5.34,2.29;5.34,61.6)|(5.04,61.6;5.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (13.34,2.29;13.34,61.6)|(13.04,61.6;13.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (33.34,2.29;33.34,61.6)|(33.04,61.6;33.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (59.34,2.29;59.34,61.6)|(59.04,61.6;59.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (57.34,2.29;57.34,61.6)|(57.04,61.6;57.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (9.34,2.29;9.34,61.6)|(9.04,61.6;9.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (55.34,2.29;55.34,61.6)|(55.04,61.6;55.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (53.34,2.29;53.34,61.6)|(53.04,61.6;53.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (62,2.29;62,61.6)|(61.04,61.6;61.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (37.34,2.29;37.34,61.6)|(37.04,61.6;37.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (51.34,2.29;51.34,61.6)|(51.04,61.6;51.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (45.34,2.29;45.34,61.6)|(45.04,61.6;45.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (49.34,2.29;49.34,61.6)|(49.04,61.6;49.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (31.34,2.29;31.34,61.6)|(31.04,61.6;31.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (35.34,2.29;35.34,61.6)|(35.04,61.6;35.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (47.34,2.29;47.34,61.6)|(47.04,61.6;47.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (43.34,2.29;43.34,61.6)|(43.04,61.6;43.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (39.34,2.29;39.34,61.6)|(39.04,61.6;39.04,2.29) 'CUP.3' Bondpad_5LM$2:r270 false 1 edge-pair: (41.34,2.29;41.34,61.6)|(41.04,61.6;41.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (29.34,2.29;29.34,61.6)|(29.04,61.6;29.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (27.34,2.29;27.34,61.6)|(27.04,61.6;27.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (25.34,2.29;25.34,61.6)|(25.04,61.6;25.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (23.34,2.29;23.34,61.6)|(23.04,61.6;23.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (19.34,2.29;19.34,61.6)|(19.04,61.6;19.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (17.34,2.29;17.34,61.6)|(17.04,61.6;17.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (21.34,2.29;21.34,61.6)|(21.04,61.6;21.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (11.34,2.29;11.34,61.6)|(11.04,61.6;11.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (15.34,2.29;15.34,61.6)|(15.04,61.6;15.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (7.34,2.29;7.34,61.6)|(7.04,61.6;7.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (5.34,2.29;5.34,61.6)|(5.04,61.6;5.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (13.34,2.29;13.34,61.6)|(13.04,61.6;13.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (33.34,2.29;33.34,61.6)|(33.04,61.6;33.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (59.34,2.29;59.34,61.6)|(59.04,61.6;59.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (57.34,2.29;57.34,61.6)|(57.04,61.6;57.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (9.34,2.29;9.34,61.6)|(9.04,61.6;9.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (55.34,2.29;55.34,61.6)|(55.04,61.6;55.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (53.34,2.29;53.34,61.6)|(53.04,61.6;53.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (62,2.29;62,61.6)|(61.04,61.6;61.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (37.34,2.29;37.34,61.6)|(37.04,61.6;37.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (51.34,2.29;51.34,61.6)|(51.04,61.6;51.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (45.34,2.29;45.34,61.6)|(45.04,61.6;45.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (49.34,2.29;49.34,61.6)|(49.04,61.6;49.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (31.34,2.29;31.34,61.6)|(31.04,61.6;31.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (35.34,2.29;35.34,61.6)|(35.04,61.6;35.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (47.34,2.29;47.34,61.6)|(47.04,61.6;47.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (43.34,2.29;43.34,61.6)|(43.04,61.6;43.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (39.34,2.29;39.34,61.6)|(39.04,61.6;39.04,2.29) 'CUP.3' Bondpad_5LM$2:r0 false 1 edge-pair: (41.34,2.29;41.34,61.6)|(41.04,61.6;41.04,2.29)